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2025-06-24 15:51:28 +02:00
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390
package/boot/uboot-lantiq/Makefile Normal file
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#
# Copyright (C) 2012-2013 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=u-boot
PKG_VERSION:=2013.10
PKG_RELEASE:=1
PKG_HASH:=0d71e62beb952b41ebafb20a7ee4df2f960db64c31b054721ceb79ff14014c55
FIRMWARE_LANTIQ_SOURCE:=$(TOPDIR)/target/linux/lantiq/files/firmware/lantiq
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=lantiq
DDR_SETTINGS:=
endef
define U-Boot/arv4519pw_ram
NAME:=Arcadyan arv4519pw (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4519pw
DDR_SETTINGS:=board/arcadyan/arv4519pw/ddr_settings.h
endef
define U-Boot/arv4519pw_nor
NAME:=Arcadyan arv4519pw (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4519pw
endef
define U-Boot/arv4519pw_brn
NAME:=Arcadyan arv4519pw (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4519pw
endef
define U-Boot/arv7506pw11_ram
NAME:=Arcadyan ARV7506PW11 (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7506pw11
DDR_SETTINGS:=board/arcadyan/arv7506pw11/ddr_settings.h
endef
define U-Boot/arv7506pw11_nor
NAME:=Arcadyan ARV7506PW11 (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7506pw11
endef
define U-Boot/arv7506pw11_brn
NAME:=Arcadyan ARV7506PW11 (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7506pw11
endef
define U-Boot/arv7510pw_ram
NAME:=Arcadyan arv7510pw (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4510pw
DDR_SETTINGS:=board/arcadyan/arv7510pw/ddr_settings.h
endef
define U-Boot/arv7510pw_nor
NAME:=Arcadyan arv7510pw (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4510pw
endef
define U-Boot/arv7510pw_brn
NAME:=Arcadyan arv7510pw (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv4510pw
endef
define U-Boot/arv7510pw22_ram
NAME:=Arcadyan arv7510pw22 (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7510pw22
DDR_SETTINGS:=board/arcadyan/arv7510pw22/ddr_settings.h
endef
define U-Boot/arv7510pw22_nor
NAME:=Arcadyan arv7510pw22 (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7510pw22
endef
define U-Boot/arv7510pw22_brn
NAME:=Arcadyan arv7510pw22 (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7510pw22
endef
define U-Boot/arv7518pw_ram
NAME:=Arcadyan arv7518pw (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7518pw
DDR_SETTINGS:=board/arcadyan/arv7518pw/ddr_settings.h
endef
define U-Boot/arv7518pw_nor
NAME:=Arcadyan arv7518pw (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7518pw
endef
define U-Boot/arv7518pw_brn
NAME:=Arcadyan arv7518pw (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv7518pw
endef
define U-Boot/arv752dpw_ram
NAME:=Arcadyan arv752dpw (RAM)
BUILD_SUBTARGET:=xway
DDR_SETTINGS:=board/arcadyan/arv752dpw/ddr_settings.h
BUILD_DEVICES:=arcadyan_arv752dpw
endef
define U-Boot/arv752dpw_nor
NAME:=Arcadyan arv752dpw (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv752dpw
endef
define U-Boot/arv752dpw_brn
NAME:=Arcadyan arv752dpw (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv752dpw
endef
define U-Boot/arv752dpw22_ram
NAME:=Arcadyan arv752dpw22 (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv752dpw22
DDR_SETTINGS:=board/arcadyan/arv752dpw22/ddr_settings.h
endef
define U-Boot/arv752dpw22_nor
NAME:=Arcadyan arv752dpw22 (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv752dpw22
endef
define U-Boot/arv752dpw22_brn
NAME:=Arcadyan arv752dpw22 (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv752dpw22
endef
define U-Boot/arv8539pw22_ram
NAME:=Speedport W 504V Typ A (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv8539pw22
DDR_SETTINGS:=board/arcadyan/arv8539pw22/ddr_settings.h
endef
define U-Boot/arv8539pw22_nor
NAME:=Speedport W 504V Typ A (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv8539pw22
endef
define U-Boot/arv8539pw22_brn
NAME:=Speedport W 504V Typ A (BRN)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=arcadyan_arv8539pw22
endef
define U-Boot/gigasx76x_ram
NAME:=Siemens Gigaset sx76x (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=siemens_gigaset-sx76x
DDR_SETTINGS:=board/gigaset/sx76x/ddr_settings.h
endef
define U-Boot/gigasx76x_nor
NAME:=Siemens Gigaset sx76x (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=siemens_gigaset-sx76x
endef
define U-Boot/acmp252_ram
NAME:=AudioCodes MP-252 (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=audiocodes_mp-252
DDR_SETTINGS:=board/audiocodes/acmp252/ddr_settings.h
endef
define U-Boot/acmp252_nor
NAME:=AudioCodes MP-252 (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=audiocodes_mp-252
endef
define U-Boot/bthomehubv5a_ram
NAME:=BT Home Hub 5A (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=bt_homehub-v5a
DDR_SETTINGS:=board/bt/bthomehubv5a/ddr_settings.h
endef
define U-Boot/easy50712_ram
NAME:=Lantiq EASY50712 (RAM)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=lantiq_easy50712
DDR_SETTINGS:=board/lantiq/easy50712/ddr_settings.h
endef
define U-Boot/easy50712_nor
NAME:=Lantiq EASY50712 (NOR)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=lantiq_easy50712
endef
define U-Boot/easy50712_norspl
NAME:=Lantiq EASY50712 (NOR SPL)
BUILD_SUBTARGET:=xway
BUILD_DEVICES:=lantiq_easy50712
UBOOT_IMAGE:=u-boot.ltq.lzo.norspl
DEPENDS+=@BROKEN
endef
define U-Boot/easy80920_ram
NAME:=Lantiq EASY80920 (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand
DDR_SETTINGS:=board/lantiq/easy80920/ddr_settings.h
endef
define U-Boot/easy80920_nor
NAME:=Lantiq EASY80920 (NOR)
BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand
BUILD_SUBTARGET:=xrx200
endef
define U-Boot/easy80920_norspl
NAME:=Lantiq EASY80920 (NOR SPL)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand
UBOOT_IMAGE:=u-boot.ltq.lzo.norspl
DEPENDS+=@BROKEN
endef
define U-Boot/easy80920_sfspl
NAME:=Lantiq EASY80920 (SPI SPL)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand
UBOOT_IMAGE:=u-boot.ltq.lzo.sfspl
DEPENDS+=@BROKEN
endef
define U-Boot/fb3370_eva
NAME:=AVM FRITZ3370 (EVA)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=avm_fritz3370
endef
define U-Boot/fb3370_ram
NAME:=AVM FRITZ3370 (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=avm_fritz3370
DDR_SETTINGS:=board/avm/fb3370/ddr_settings.h
endef
define U-Boot/fb3370_sfspl
NAME:=AVM FRITZ3370 (SPI SPL)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=avm_fritz3370
UBOOT_IMAGE:=u-boot.ltq.lzo.sfspl
DEPENDS+=@BROKEN
endef
define U-Boot/p2812hnufx_ram
NAME:=ZyXEL P-2812HNU-Fx (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=zyxel_p-2812hnu-f1
DDR_SETTINGS:=board/zyxel/p2812hnufx/ddr_settings.h
endef
define U-Boot/p2812hnufx_nandspl
NAME:=ZyXEL P-2812HNU-Fx (NAND SPL)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=zyxel_p-2812hnu-f1
UBOOT_IMAGE:=u-boot.ltq.lzo.nandspl
DEPENDS+=@BROKEN
endef
define U-Boot/vgv7510kw22_brn
NAME:=Arcadyan VGV7510KW22 (BRN)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7510kw22-nor
endef
define U-Boot/vgv7510kw22_nor
NAME:=Arcadyan VGV7510KW22 (NOR)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7510kw22-nor
endef
define U-Boot/vgv7510kw22_ram
NAME:=Arcadyan VGV7510KW22 (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7510kw22-nor
DDR_SETTINGS:=board/arcadyan/vgv7510kw22/ddr_settings.h
endef
define U-Boot/vgv7519_brn
NAME:=Arcadyan VGV7519 (BRN)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn
endef
define U-Boot/vgv7519_nor
NAME:=Arcadyan VGV7519 (NOR)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn
endef
define U-Boot/vgv7519_ram
NAME:=Arcadyan VGV7519 (RAM)
BUILD_SUBTARGET:=xrx200
BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn
DDR_SETTINGS:=board/arcadyan/vgv7519/ddr_settings.h
endef
UBOOT_TARGETS:= \
arv4519pw_ram arv4519pw_nor arv4519pw_brn \
arv7506pw11_ram arv7506pw11_nor arv7506pw11_brn \
arv7510pw_ram arv7510pw_nor arv7510pw_brn \
arv7510pw22_ram arv7510pw22_nor arv7510pw22_brn \
arv7518pw_ram arv7518pw_nor arv7518pw_brn \
arv752dpw_ram arv752dpw_nor arv752dpw_brn \
arv752dpw22_ram arv752dpw22_nor arv752dpw22_brn \
arv8539pw22_brn arv8539pw22_nor arv8539pw22_ram \
bthomehubv5a_ram \
gigasx76x_ram gigasx76x_nor \
acmp252_ram acmp252_nor \
easy50712_ram easy50712_nor easy50712_norspl \
easy80920_ram easy80920_nor easy80920_norspl easy80920_sfspl \
fb3370_eva fb3370_ram fb3370_sfspl \
p2812hnufx_ram p2812hnufx_nandspl \
vgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram \
vgv7519_brn vgv7519_nor vgv7519_ram
define CompressVR9Firmware
$(STAGING_DIR_HOST)/bin/lzma e \
$(FIRMWARE_LANTIQ_SOURCE)/xrx200_phy$(1)_a$(2)$(3).bin \
$(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/fw_phy$(1)_a$(2)x.blob
endef
define Build/Prepare
$(call Build/Prepare/Default)
mkdir -p $(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/
$(call CompressVR9Firmware,11g,1,4)
$(call CompressVR9Firmware,11g,2,2)
$(call CompressVR9Firmware,22f,1,4)
$(call CompressVR9Firmware,22f,2,2)
endef
UBOOT_MAKE_FLAGS :=
ifeq ($(SUBTARGET),xway)
SOC:=danube
else
SOC:=vr9
endif
define Package/u-boot/install/uart
awk -f $(PKG_BUILD_DIR)/tools/lantiq_ram_init_uart.awk \
-v soc=$(SOC) $(PKG_BUILD_DIR)/$(DDR_SETTINGS) \
> $(PKG_BUILD_DIR)/ddr_settings
perl $(PKG_BUILD_DIR)/tools/gct.pl \
$(PKG_BUILD_DIR)/ddr_settings $(PKG_BUILD_DIR)/u-boot.srec \
$(1)/u-boot.asc
endef
define Package/u-boot/install
$(Package/u-boot/install/$(if $(DDR_SETTINGS),uart,default))
endef
$(eval $(call BuildPackage/U-Boot))

6
package/boot/uboot-lantiq/README Normal file
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# How to refresh patches
$ git clone git@github.com:danielschwierzeck/u-boot-lantiq.git
$ mkdir -p $OPENWRT_ROOT/packages/boot/uboot-lantiq/patches
$ cd u-boot-lantiq.git
$ git format-patch -p -k --no-renames --no-binary -o $OPENWRT_ROOT/package/boot/uboot-lantiq/patches v2013.10..u-boot-lantiq-v2013.10-openwrtN

170
package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch Normal file
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From 909840ef844013379e5ec399c1e76c65d1a6eb1d Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sat, 12 Oct 2013 21:09:47 +0200
Subject: sf: fix out-of-order calls for spi_claim_bus and spi_release_bus
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -132,12 +132,6 @@ int spi_flash_write_common(struct spi_fl
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: unable to claim SPI bus\n");
- return ret;
- }
-
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
debug("SF: enabling write failed\n");
@@ -158,8 +152,6 @@ int spi_flash_write_common(struct spi_fl
return ret;
}
- spi_release_bus(spi);
-
return ret;
}
@@ -175,12 +167,18 @@ int spi_flash_cmd_erase_ops(struct spi_f
return -1;
}
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
cmd[0] = flash->erase_cmd;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, offset);
if (ret < 0)
- return ret;
+ goto done;
#endif
spi_flash_addr(offset, cmd);
@@ -190,13 +188,16 @@ int spi_flash_cmd_erase_ops(struct spi_f
ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
if (ret < 0) {
debug("SF: erase failed\n");
- break;
+ goto done;
}
offset += erase_size;
len -= erase_size;
}
+done:
+ spi_release_bus(flash->spi);
+
return ret;
}
@@ -208,6 +209,12 @@ int spi_flash_cmd_write_ops(struct spi_f
u8 cmd[4];
int ret = -1;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
page_size = flash->page_size;
cmd[0] = CMD_PAGE_PROGRAM;
@@ -215,7 +222,7 @@ int spi_flash_cmd_write_ops(struct spi_f
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, offset);
if (ret < 0)
- return ret;
+ goto done;
#endif
byte_addr = offset % page_size;
chunk_len = min(len - actual, page_size - byte_addr);
@@ -232,12 +239,15 @@ int spi_flash_cmd_write_ops(struct spi_f
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
- break;
+ goto done;
}
offset += chunk_len;
}
+done:
+ spi_release_bus(flash->spi);
+
return ret;
}
@@ -247,20 +257,12 @@ int spi_flash_read_common(struct spi_fla
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: unable to claim SPI bus\n");
- return ret;
- }
-
ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
if (ret < 0) {
debug("SF: read cmd failed\n");
return ret;
}
- spi_release_bus(spi);
-
return ret;
}
@@ -271,6 +273,12 @@ int spi_flash_cmd_read_ops(struct spi_fl
u32 remain_len, read_len;
int ret = -1;
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
/* Handle memory-mapped SPI */
if (flash->memory_map) {
spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
@@ -289,7 +297,7 @@ int spi_flash_cmd_read_ops(struct spi_fl
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
debug("SF: fail to set bank%d\n", bank_sel);
- return ret;
+ goto done;
}
#endif
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
@@ -304,7 +312,7 @@ int spi_flash_cmd_read_ops(struct spi_fl
data, read_len);
if (ret < 0) {
debug("SF: read failed\n");
- break;
+ goto done;
}
offset += read_len;
@@ -312,6 +320,9 @@ int spi_flash_cmd_read_ops(struct spi_fl
data += read_len;
}
+done:
+ spi_release_bus(flash->spi);
+
return ret;
}

49
package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch Normal file
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@@ -0,0 +1,49 @@
From bb7df8c6ff30be3786483767d3afb0e77a69a640 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sat, 12 Oct 2013 21:21:18 +0200
Subject: sf: consistently use debug() for warning/error messages
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -176,8 +176,8 @@ static struct spi_flash *spi_flash_valid
}
if (i == ARRAY_SIZE(spi_flash_params_table)) {
- printf("SF: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ debug("SF: Unsupported flash IDs: ");
+ debug("manuf %02x, jedec %04x, ext_jedec %04x\n",
idcode[0], jedec, ext_jedec);
return NULL;
}
@@ -296,7 +296,7 @@ struct spi_flash *spi_flash_probe(unsign
/* Setup spi_slave */
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
- printf("SF: Failed to set up slave\n");
+ debug("SF: Failed to set up slave\n");
return NULL;
}
@@ -310,7 +310,7 @@ struct spi_flash *spi_flash_probe(unsign
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
if (ret) {
- printf("SF: Failed to get idcodes\n");
+ debug("SF: Failed to get idcodes\n");
goto err_read_id;
}
@@ -341,8 +341,8 @@ struct spi_flash *spi_flash_probe(unsign
#endif
#ifndef CONFIG_SPI_FLASH_BAR
if (flash->size > SPI_FLASH_16MB_BOUN) {
- puts("SF: Warning - Only lower 16MiB accessible,");
- puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ debug("SF: Warning - Only lower 16MiB accessible,");
+ debug(" Full access #define CONFIG_SPI_FLASH_BAR\n");
}
#endif

110
package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch Normal file
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@@ -0,0 +1,110 @@
From 36b7400465fe2339f1c78274b3fd258ade3a4c00 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sat, 12 Oct 2013 21:30:07 +0200
Subject: sf: move malloc of spi_flash to spi_flash_probe()
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -153,11 +153,10 @@ static const struct spi_flash_params spi
*/
};
-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
+static int spi_flash_validate_params(struct spi_flash *flash,
u8 *idcode)
{
const struct spi_flash_params *params;
- struct spi_flash *flash;
int i;
u16 jedec = idcode[1] << 8 | idcode[2];
u16 ext_jedec = idcode[3] << 8 | idcode[4];
@@ -179,20 +178,12 @@ static struct spi_flash *spi_flash_valid
debug("SF: Unsupported flash IDs: ");
debug("manuf %02x, jedec %04x, ext_jedec %04x\n",
idcode[0], jedec, ext_jedec);
- return NULL;
- }
-
- flash = malloc(sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate spi_flash\n");
- return NULL;
+ return -1;
}
- memset(flash, '\0', sizeof(*flash));
/* Assign spi data */
- flash->spi = spi;
flash->name = params->name;
- flash->memory_map = spi->memory_map;
+ flash->memory_map = flash->spi->memory_map;
/* Assign spi_flash ops */
flash->write = spi_flash_cmd_write_ops;
@@ -239,7 +230,7 @@ static struct spi_flash *spi_flash_valid
if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
&curr_bank, 1)) {
debug("SF: fail to read bank addr register\n");
- return NULL;
+ return -1;
}
flash->bank_curr = curr_bank;
} else {
@@ -254,7 +245,7 @@ static struct spi_flash *spi_flash_valid
spi_flash_cmd_write_status(flash, 0);
#endif
- return flash;
+ return 0;
}
#ifdef CONFIG_OF_CONTROL
@@ -289,15 +280,22 @@ struct spi_flash *spi_flash_probe(unsign
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
- struct spi_flash *flash = NULL;
+ struct spi_flash *flash;
u8 idcode[5];
int ret;
+ flash = malloc(sizeof(*flash));
+ if (!flash) {
+ debug("SF: Failed to allocate spi_flash\n");
+ return NULL;
+ }
+ memset(flash, 0, sizeof(*flash));
+
/* Setup spi_slave */
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
debug("SF: Failed to set up slave\n");
- return NULL;
+ goto err_setup;
}
/* Claim spi bus */
@@ -320,8 +318,9 @@ struct spi_flash *spi_flash_probe(unsign
#endif
/* Validate params from spi_flash_params table */
- flash = spi_flash_validate_params(spi, idcode);
- if (!flash)
+ flash->spi = spi;
+ ret = spi_flash_validate_params(flash, idcode);
+ if (ret)
goto err_read_id;
#ifdef CONFIG_OF_CONTROL
@@ -355,6 +354,9 @@ err_read_id:
spi_release_bus(spi);
err_claim_bus:
spi_free_slave(spi);
+err_setup:
+ free(flash);
+
return NULL;
}

80
package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch Normal file
View File

@@ -0,0 +1,80 @@
From da11da943487e2f724f25d409bcaa1f099637c0b Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 13 Oct 2013 14:56:45 +0200
Subject: sf: add slim probe funtions for SPL
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -365,3 +365,58 @@ void spi_flash_free(struct spi_flash *fl
spi_free_slave(flash->spi);
free(flash);
}
+
+#ifdef CONFIG_SPI_SPL_SIMPLE
+int spl_spi_flash_probe(struct spi_flash *flash)
+{
+ struct spi_slave *spi;
+ u8 idcode[5];
+ int ret;
+
+ /* Setup spi_slave */
+ spi = spi_setup_slave(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
+ CONFIG_SPL_SPI_MAX_HZ, CONFIG_SPL_SPI_MODE);
+ if (!spi) {
+ debug("SF: Failed to set up slave\n");
+ return -1;
+ }
+
+ /* Claim spi bus */
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("SF: Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ /* Read the ID codes */
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ if (ret) {
+ debug("SF: Failed to get idcodes\n");
+ goto err_read_id;
+ }
+
+ /* Validate params from spi_flash_params table */
+ flash->spi = spi;
+ ret = spi_flash_validate_params(flash, idcode);
+ if (ret)
+ goto err_read_id;
+
+ /* Release spi bus */
+ spi_release_bus(spi);
+
+ return 0;
+
+err_read_id:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ flash->spi = NULL;
+
+ return ret;
+}
+
+void spl_spi_flash_free(struct spi_flash *flash)
+{
+ spi_free_slave(flash->spi);
+}
+#endif
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -69,6 +69,9 @@ struct spi_flash *spi_flash_probe(unsign
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);
+int spl_spi_flash_probe(struct spi_flash *flash);
+void spl_spi_flash_free(struct spi_flash *flash);
+
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{

134
package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch Normal file
View File

@@ -0,0 +1,134 @@
From 6fb5f86b094756d94de8abe7425e3d290ff22dd2 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 13 Oct 2013 15:09:28 +0200
Subject: sf: make calculatiom of address bytes completely configurable
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -15,12 +15,17 @@
#include "sf_internal.h"
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ cmd[1] = addr >> (flash->addr_width * 8 - 8);
+ cmd[2] = addr >> (flash->addr_width * 8 - 16);
+ cmd[3] = addr >> (flash->addr_width * 8 - 24);
+}
+
+static int spi_flash_cmdsz(const struct spi_flash *flash)
+{
+ return 1 + flash->addr_width;
}
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
@@ -158,7 +163,7 @@ int spi_flash_write_common(struct spi_fl
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[4], cmd_len;
int ret = -1;
erase_size = flash->erase_size;
@@ -180,12 +185,13 @@ int spi_flash_cmd_erase_ops(struct spi_f
if (ret < 0)
goto done;
#endif
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(flash, offset, cmd);
+ cmd_len = spi_flash_cmdsz(flash);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], offset);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);
if (ret < 0) {
debug("SF: erase failed\n");
goto done;
@@ -206,7 +212,7 @@ int spi_flash_cmd_write_ops(struct spi_f
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[4], cmd_len;
int ret = -1;
ret = spi_claim_bus(flash->spi);
@@ -230,12 +236,13 @@ int spi_flash_cmd_write_ops(struct spi_f
if (flash->spi->max_write_size)
chunk_len = min(chunk_len, flash->spi->max_write_size);
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(flash, offset, cmd);
+ cmd_len = spi_flash_cmdsz(flash);
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
+ ret = spi_flash_write_common(flash, cmd, cmd_len,
buf + actual, chunk_len);
if (ret < 0) {
debug("SF: write failed\n");
@@ -269,7 +276,7 @@ int spi_flash_read_common(struct spi_fla
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 cmd[5], cmd_len, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -288,7 +295,6 @@ int spi_flash_cmd_read_ops(struct spi_fl
}
cmd[0] = CMD_READ_ARRAY_FAST;
- cmd[4] = 0x00;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
@@ -306,9 +312,11 @@ int spi_flash_cmd_read_ops(struct spi_fl
else
read_len = remain_len;
- spi_flash_addr(offset, cmd);
+ spi_flash_addr(flash, offset, cmd);
+ cmd_len = spi_flash_cmdsz(flash);
+ cmd[cmd_len] = 0x00;
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+ ret = spi_flash_read_common(flash, cmd, cmd_len + 1,
data, read_len);
if (ret < 0) {
debug("SF: read failed\n");
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -218,6 +218,9 @@ static int spi_flash_validate_params(str
flash->poll_cmd = CMD_FLAG_STATUS;
#endif
+ /* Configure default 3-byte addressing */
+ flash->addr_width = 3;
+
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
u8 curr_bank = 0;
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -57,6 +57,7 @@ struct spi_flash {
#endif
u8 poll_cmd;
u8 erase_cmd;
+ u8 addr_width;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);

160
package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch Normal file
View File

@@ -0,0 +1,160 @@
From 3af3addee645bd81537be1ddee49969f8dfc64ee Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 13 Oct 2013 15:24:56 +0200
Subject: sf: add support for 4-byte addressing
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -38,12 +38,14 @@
#define CMD_READ_ID 0x9f
/* Bank addr access commands */
-#ifdef CONFIG_SPI_FLASH_BAR
-# define CMD_BANKADDR_BRWR 0x17
-# define CMD_BANKADDR_BRRD 0x16
-# define CMD_EXTNADDR_WREAR 0xC5
-# define CMD_EXTNADDR_RDEAR 0xC8
-#endif
+#define CMD_BANKADDR_BRWR 0x17
+#define CMD_BANKADDR_BRRD 0x16
+#define CMD_EXTNADDR_WREAR 0xC5
+#define CMD_EXTNADDR_RDEAR 0xC8
+
+/* Macronix style 4-byte addressing */
+#define CMD_EN4B 0xb7
+#define CMD_EX4B 0xe9
/* Common status */
#define STATUS_WIP 0x01
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -21,6 +21,7 @@ static void spi_flash_addr(const struct
cmd[1] = addr >> (flash->addr_width * 8 - 8);
cmd[2] = addr >> (flash->addr_width * 8 - 16);
cmd[3] = addr >> (flash->addr_width * 8 - 24);
+ cmd[4] = addr >> (flash->addr_width * 8 - 32);
}
static int spi_flash_cmdsz(const struct spi_flash *flash)
@@ -163,7 +164,7 @@ int spi_flash_write_common(struct spi_fl
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- u8 cmd[4], cmd_len;
+ u8 cmd[5], cmd_len;
int ret = -1;
erase_size = flash->erase_size;
@@ -188,8 +189,8 @@ int spi_flash_cmd_erase_ops(struct spi_f
spi_flash_addr(flash, offset, cmd);
cmd_len = spi_flash_cmdsz(flash);
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], offset);
+ debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
+ cmd[2], cmd[3], cmd[4], offset);
ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);
if (ret < 0) {
@@ -212,7 +213,7 @@ int spi_flash_cmd_write_ops(struct spi_f
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4], cmd_len;
+ u8 cmd[5], cmd_len;
int ret = -1;
ret = spi_claim_bus(flash->spi);
@@ -239,8 +240,8 @@ int spi_flash_cmd_write_ops(struct spi_f
spi_flash_addr(flash, offset, cmd);
cmd_len = spi_flash_cmdsz(flash);
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
ret = spi_flash_write_common(flash, cmd, cmd_len,
buf + actual, chunk_len);
@@ -276,9 +277,13 @@ int spi_flash_read_common(struct spi_fla
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], cmd_len, bank_sel = 0;
- u32 remain_len, read_len;
+ u8 cmd[6], cmd_len;
+ u32 read_len;
int ret = -1;
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel = 0;
+ u32 remain_len;
+#endif
ret = spi_claim_bus(flash->spi);
if (ret) {
@@ -305,12 +310,15 @@ int spi_flash_cmd_read_ops(struct spi_fl
debug("SF: fail to set bank%d\n", bank_sel);
goto done;
}
-#endif
+
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
if (len < remain_len)
read_len = len;
else
read_len = remain_len;
+#else
+ read_len = len;
+#endif
spi_flash_addr(flash, offset, cmd);
cmd_len = spi_flash_cmdsz(flash);
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -153,6 +153,25 @@ static const struct spi_flash_params spi
*/
};
+int spi_flash_4byte_set(struct spi_flash *flash, u8 idcode0, int enable)
+{
+ u8 cmd, bankaddr;
+
+ switch (idcode0) {
+ case 0xc2:
+ case 0xef:
+ case 0x1c:
+ /* Macronix style */
+ cmd = enable ? CMD_EN4B : CMD_EX4B;
+ return spi_flash_cmd(flash->spi, cmd, NULL, 0);
+ default:
+ /* Spansion style */
+ cmd = CMD_BANKADDR_BRWR;
+ bankaddr = enable << 7;
+ return spi_flash_cmd_write(flash->spi, &cmd, 1, &bankaddr, 1);
+ }
+}
+
static int spi_flash_validate_params(struct spi_flash *flash,
u8 *idcode)
{
@@ -218,8 +237,18 @@ static int spi_flash_validate_params(str
flash->poll_cmd = CMD_FLAG_STATUS;
#endif
+#ifndef CONFIG_SPI_FLASH_BAR
+ /* enable 4-byte addressing if the device exceeds 16MiB */
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ flash->addr_width = 4;
+ spi_flash_4byte_set(flash, idcode[0], 1);
+ } else {
+ flash->addr_width = 3;
+ }
+#else
/* Configure default 3-byte addressing */
flash->addr_width = 3;
+#endif
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR

17
package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch Normal file
View File

@@ -0,0 +1,17 @@
From d5aa0d4117a439803a3d074d2745372036d2a1eb Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 13 Oct 2013 15:35:34 +0200
Subject: sf: add support for EN25QH256
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -53,6 +53,7 @@ static const struct spi_flash_params spi
{"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
{"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
{"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0},
+ {"EN25QH256", 0x1c7019, 0x0, 64 * 1024, 512, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},

21
package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch Normal file
View File

@@ -0,0 +1,21 @@
From 5a6d8045190c887c7f65e65fb1bfc8854774c458 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 13 Oct 2013 15:40:07 +0200
Subject: sf: fix sector layout of S25FL256S_256K and S25FL512S_256K
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -80,9 +80,9 @@ static const struct spi_flash_params spi
{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0},
{"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0},
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0},
- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, 0},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0},
- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, 0},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */

244
package/boot/uboot-lantiq/patches/0009-net-switchlib-add-framework-for-ethernet-switch-driv.patch Normal file
View File

@@ -0,0 +1,244 @@
From 0dff8c753c8929a478357abb38db0d1c1a60ec94 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:15 +0200
Subject: net: switchlib: add framework for ethernet switch drivers
Add a generic framework similar to phylib for ethernet switch
drivers and devices. This is useful to share the init and
setup code for switch devices across different boards.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
--- a/Makefile
+++ b/Makefile
@@ -280,6 +280,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o
LIBS-y += drivers/mtd/spi/libspi_flash.o
LIBS-y += drivers/net/libnet.o
LIBS-y += drivers/net/phy/libphy.o
+LIBS-y += drivers/net/switch/libswitch.o
LIBS-y += drivers/pci/libpci.o
LIBS-y += drivers/pcmcia/libpcmcia.o
LIBS-y += drivers/power/libpower.o \
--- /dev/null
+++ b/drivers/net/switch/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libswitch.o
+
+COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/drivers/net/switch/switch.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <switch.h>
+
+static struct list_head switch_drivers;
+static struct list_head switch_devices;
+
+void switch_init(void)
+{
+ INIT_LIST_HEAD(&switch_drivers);
+ INIT_LIST_HEAD(&switch_devices);
+
+ board_switch_init();
+}
+
+void switch_driver_register(struct switch_driver *drv)
+{
+ INIT_LIST_HEAD(&drv->list);
+ list_add_tail(&drv->list, &switch_drivers);
+}
+
+int switch_device_register(struct switch_device *dev)
+{
+ struct switch_driver *drv;
+
+ /* Add switch device only, if an adequate driver is registered */
+ list_for_each_entry(drv, &switch_drivers, list) {
+ if (!strcmp(drv->name, dev->name)) {
+ dev->drv = drv;
+
+ INIT_LIST_HEAD(&dev->list);
+ list_add_tail(&dev->list, &switch_devices);
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+struct switch_device *switch_connect(struct mii_dev *bus)
+{
+ struct switch_device *sw;
+ int err;
+
+ list_for_each_entry(sw, &switch_devices, list) {
+ sw->bus = bus;
+
+ err = sw->drv->probe(sw);
+ if (!err)
+ return sw;
+ }
+
+ return NULL;
+}
--- /dev/null
+++ b/include/switch.h
@@ -0,0 +1,102 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ */
+
+#ifndef __SWITCH_H
+#define __SWITCH_H
+
+#include <linux/list.h>
+
+#define SWITCH_NAME_SIZE 32
+
+struct switch_device;
+struct mii_dev;
+
+struct switch_driver {
+ struct list_head list;
+
+ /* Switch device name */
+ const char name[SWITCH_NAME_SIZE];
+
+ /*
+ * Called to probe the switch chip. Must return 0 if the switch
+ * chip matches the given switch device/driver combination. Otherwise
+ * 1 must be returned.
+ */
+ int (*probe) (struct switch_device *dev);
+
+ /*
+ * Called to initialize the switch chip.
+ */
+ void (*setup) (struct switch_device *dev);
+};
+
+struct switch_device {
+ struct list_head list;
+ struct switch_driver *drv;
+
+ /* MII bus the switch chip is connected to */
+ struct mii_dev *bus;
+
+ /* Switch device name */
+ const char name[SWITCH_NAME_SIZE];
+
+ /* Bitmask for board specific setup of used switch ports */
+ u16 port_mask;
+
+ /* Number of switch port that is connected to host CPU */
+ u16 cpu_port;
+};
+
+/*
+ * Board specific switch initialization.
+ *
+ * Called from switch_init to register the board specific switch_device
+ * structure.
+ */
+extern int board_switch_init(void);
+
+/* Initialize switch subsystem */
+#ifdef CONFIG_SWITCH_MULTI
+extern void switch_init(void);
+#else
+static inline void switch_init(void)
+{
+}
+#endif
+
+/* Register a switch driver */
+extern void switch_driver_register(struct switch_driver *drv);
+
+/* Register a switch device */
+extern int switch_device_register(struct switch_device *dev);
+
+/*
+ * Probe the available switch chips and connect the found one
+ * with the given MII bus
+ */
+#ifdef CONFIG_SWITCH_MULTI
+extern struct switch_device *switch_connect(struct mii_dev *bus);
+#else
+static inline struct switch_device *switch_connect(struct mii_dev *bus)
+{
+ return NULL;
+}
+#endif
+
+/*
+ * Setup the given switch device
+ */
+static inline void switch_setup(struct switch_device *dev)
+{
+ if (dev->drv->setup)
+ dev->drv->setup(dev);
+}
+
+/* Init functions for supported Switch drivers */
+
+#endif /* __SWITCH_H */
+
--- a/net/eth.c
+++ b/net/eth.c
@@ -10,6 +10,7 @@
#include <net.h>
#include <miiphy.h>
#include <phy.h>
+#include <switch.h>
void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
{
@@ -287,6 +288,8 @@ int eth_initialize(bd_t *bis)
phy_init();
#endif
+ switch_init();
+
eth_env_init(bis);
/*

161
package/boot/uboot-lantiq/patches/0010-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch Normal file
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@@ -0,0 +1,161 @@
From e2c59cedebf72e4a002134a2932f722b508a5448 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:15 +0200
Subject: net: switchlib: add driver for Lantiq PSB697X switch family
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
+COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/psb697x.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <switch.h>
+#include <miiphy.h>
+
+#define PSB697X_CHIPID1 0x2599
+#define PSB697X_PORT_COUNT 7
+
+#define PSB697X_PORT_BASE(p) (p * 0x20)
+#define PSB697X_REG_PS(p) (PSB697X_PORT_BASE(p) + 0x00)
+#define PSB697X_REG_PBC(p) (PSB697X_PORT_BASE(p) + 0x01)
+#define PSB697X_REG_PEC(p) (PSB697X_PORT_BASE(p) + 0x02)
+
+#define PSB697X_REG_SGC1 0x0E0 /* Switch Global Control Register 1 */
+#define PSB697X_REG_SGC2 0x0E1 /* Switch Global Control Register 2 */
+#define PSB697X_REG_CMH 0x0E2 /* CPU Port & Mirror Control */
+#define PSB697X_REG_MIICR 0x0F5 /* MII Port Control */
+#define PSB697X_REG_CI0 0x100 /* Chip Identifier 0 */
+#define PSB697X_REG_CI1 0x101 /* Chip Identifier 1 */
+#define PSB697X_REG_MIIAC 0x120 /* MII Indirect Access Control */
+#define PSB697X_REG_MIIWD 0x121 /* MII Indirect Write Data */
+#define PSB697X_REG_MIIRD 0x122 /* MII Indirect Read Data */
+
+#define PSB697X_REG_PORT_FLP (1 << 2) /* Force link up */
+#define PSB697X_REG_PORT_FLD (1 << 1) /* Force link down */
+
+#define PSB697X_REG_SGC2_SE (1 << 15) /* Switch enable */
+
+#define PSB697X_REG_CMH_CPN_MASK 0x7
+#define PSB697X_REG_CMH_CPN_SHIFT 5
+
+
+static inline int psb697x_mii_read(struct mii_dev *bus, u16 reg)
+{
+ int ret;
+
+ ret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);
+
+ return ret;
+}
+
+static inline int psb697x_mii_write(struct mii_dev *bus, u16 reg, u16 val)
+{
+ int ret;
+
+ ret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,
+ reg & 0x1f, val);
+
+ return ret;
+}
+
+static int psb697x_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ int ci1;
+
+ ci1 = psb697x_mii_read(bus, PSB697X_REG_CI1);
+
+ if (ci1 == PSB697X_CHIPID1)
+ return 0;
+
+ return 1;
+}
+
+static void psb697x_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ int i, state;
+
+ /* Enable switch */
+ psb697x_mii_write(bus, PSB697X_REG_SGC2, PSB697X_REG_SGC2_SE);
+
+ /*
+ * Force 100 Mbps as default value for CPU ports 5 and 6 to get
+ * full speed.
+ */
+ psb697x_mii_write(bus, PSB697X_REG_MIICR, 0x0773);
+
+ for (i = 0; i < PSB697X_PORT_COUNT; i++) {
+ state = dev->port_mask & (1 << i);
+
+ /*
+ * Software workaround from Errata Sheet:
+ * Force link down and reset internal PHY, keep that state
+ * for all unconnected ports and disable force link down
+ * for all connected ports
+ */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i),
+ PSB697X_REG_PORT_FLD);
+
+ if (i == dev->cpu_port)
+ /* Force link up for CPU port */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i),
+ PSB697X_REG_PORT_FLP);
+ else if (state)
+ /* Disable force link down for active LAN ports */
+ psb697x_mii_write(bus, PSB697X_REG_PBC(i), 0);
+ }
+}
+
+static struct switch_driver psb697x_drv = {
+ .name = "psb697x",
+};
+
+void switch_psb697x_init(void)
+{
+ /* For archs with manual relocation */
+ psb697x_drv.probe = psb697x_probe;
+ psb697x_drv.setup = psb697x_setup;
+
+ switch_driver_register(&psb697x_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -17,6 +17,10 @@ void switch_init(void)
INIT_LIST_HEAD(&switch_drivers);
INIT_LIST_HEAD(&switch_devices);
+#if defined(CONFIG_SWITCH_PSB697X)
+ switch_psb697x_init();
+#endif
+
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -97,6 +97,7 @@ static inline void switch_setup(struct s
}
/* Init functions for supported Switch drivers */
+extern void switch_psb697x_init(void);
#endif /* __SWITCH_H */

157
package/boot/uboot-lantiq/patches/0011-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch Normal file
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@@ -0,0 +1,157 @@
From c291443dc97dadcf0c6afd04688a7d9f79a221b5 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 29 Aug 2012 22:08:16 +0200
Subject: net: switchlib: add driver for Lantiq ADM6996I switch family
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -11,6 +11,7 @@ LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
+COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/adm6996i.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <switch.h>
+#include <miiphy.h>
+
+#define ADM6996I_CHIPID0 0x1020
+#define ADM6996I_CHIPID1 0x0007
+#define ADM6996I_PORT_COUNT 6
+
+#define ADM6996I_REG_P0BC 0x001 /* P0 Basic Control */
+#define ADM6996I_REG_P1BC 0x003 /* P1 Basic Control */
+#define ADM6996I_REG_P2BC 0x005 /* P2 Basic Control */
+#define ADM6996I_REG_P3BC 0x007 /* P3 Basic Control */
+#define ADM6996I_REG_P4BC 0x008 /* P4 Basic Control */
+#define ADM6996I_REG_P5BC 0x009 /* P5 Basic Control */
+
+#define ADM6996I_REG_P0EC 0x002 /* P0 Extended Control */
+#define ADM6996I_REG_P1EC 0x002 /* P1 Extended Control */
+#define ADM6996I_REG_P2EC 0x004 /* P2 Extended Control */
+#define ADM6996I_REG_P3EC 0x004 /* P3 Extended Control */
+#define ADM6996I_REG_P4EC 0x006 /* P4 Extended Control */
+#define ADM6996I_REG_P5EC 0x006 /* P5 Extended Control */
+
+#define ADM6996I_REG_SC4 0x012 /* System Control 4 */
+
+#define ADM6996I_REG_CI0 0xA0 /* Chip Identifier 0 */
+#define ADM6996I_REG_CI1 0xA1 /* Chip Identifier 1 */
+
+#define ADM6996I_REG_PXBC_DEFAULT 0x040F
+#define ADM6996I_REG_PXBC_CROSS_EE (1 << 15)
+#define ADM6996I_REG_PXBC_PD (1 << 5)
+
+#define ADM6996I_REG_SC4_DEFAULT 0x3600
+#define ADM6996I_REG_SC4_LED_ENABLE (1 << 1)
+
+#define ADM6996I_REG_CI0_PC_MASK 0xFFF0
+#define ADM6996I_REG_CI0_VN_MASK 0xF
+#define ADM6996I_REG_CI1_PC_MASK 0xF
+
+
+static inline int adm6996i_mii_read(struct mii_dev *bus, u16 reg)
+{
+ int ret;
+
+ ret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);
+
+ return ret;
+}
+
+static inline int adm6996i_mii_write(struct mii_dev *bus, u16 reg, u16 val)
+{
+ int ret;
+
+ ret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,
+ reg & 0x1f, val);
+
+ return ret;
+}
+
+static int adm6996i_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u16 ci0, ci1;
+
+ ci0 = adm6996i_mii_read(bus, ADM6996I_REG_CI0);
+ ci1 = adm6996i_mii_read(bus, ADM6996I_REG_CI1);
+
+ ci0 &= ADM6996I_REG_CI0_PC_MASK;
+ ci1 &= ADM6996I_REG_CI1_PC_MASK;
+
+ if (ci0 == ADM6996I_CHIPID0 && ci1 == ADM6996I_CHIPID1)
+ return 0;
+
+ return 1;
+}
+
+static void adm6996i_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u16 val;
+
+ /*
+ * Write default values (Port enable, 100 Mbps, Full Duplex,
+ * Auto negotiation, Flow control) and enable crossover auto-detect
+ */
+ val = ADM6996I_REG_PXBC_DEFAULT | ADM6996I_REG_PXBC_CROSS_EE;
+ adm6996i_mii_write(bus, ADM6996I_REG_P0BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P1BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P2BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P3BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P4BC, val);
+ adm6996i_mii_write(bus, ADM6996I_REG_P5BC, val);
+
+ val = ADM6996I_REG_SC4_DEFAULT | ADM6996I_REG_SC4_LED_ENABLE;
+ adm6996i_mii_write(bus, ADM6996I_REG_SC4, val);
+}
+
+static struct switch_driver adm6996i_drv = {
+ .name = "adm6996i",
+};
+
+void switch_adm6996i_init(void)
+{
+ /* For archs with manual relocation */
+ adm6996i_drv.probe = adm6996i_probe;
+ adm6996i_drv.setup = adm6996i_setup;
+
+ switch_driver_register(&adm6996i_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -20,6 +20,9 @@ void switch_init(void)
#if defined(CONFIG_SWITCH_PSB697X)
switch_psb697x_init();
#endif
+#if defined(CONFIG_SWITCH_ADM6996I)
+ switch_adm6996i_init();
+#endif
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -98,6 +98,7 @@ static inline void switch_setup(struct s
/* Init functions for supported Switch drivers */
extern void switch_psb697x_init(void);
+extern void switch_adm6996i_init(void);
#endif /* __SWITCH_H */

157
package/boot/uboot-lantiq/patches/0012-net-switchlib-add-driver-for-Atheros-AR8216.patch Normal file
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@@ -0,0 +1,157 @@
From 1a1d61a2faf0390033a3766559ce0e758e15894e Mon Sep 17 00:00:00 2001
From: Luka Perkov <openwrt@lukaperkov.net>
Date: Wed, 29 Aug 2012 22:08:16 +0200
Subject: net: switchlib: add driver for Atheros AR8216
Signed-off-by: Luka Perkov <openwrt@lukaperkov.net>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -12,6 +12,7 @@ LIB := $(obj)libswitch.o
COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
+COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/ar8216.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <switch.h>
+#include <netdev.h>
+
+#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
+
+#define AR8216_REG_CTRL 0x0000
+#define AR8216_CTRL_REVISION BITS(0, 8)
+#define AR8216_CTRL_VERSION BITS(8, 8)
+
+#define AR8216_PROBE_RETRIES 10
+
+static void split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
+{
+ regaddr >>= 1;
+ *r1 = regaddr & 0x1e;
+
+ regaddr >>= 5;
+ *r2 = regaddr & 0x7;
+
+ regaddr >>= 3;
+ *page = regaddr & 0x1ff;
+}
+
+static int ar8216_mii_read(struct mii_dev *bus, u32 reg)
+{
+ u16 r1, r2, page;
+ u16 lo, hi;
+
+ split_addr(reg, &r1, &r2, &page);
+
+ bus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, page);
+ __udelay(1000);
+
+ lo = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1);
+ hi = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1);
+
+ return (hi << 16) | lo;
+}
+
+static void ar8216_mii_write(struct mii_dev *bus, u16 reg, u32 val)
+{
+ u16 r1, r2, r3;
+ u16 lo, hi;
+
+ split_addr((u32) reg, &r1, &r2, &r3);
+
+ bus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, r3);
+ __udelay(1000);
+
+ lo = val & 0xffff;
+ hi = (u16) (val >> 16);
+ bus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1, hi);
+ bus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1, lo);
+}
+
+static int ar8216_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ u32 val;
+ u16 id;
+
+ val = ar8216_mii_read(bus, AR8216_REG_CTRL);
+ if (val == ~0)
+ return 1;
+
+ id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
+
+ switch (id) {
+ case 0x0101:
+ return 0;
+ default:
+ return 1;
+ }
+}
+
+static void ar8216_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+
+ ar8216_mii_write(bus, 0x200, 0x200);
+ ar8216_mii_write(bus, 0x300, 0x200);
+ ar8216_mii_write(bus, 0x400, 0x200);
+ ar8216_mii_write(bus, 0x500, 0x200);
+ ar8216_mii_write(bus, 0x600, 0x7d);
+ ar8216_mii_write(bus, 0x38, 0xc000050e);
+ ar8216_mii_write(bus, 0x104, 0x4004);
+ ar8216_mii_write(bus, 0x60, 0xffffffff);
+ ar8216_mii_write(bus, 0x64, 0xaaaaaaaa);
+ ar8216_mii_write(bus, 0x68, 0x55555555);
+ ar8216_mii_write(bus, 0x6c, 0x0);
+ ar8216_mii_write(bus, 0x70, 0x41af);
+}
+
+static struct switch_driver ar8216_drv = {
+ .name = "ar8216",
+};
+
+void switch_ar8216_init(void)
+{
+ /* for archs with manual relocation */
+ ar8216_drv.probe = ar8216_probe;
+ ar8216_drv.setup = ar8216_setup;
+
+ switch_driver_register(&ar8216_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -23,6 +23,9 @@ void switch_init(void)
#if defined(CONFIG_SWITCH_ADM6996I)
switch_adm6996i_init();
#endif
+#if defined(CONFIG_SWITCH_AR8216)
+ switch_ar8216_init();
+#endif
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -99,6 +99,7 @@ static inline void switch_setup(struct s
/* Init functions for supported Switch drivers */
extern void switch_psb697x_init(void);
extern void switch_adm6996i_init(void);
+extern void switch_ar8216_init(void);
#endif /* __SWITCH_H */

375
package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch Normal file
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@@ -0,0 +1,375 @@
From 42cb399df978a33539b95d668b3f973d927cb902 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 17 Dec 2012 23:37:57 +0100
Subject: net: switchlib: add driver for REALTEK RTL8306
Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/drivers/net/switch/Makefile
+++ b/drivers/net/switch/Makefile
@@ -13,6 +13,7 @@ COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o
+COBJS-$(CONFIG_SWITCH_RTL8306) += rtl8306.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+++ b/drivers/net/switch/rtl8306.c
@@ -0,0 +1,332 @@
+/*
+ * Based on OpenWrt linux driver
+ *
+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#define DEBUG
+#include <common.h>
+#include <malloc.h>
+#include <switch.h>
+#include <miiphy.h>
+
+#define RTL8306_REG_PAGE 16
+#define RTL8306_REG_PAGE_LO (1 << 15)
+#define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
+#define RTL8306_CHIPID 0x5988
+
+#define RTL8306_NUM_VLANS 16
+#define RTL8306_NUM_PORTS 6
+#define RTL8306_PORT_CPU 5
+#define RTL8306_NUM_PAGES 4
+#define RTL8306_NUM_REGS 32
+
+enum {
+ RTL_TYPE_S,
+ RTL_TYPE_SD,
+ RTL_TYPE_SDM,
+};
+
+struct rtl_reg {
+ int page;
+ int phy;
+ int reg;
+ int bits;
+ int shift;
+ int inverted;
+};
+
+enum rtl_regidx {
+ RTL_REG_CHIPID,
+ RTL_REG_CHIPVER,
+ RTL_REG_CHIPTYPE,
+ RTL_REG_CPUPORT,
+
+ RTL_REG_EN_CPUPORT,
+ RTL_REG_EN_TAG_OUT,
+ RTL_REG_EN_TAG_CLR,
+ RTL_REG_EN_TAG_IN,
+ RTL_REG_TRAP_CPU,
+ RTL_REG_TRUNK_PORTSEL,
+ RTL_REG_EN_TRUNK,
+ RTL_REG_RESET,
+ RTL_REG_PHY_RESET,
+ RTL_REG_CPU_LINKUP,
+
+ RTL_REG_VLAN_ENABLE,
+ RTL_REG_VLAN_FILTER,
+ RTL_REG_VLAN_TAG_ONLY,
+ RTL_REG_VLAN_TAG_AWARE,
+#define RTL_VLAN_ENUM(id) \
+ RTL_REG_VLAN##id##_VID, \
+ RTL_REG_VLAN##id##_PORTMASK
+ RTL_VLAN_ENUM(0),
+ RTL_VLAN_ENUM(1),
+ RTL_VLAN_ENUM(2),
+ RTL_VLAN_ENUM(3),
+ RTL_VLAN_ENUM(4),
+ RTL_VLAN_ENUM(5),
+ RTL_VLAN_ENUM(6),
+ RTL_VLAN_ENUM(7),
+ RTL_VLAN_ENUM(8),
+ RTL_VLAN_ENUM(9),
+ RTL_VLAN_ENUM(10),
+ RTL_VLAN_ENUM(11),
+ RTL_VLAN_ENUM(12),
+ RTL_VLAN_ENUM(13),
+ RTL_VLAN_ENUM(14),
+ RTL_VLAN_ENUM(15),
+#define RTL_PORT_ENUM(id) \
+ RTL_REG_PORT##id##_PVID, \
+ RTL_REG_PORT##id##_NULL_VID_REPLACE, \
+ RTL_REG_PORT##id##_NON_PVID_DISCARD, \
+ RTL_REG_PORT##id##_VID_INSERT, \
+ RTL_REG_PORT##id##_TAG_INSERT, \
+ RTL_REG_PORT##id##_LINK, \
+ RTL_REG_PORT##id##_SPEED, \
+ RTL_REG_PORT##id##_NWAY, \
+ RTL_REG_PORT##id##_NRESTART, \
+ RTL_REG_PORT##id##_DUPLEX, \
+ RTL_REG_PORT##id##_RXEN, \
+ RTL_REG_PORT##id##_TXEN, \
+ RTL_REG_PORT##id##_LRNEN
+ RTL_PORT_ENUM(0),
+ RTL_PORT_ENUM(1),
+ RTL_PORT_ENUM(2),
+ RTL_PORT_ENUM(3),
+ RTL_PORT_ENUM(4),
+ RTL_PORT_ENUM(5),
+};
+
+static const struct rtl_reg rtl_regs[] = {
+ [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
+ [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
+ [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
+
+ /* CPU port number */
+ [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
+ /* Enable CPU port function */
+ [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
+ /* Enable CPU port tag insertion */
+ [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
+ /* Enable CPU port tag removal */
+ [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
+ /* Enable CPU port tag checking */
+ [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
+ [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
+ [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
+ [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
+ [RTL_REG_PHY_RESET] = { 0, 0, 0, 1, 15, 0 },
+ [RTL_REG_CPU_LINKUP] = { 0, 6, 22, 1, 15, 0 },
+ [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
+
+ [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
+ [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
+ [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
+ [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
+
+#define RTL_VLAN_REGS(id, phy, page, regofs) \
+ [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
+ [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
+ RTL_VLAN_REGS( 0, 0, 0, 0),
+ RTL_VLAN_REGS( 1, 1, 0, 0),
+ RTL_VLAN_REGS( 2, 2, 0, 0),
+ RTL_VLAN_REGS( 3, 3, 0, 0),
+ RTL_VLAN_REGS( 4, 4, 0, 0),
+ RTL_VLAN_REGS( 5, 0, 1, 2),
+ RTL_VLAN_REGS( 6, 1, 1, 2),
+ RTL_VLAN_REGS( 7, 2, 1, 2),
+ RTL_VLAN_REGS( 8, 3, 1, 2),
+ RTL_VLAN_REGS( 9, 4, 1, 2),
+ RTL_VLAN_REGS(10, 0, 1, 4),
+ RTL_VLAN_REGS(11, 1, 1, 4),
+ RTL_VLAN_REGS(12, 2, 1, 4),
+ RTL_VLAN_REGS(13, 3, 1, 4),
+ RTL_VLAN_REGS(14, 4, 1, 4),
+ RTL_VLAN_REGS(15, 0, 1, 6),
+
+#define REG_PORT_SETTING(port, phy) \
+ [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
+ [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
+ [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
+ [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
+ [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
+ [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
+ [RTL_REG_PORT##port##_LRNEN] = { 0, phy, 24, 1, 9, 0 }, \
+ [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
+ [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
+ [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
+ [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
+ [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
+
+ REG_PORT_SETTING(0, 0),
+ REG_PORT_SETTING(1, 1),
+ REG_PORT_SETTING(2, 2),
+ REG_PORT_SETTING(3, 3),
+ REG_PORT_SETTING(4, 4),
+ REG_PORT_SETTING(5, 6),
+
+#define REG_PORT_PVID(phy, page, regofs) \
+ { page, phy, 24 + regofs, 4, 12, 0 }
+ [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
+ [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
+ [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
+ [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
+ [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
+ [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
+};
+
+static void rtl_set_page(struct mii_dev *bus, unsigned int page)
+{
+ u16 pgsel;
+
+ BUG_ON(page > RTL8306_NUM_PAGES);
+
+ pgsel = bus->read(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE);
+ pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
+
+ if (page & (1 << 0))
+ pgsel |= RTL8306_REG_PAGE_LO;
+
+ if (!(page & (1 << 1))) /* bit is inverted */
+ pgsel |= RTL8306_REG_PAGE_HI;
+
+ bus->write(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE, pgsel);
+
+}
+
+static __maybe_unused int rtl_w16(struct mii_dev *bus, unsigned int page, unsigned int phy,
+ unsigned int reg, u16 val)
+{
+ rtl_set_page(bus, page);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, reg, val);
+ bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
+
+ return 0;
+}
+
+static int rtl_r16(struct mii_dev *bus, unsigned int page, unsigned int phy,
+ unsigned int reg)
+{
+ rtl_set_page(bus, page);
+
+ return bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
+}
+
+static u16 rtl_rmw(struct mii_dev *bus, unsigned int page, unsigned int phy,
+ unsigned int reg, u16 mask, u16 val)
+{
+ u16 r;
+
+ rtl_set_page(bus, page);
+
+ r = bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
+ r &= ~mask;
+ r |= val;
+ bus->write(bus, phy, MDIO_DEVAD_NONE, reg, r);
+
+ return bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
+}
+
+static int rtl_get(struct mii_dev *bus, enum rtl_regidx s)
+{
+ const struct rtl_reg *r = &rtl_regs[s];
+ u16 val;
+
+ BUG_ON(s >= ARRAY_SIZE(rtl_regs));
+
+ if (r->bits == 0) /* unimplemented */
+ return 0;
+
+ val = rtl_r16(bus, r->page, r->phy, r->reg);
+
+ if (r->shift > 0)
+ val >>= r->shift;
+
+ if (r->inverted)
+ val = ~val;
+
+ val &= (1 << r->bits) - 1;
+
+ return val;
+}
+
+static __maybe_unused int rtl_set(struct mii_dev *bus, enum rtl_regidx s, unsigned int val)
+{
+ const struct rtl_reg *r = &rtl_regs[s];
+ u16 mask = 0xffff;
+
+ BUG_ON(s >= ARRAY_SIZE(rtl_regs));
+
+ if (r->bits == 0) /* unimplemented */
+ return 0;
+
+ if (r->shift > 0)
+ val <<= r->shift;
+
+ if (r->inverted)
+ val = ~val;
+
+ if (r->bits != 16) {
+ mask = (1 << r->bits) - 1;
+ mask <<= r->shift;
+ }
+
+ val &= mask;
+
+ return rtl_rmw(bus, r->page, r->phy, r->reg, mask, val);
+}
+
+static int rtl8306_probe(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+ unsigned int chipid, chipver, chiptype;
+
+ chipid = rtl_get(bus, RTL_REG_CHIPID);
+ chipver = rtl_get(bus, RTL_REG_CHIPVER);
+ chiptype = rtl_get(bus, RTL_REG_CHIPTYPE);
+
+ debug("%s: chipid %x, chipver %x, chiptype %x\n",
+ __func__, chipid, chipver, chiptype);
+
+ if (chipid == RTL8306_CHIPID)
+ return 0;
+
+ return 1;
+}
+
+static void rtl8306_setup(struct switch_device *dev)
+{
+ struct mii_dev *bus = dev->bus;
+
+ /* initialize cpu port settings */
+ rtl_set(bus, RTL_REG_CPUPORT, dev->cpu_port);
+ rtl_set(bus, RTL_REG_EN_CPUPORT, 1);
+
+ /* enable phy 5 link status */
+ rtl_set(bus, RTL_REG_CPU_LINKUP, 1);
+// rtl_set(bus, RTL_REG_PORT5_TXEN, 1);
+// rtl_set(bus, RTL_REG_PORT5_RXEN, 1);
+// rtl_set(bus, RTL_REG_PORT5_LRNEN, 1);
+#ifdef DEBUG
+ debug("%s: CPU link up: %i\n",
+ __func__, rtl_get(bus, RTL_REG_PORT5_LINK));
+#endif
+
+}
+
+static struct switch_driver rtl8306_drv = {
+ .name = "rtl8306",
+};
+
+void switch_rtl8306_init(void)
+{
+ /* For archs with manual relocation */
+ rtl8306_drv.probe = rtl8306_probe;
+ rtl8306_drv.setup = rtl8306_setup;
+
+ switch_driver_register(&rtl8306_drv);
+}
--- a/drivers/net/switch/switch.c
+++ b/drivers/net/switch/switch.c
@@ -26,6 +26,9 @@ void switch_init(void)
#if defined(CONFIG_SWITCH_AR8216)
switch_ar8216_init();
#endif
+#if defined(CONFIG_SWITCH_RTL8306)
+ switch_rtl8306_init();
+#endif
board_switch_init();
}
--- a/include/switch.h
+++ b/include/switch.h
@@ -100,6 +100,7 @@ static inline void switch_setup(struct s
extern void switch_psb697x_init(void);
extern void switch_adm6996i_init(void);
extern void switch_ar8216_init(void);
+extern void switch_rtl8306_init(void);
#endif /* __SWITCH_H */

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package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch Normal file
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package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch Normal file
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546
package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch Normal file
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@@ -0,0 +1,546 @@
From 7288414298b34dcda1216fee1fe38d05ea0027a2 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 17 Dec 2012 23:32:39 +0100
Subject: net: add driver for Lantiq XWAY ARX100 switch
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/arch/mips/include/asm/arch-arx100/config.h
+++ b/arch/mips/include/asm/arch-arx100/config.h
@@ -10,17 +10,21 @@
* and drivers for this SoC:
*
* CONFIG_LTQ_SUPPORT_UART
- * - support the Danube ASC/UART interface and console
+ * - support the ARX100 ASC/UART interface and console
*
* CONFIG_LTQ_SUPPORT_NOR_FLASH
* - support a parallel NOR flash via the CFI interface in flash bank 0
*
* CONFIG_LTQ_SUPPORT_ETHERNET
- * - support the Danube ETOP and MAC interface
+ * - support the ARX100 ETOP and MAC interface
*
* CONFIG_LTQ_SUPPORT_SPI_FLASH
- * - support the Danube SPI interface and serial flash drivers
+ * - support the ARX100 SPI interface and serial flash drivers
* - specific SPI flash drivers must be configured separately
+ *
+ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH
+ * - build a preloader that runs in the internal SRAM and loads
+ * the U-Boot from SPI flash into RAM
*/
#ifndef __ARX100_CONFIG_H__
--- /dev/null
+++ b/arch/mips/include/asm/arch-arx100/switch.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARX100_SWITCH_H__
+#define __ARX100_SWITCH_H__
+
+struct ar9_switch_regs {
+ __be32 ps; /* Port status*/
+ __be32 p0_ctl; /* Port 0 control */
+ __be32 p1_ctl; /* Port 1 control */
+ __be32 p2_ctl; /* Port 2 control */
+ __be32 p0_vlan; /* Port 0 VLAN control */
+ __be32 p1_vlan; /* Port 1 VLAN control */
+ __be32 p2_vlan; /* Port 2 VLAN control */
+ __be32 p0_inctl; /* Port 0 ingress control */
+ __be32 p1_inctl; /* Port 1 ingress control */
+ __be32 p2_inctl; /* Port 2 ingress control */
+ u32 rsvd0[16];
+ __be32 sw_gctl0; /* Switch global control 0 */
+ __be32 sw_gctl1; /* Switch global control 1 */
+ __be32 arp; /* ARP/RARP */
+ __be32 strm_ctl; /* Storm control */
+ __be32 rgmii_ctl; /* RGMII/GMII port control */
+ u32 rsvd1[4];
+ __be32 pmac_hd_ctl; /* PMAC header control */
+ u32 rsvd2[15];
+ __be32 mdio_ctrl; /* MDIO indirect access control */
+ __be32 mdio_data; /* MDIO indirect read data */
+};
+
+#define BUILD_CHECK_AR9_REG(name, offset) \
+ BUILD_BUG_ON(offsetof(struct ar9_switch_regs, name) != (offset))
+
+static inline void build_check_ar9_registers(void)
+{
+ BUILD_CHECK_AR9_REG(sw_gctl0, 0x68);
+ BUILD_CHECK_AR9_REG(rgmii_ctl, 0x78);
+ BUILD_CHECK_AR9_REG(pmac_hd_ctl, 0x8c);
+ BUILD_CHECK_AR9_REG(mdio_ctrl, 0xcc);
+ BUILD_CHECK_AR9_REG(mdio_data, 0xd0);
+}
+
+#define P0_CTL_FLP (1 << 18)
+#define P0_CTL_FLD (1 << 17)
+
+#define SW_GCTL0_SE (1 << 31)
+
+#define RGMII_CTL_P1_SHIFT 10
+#define RGMII_CTL_P1_MASK (0x3FF << RGMII_CTL_P1_SHIFT)
+#define RGMII_CTL_P0_MASK 0x3FF
+#define RGMII_CTL_P0IS_SHIFT 8
+#define RGMII_CTL_P0IS_RGMII (0x0 << RGMII_CTL_P0IS_SHIFT)
+#define RGMII_CTL_P0IS_MII (0x1 << RGMII_CTL_P0IS_SHIFT)
+#define RGMII_CTL_P0IS_REVMII (0x2 << RGMII_CTL_P0IS_SHIFT)
+#define RGMII_CTL_P0IS_RMII (0x3 << RGMII_CTL_P0IS_SHIFT)
+#define RGMII_CTL_P0RDLY_SHIFT 6
+#define RGMII_CTL_P0RDLY_0_0 (0x0 << RGMII_CTL_P0RDLY_SHIFT)
+#define RGMII_CTL_P0RDLY_1_5 (0x1 << RGMII_CTL_P0RDLY_SHIFT)
+#define RGMII_CTL_P0RDLY_1_75 (0x2 << RGMII_CTL_P0RDLY_SHIFT)
+#define RGMII_CTL_P0RDLY_2_0 (0x3 << RGMII_CTL_P0RDLY_SHIFT)
+#define RGMII_CTL_P0TDLY_SHIFT 4
+#define RGMII_CTL_P0TDLY_0_0 (0x0 << RGMII_CTL_P0TDLY_SHIFT)
+#define RGMII_CTL_P0TDLY_1_5 (0x1 << RGMII_CTL_P0TDLY_SHIFT)
+#define RGMII_CTL_P0TDLY_1_75 (0x2 << RGMII_CTL_P0TDLY_SHIFT)
+#define RGMII_CTL_P0TDLY_2_0 (0x3 << RGMII_CTL_P0TDLY_SHIFT)
+#define RGMII_CTL_P0SPD_SHIFT 2
+#define RGMII_CTL_P0SPD_10 (0x0 << RGMII_CTL_P0SPD_SHIFT)
+#define RGMII_CTL_P0SPD_100 (0x1 << RGMII_CTL_P0SPD_SHIFT)
+#define RGMII_CTL_P0SPD_1000 (0x2 << RGMII_CTL_P0SPD_SHIFT)
+#define RGMII_CTL_P0DUP_FULL (1 << 1)
+#define RGMII_CTL_P0FCE_EN (1 << 0)
+
+#define PMAC_HD_CTL_AC (1 << 18)
+
+#define MDIO_CTRL_WD_SHIFT 16
+#define MDIO_CTRL_MBUSY (1 << 15)
+#define MDIO_CTRL_OP_READ (1 << 11)
+#define MDIO_CTRL_OP_WRITE (1 << 10)
+#define MDIO_CTRL_PHYAD_SHIFT 5
+#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT)
+#define MDIO_CTRL_REGAD_MASK 0x1f
+
+#endif /* __ARX100_SWITCH_H__ */
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks86
COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o
+COBJS-$(CONFIG_LANTIQ_ARX100_SWITCH) += lantiq_arx100_switch.o
COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
--- /dev/null
+++ b/drivers/net/lantiq_arx100_switch.c
@@ -0,0 +1,410 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#define DEBUG
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <switch.h>
+#include <linux/compiler.h>
+#include <asm/gpio.h>
+#include <asm/processor.h>
+#include <asm/lantiq/io.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/pm.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/dma.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/switch.h>
+
+#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
+#define LTQ_ETH_TX_BUFFER_CNT 8
+#define LTQ_ETH_RX_DATA_SIZE PKTSIZE_ALIGN
+#define LTQ_ETH_IP_ALIGN 2
+
+#define LTQ_MDIO_DRV_NAME "ltq-mdio"
+#define LTQ_ETH_DRV_NAME "ltq-eth"
+
+#define LTQ_ETHSW_MAX_GMAC 2
+#define LTQ_ETHSW_PMAC 2
+
+struct ltq_eth_priv {
+ struct ltq_dma_device dma_dev;
+ struct mii_dev *bus;
+ struct eth_device *dev;
+ struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
+ int rx_num;
+ int tx_num;
+};
+
+static struct ar9_switch_regs *switch_regs =
+ (struct ar9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);
+
+static int ltq_mdio_is_busy(void)
+{
+ u32 mdio_ctrl = ltq_readl(&switch_regs->mdio_ctrl);
+
+ return mdio_ctrl & MDIO_CTRL_MBUSY;
+}
+
+static void ltq_mdio_poll(void)
+{
+ while (ltq_mdio_is_busy())
+ cpu_relax();
+
+ __udelay(1000);
+}
+
+static int ltq_mdio_read(struct mii_dev *bus, int phyad, int devad,
+ int regad)
+{
+ u32 mdio_ctrl;
+ int retval;
+
+ mdio_ctrl = MDIO_CTRL_MBUSY | MDIO_CTRL_OP_READ |
+ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
+ (regad & MDIO_CTRL_REGAD_MASK);
+
+ ltq_mdio_poll();
+ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
+ ltq_mdio_poll();
+ retval = ltq_readl(&switch_regs->mdio_data);
+ ltq_writel(&switch_regs->mdio_data, 0xFFFF);
+
+ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, retval);
+
+ return retval;
+}
+
+static int ltq_mdio_write(struct mii_dev *bus, int phyad, int devad,
+ int regad, u16 val)
+{
+ u32 mdio_ctrl;
+
+ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, val);
+
+ mdio_ctrl = (val << MDIO_CTRL_WD_SHIFT) | MDIO_CTRL_MBUSY |
+ MDIO_CTRL_OP_WRITE |
+ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
+ (regad & MDIO_CTRL_REGAD_MASK);
+
+ ltq_mdio_poll();
+ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);
+
+ return 0;
+}
+
+static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
+{
+}
+
+static inline u8 *ltq_eth_rx_packet_align(int rx_num)
+{
+ u8 *packet = (u8 *) NetRxPackets[rx_num];
+
+ /*
+ * IP header needs
+ */
+ return packet + LTQ_ETH_IP_ALIGN;
+}
+
+static int ltq_eth_init(struct eth_device *dev, bd_t *bis)
+{
+ struct ltq_eth_priv *priv = dev->priv;
+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
+ struct phy_device *phydev;
+ int i;
+
+ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
+ phydev = priv->phymap[i];
+ if (!phydev)
+ continue;
+
+ phy_startup(phydev);
+ ltq_eth_gmac_update(phydev, i);
+ }
+
+ for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)
+ ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),
+ LTQ_ETH_RX_DATA_SIZE);
+
+ ltq_dma_enable(dma_dev);
+
+ priv->rx_num = 0;
+ priv->tx_num = 0;
+
+ return 0;
+}
+
+static void ltq_eth_halt(struct eth_device *dev)
+{
+ struct ltq_eth_priv *priv = dev->priv;
+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
+ struct phy_device *phydev;
+ int i;
+
+ ltq_dma_reset(dma_dev);
+
+ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
+ phydev = priv->phymap[i];
+ if (!phydev)
+ continue;
+
+ phy_shutdown(phydev);
+ phydev->link = 0;
+ ltq_eth_gmac_update(phydev, i);
+ }
+}
+
+static int ltq_eth_send(struct eth_device *dev, void *packet, int length)
+{
+ struct ltq_eth_priv *priv = dev->priv;
+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
+ int err;
+
+ err = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);
+ if (err) {
+ puts("NET: timeout on waiting for TX descriptor\n");
+ return -1;
+ }
+
+ priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;
+
+ return err;
+}
+
+static int ltq_eth_recv(struct eth_device *dev)
+{
+ struct ltq_eth_priv *priv = dev->priv;
+ struct ltq_dma_device *dma_dev = &priv->dma_dev;
+ u8 *packet;
+ int len;
+
+ if (!ltq_dma_rx_poll(dma_dev, priv->rx_num))
+ return 0;
+
+#if 0
+ printf("%s: rx_num %d\n", __func__, priv->rx_num);
+#endif
+
+ len = ltq_dma_rx_length(dma_dev, priv->rx_num);
+ packet = ltq_eth_rx_packet_align(priv->rx_num);
+
+#if 0
+ printf("%s: received: packet %p, len %u, rx_num %d\n",
+ __func__, packet, len, priv->rx_num);
+#endif
+
+ if (len)
+ NetReceive(packet, len);
+
+ ltq_dma_rx_map(dma_dev, priv->rx_num, packet,
+ LTQ_ETH_RX_DATA_SIZE);
+
+ priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;
+
+ return 0;
+}
+
+static void ltq_eth_pmac_init(void)
+{
+ /* Add CRC to packets from DMA to PMAC */
+ ltq_setbits(&switch_regs->pmac_hd_ctl, PMAC_HD_CTL_AC);
+
+ /* Force link up */
+ ltq_setbits(&switch_regs->p2_ctl, P0_CTL_FLP);
+}
+
+static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)
+{
+ /* Power up ethernet subsystems */
+ ltq_pm_enable(LTQ_PM_ETH);
+
+ /* Enable switch core */
+ ltq_setbits(&switch_regs->sw_gctl0, SW_GCTL0_SE);
+
+ /* MII/MDIO */
+ gpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* MII/MDC */
+ gpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+
+ ltq_eth_pmac_init();
+}
+
+static void ltq_eth_port_config(struct ltq_eth_priv *priv,
+ const struct ltq_eth_port_config *port)
+{
+ struct phy_device *phydev;
+ struct switch_device *sw;
+ u32 rgmii_ctl;
+ unsigned int port_ctl, port_xmii = 0;
+
+ if (port->num > 1)
+ return;
+
+ rgmii_ctl = ltq_readl(&switch_regs->rgmii_ctl);
+
+ if (port->num == 1)
+ port_ctl = ltq_readl(&switch_regs->p1_ctl);
+ else
+ port_ctl = ltq_readl(&switch_regs->p0_ctl);
+
+ switch (port->phy_if) {
+ case PHY_INTERFACE_MODE_RGMII:
+ port_xmii = RGMII_CTL_P0IS_RGMII;
+
+ switch (port->rgmii_tx_delay) {
+ case 1:
+ port_xmii |= RGMII_CTL_P0TDLY_1_5;
+ break;
+ case 2:
+ port_xmii |= RGMII_CTL_P0TDLY_1_75;
+ break;
+ case 3:
+ port_xmii |= RGMII_CTL_P0TDLY_2_0;
+ break;
+ default:
+ break;
+ }
+
+ switch (port->rgmii_rx_delay) {
+ case 1:
+ port_xmii |= RGMII_CTL_P0RDLY_1_5;
+ break;
+ case 2:
+ port_xmii |= RGMII_CTL_P0RDLY_1_75;
+ break;
+ case 3:
+ port_xmii |= RGMII_CTL_P0RDLY_2_0;
+ break;
+ default:
+ break;
+ }
+
+ if (!(port->flags & LTQ_ETH_PORT_PHY)) {
+ port_xmii |= (RGMII_CTL_P0SPD_1000 |
+ RGMII_CTL_P0DUP_FULL);
+ port_ctl |= P0_CTL_FLP;
+ }
+
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ port_xmii = RGMII_CTL_P0IS_MII;
+
+ if (!(port->flags & LTQ_ETH_PORT_PHY)) {
+ port_xmii |= (RGMII_CTL_P0SPD_100 |
+ RGMII_CTL_P0DUP_FULL);
+ port_ctl |= P0_CTL_FLP;
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if (port->num == 1) {
+ ltq_writel(&switch_regs->p1_ctl, port_ctl);
+
+ rgmii_ctl &= ~RGMII_CTL_P1_MASK;
+ rgmii_ctl |= (port_xmii << RGMII_CTL_P1_SHIFT);
+ } else {
+ ltq_writel(&switch_regs->p0_ctl, port_ctl);
+
+ rgmii_ctl &= ~RGMII_CTL_P0_MASK;
+ rgmii_ctl |= port_xmii;
+ }
+
+ ltq_writel(&switch_regs->rgmii_ctl, rgmii_ctl);
+
+ /* Connect to external switch */
+ if (port->flags & LTQ_ETH_PORT_SWITCH) {
+ sw = switch_connect(priv->bus);
+ if (sw)
+ switch_setup(sw);
+ }
+
+ /* Connect to internal/external PHYs */
+ if (port->flags & LTQ_ETH_PORT_PHY) {
+ phydev = phy_connect(priv->bus, port->phy_addr, priv->dev,
+ port->phy_if);
+ if (phydev)
+ phy_config(phydev);
+
+ priv->phymap[port->num] = phydev;
+ }
+}
+
+int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)
+{
+ struct eth_device *dev;
+ struct mii_dev *bus;
+ struct ltq_eth_priv *priv;
+ struct ltq_dma_device *dma_dev;
+ const struct ltq_eth_port_config *port = &board_config->ports[0];
+ int i, ret;
+
+ build_check_ar9_registers();
+
+ ltq_dma_init();
+ ltq_eth_hw_init(port);
+
+ dev = calloc(1, sizeof(*dev));
+ if (!dev)
+ return -1;
+
+ priv = calloc(1, sizeof(*priv));
+ if (!priv)
+ return -1;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -1;
+
+ sprintf(dev->name, LTQ_ETH_DRV_NAME);
+ dev->priv = priv;
+ dev->init = ltq_eth_init;
+ dev->halt = ltq_eth_halt;
+ dev->recv = ltq_eth_recv;
+ dev->send = ltq_eth_send;
+
+ sprintf(bus->name, LTQ_MDIO_DRV_NAME);
+ bus->read = ltq_mdio_read;
+ bus->write = ltq_mdio_write;
+ bus->priv = priv;
+
+ dma_dev = &priv->dma_dev;
+ dma_dev->port = 0;
+ dma_dev->rx_chan.chan_no = 0;
+ dma_dev->rx_chan.class = 0;
+ dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;
+ dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
+ dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;
+ dma_dev->tx_chan.chan_no = 1;
+ dma_dev->tx_chan.class = 0;
+ dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;
+ dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
+ dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;
+
+ priv->bus = bus;
+ priv->dev = dev;
+
+ ret = ltq_dma_register(dma_dev);
+ if (ret)
+ return ret;
+
+ ret = mdio_register(bus);
+ if (ret)
+ return ret;
+
+ ret = eth_register(dev);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < board_config->num_ports; i++)
+ ltq_eth_port_config(priv, &board_config->ports[i]);
+
+ return 0;
+}

477
package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch Normal file
View File

@@ -0,0 +1,477 @@
From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: tools: add some helper tools for Lantiq SoCs
Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/tools/gct.pl
@@ -0,0 +1,155 @@
+#!/usr/bin/perl
+
+#use strict;
+#use Cwd;
+#use Env;
+
+my $aline;
+my $lineid;
+my $length;
+my $address;
+my @bytes;
+my $addstr;
+my $chsum=0;
+my $count=0;
+my $firstime=1;
+my $i;
+my $currentaddr;
+my $tmp;
+my $holder="";
+my $loadaddr;
+
+if(@ARGV < 2){
+ die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
+}
+
+open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
+open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
+open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
+
+$i=0;
+while ($line = <IN_UART_DDR_SETTINGS>){
+ if($line=~/\w/){
+ if($line!~/[;#\*]/){
+ if($i eq 0){
+ printf OUT_UBOOT_ASC ("33333333");
+ }
+ chomp($line);
+ $line=~s/\t//;
+ @array=split(/ +/,$line);
+ $j=0;
+ while(@array[$j]!~/\w/){
+ $j=$j+1;
+ }
+ $addr=@array[$j];
+ $regval=@array[$j+1];
+ $addr=~s/0x//;
+ $regval=~s/0x//;
+ printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
+ $i=$i+1;
+ if($i eq 8){
+ $i=0;
+ printf OUT_UBOOT_ASC ("\n");
+ }
+ }
+ }
+}
+
+while($i lt 8 && $i gt 0){
+ printf OUT_UBOOT_ASC "00"x8;
+ $i=$i+1;
+}
+
+if($i eq 8){
+ printf OUT_UBOOT_ASC ("\n");
+}
+
+while($aline=<IN_UART_SREC>){
+ $aline=uc($aline);
+ chomp($aline);
+ next if(($aline=~/^S0/) || ($aline=~/^S7/));
+ ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
+ $length = hex($length);
+ $address = hex($address);
+ $length -=5;
+ $i=0;
+
+ while($length>0){
+ if($firstime==1){
+ $addstr = sprintf("%x", $address);
+ $addstr = "0"x(8-length($addstr)).$addstr;
+ print OUT_UBOOT_ASC $addstr;
+ addchsum($addstr);
+ $firstime=0;
+ $currentaddr=$address;
+ $loadaddr = $addstr;
+ }
+ else{
+ if($count==64){
+ $addstr = sprintf("%x", $currentaddr);
+ $addstr = "0"x(8-length($addstr)).$addstr;
+ print OUT_UBOOT_ASC $addstr;
+ addchsum($addstr);
+ $count=0;
+ }
+#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
+ }
+ if($currentaddr < $address) {
+ print OUT_UBOOT_ASC "00";
+ addchsum("00");
+ $count++;
+ $currentaddr++;
+ }
+ else {
+ while($count<64){
+ $bytes[$i]=~tr/ABCDEF/abcdef/;
+ print OUT_UBOOT_ASC "$bytes[$i]";
+ addchsum($bytes[$i]);
+ $i++;
+ $count++;
+ $currentaddr++;
+ $length--;
+ last if($length==0);
+ }
+ }
+ if($count==64){
+ print OUT_UBOOT_ASC "\n";
+ }
+ }
+}
+if($count != 64){
+ $tmp = "00";
+ for($i=0;$i<(64-$count);$i++){
+ print OUT_UBOOT_ASC "00";
+ addchsum($tmp);
+ }
+ print OUT_UBOOT_ASC "\n";
+}
+
+
+print OUT_UBOOT_ASC "11"x4;
+use integer;
+$chsum=$chsum & 0xffffffff;
+$chsum = sprintf("%X", $chsum);
+$chsum = "0"x(8-length($chsum)).$chsum;
+$chsum =~tr/ABCDEF/abcdef/;
+print OUT_UBOOT_ASC $chsum;
+print OUT_UBOOT_ASC "00"x60;
+print OUT_UBOOT_ASC "\n";
+
+print OUT_UBOOT_ASC "99"x4;
+print OUT_UBOOT_ASC $loadaddr;
+print OUT_UBOOT_ASC "00"x60;
+print OUT_UBOOT_ASC "\n";
+
+close OUT_UBOOT_ASC;
+
+sub addchsum{
+ my $cc=$_[0];
+ $holder=$holder.$cc;
+ if(length($holder)==8){
+ $holder = hex($holder);
+ $chsum+=$holder;
+ $holder="";
+ }
+}
--- /dev/null
+++ b/tools/lantiq_bdi_conf.awk
@@ -0,0 +1,116 @@
+#!/usr/bin/awk -f
+#
+# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#
+# Usage:
+# awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
+#
+# Additional information:
+# http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+function print_header()
+{
+ print "; "
+ print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org> "
+ print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
+ print "; "
+ print "; This file has been generated with lantiq_bdi_conf.awk script. "
+ print "; "
+ print "; SPDX-License-Identifier: GPL-2.0+ "
+ print "; "
+ print ""
+}
+
+function init_ar9_prologue()
+{
+ print "WM32 0xBF103010 0x80 ; CGU for CPU 333Mhz, DDR 167Mhz"
+ print "WM32 0xBF103014 0x01 ; CGU update"
+ print "WM32 0xBF800010 0x0 ; Clear error access log register"
+ print "WM32 0xBF800020 0x0 ; Clear error access log register"
+ print "WM32 0xBF800060 0xD ; Enable FPI, DDR and SRAM module in memory controller"
+ print "WM32 0xBF801030 0x0 ; Clear start bit of DDR memory controller"
+}
+
+function init_ar9_epilogue()
+{
+ print "WM32 0xBE105360 0x4001D7FF ; EBU setup"
+}
+
+function init_ddr1_epilogue()
+{
+ print "WM32 0xBF801030 0x100 ; Set start bit of DDR memory controller"
+}
+
+function ar9_target()
+{
+ print "CPUTYPE M34K"
+ print "ENDIAN BIG"
+ print "JTAGCLOCK 1"
+ print "BDIMODE AGENT ; [ LOADONLY, AGENT ]"
+ print "RESET JTAG ; [ NONE, JTAG, HARD ]"
+ print "POWERUP 100"
+ print "WAKEUP 100"
+ print "BREAKMODE HARD ; [ SOFT, HARD ]"
+ print "STEPMODE SWBP ; [ JTAG, HWBP, SWBP ]"
+ print "VECTOR CATCH"
+ print "SCANSUCC 1 5"
+}
+
+function flash_p2601hnfx()
+{
+ print "CHIPTYPE MIRRORX16"
+ print "CHIPSIZE 0x1000000"
+ print "BUSWIDTH 16"
+}
+
+BEGIN {
+ switch (soc) {
+ case "ar9":
+ reg_base = 0xbf801000
+ print_header()
+ print "[INIT]"
+ init_ar9_prologue()
+ break
+ default:
+ print "Invalid or no value for SoC specified!"
+ exit 1
+ }
+}
+
+/^#define/ {
+ /* DC03 contains MC enable bit and must not be set here */
+ if (tolower($2) != "mc_dc03_value")
+ printf("WM32 0x%x %s\n", reg_base, tolower($3))
+
+ reg_base += 0x10
+}
+
+END {
+ switch (soc) {
+ case "ar9":
+ init_ddr1_epilogue()
+ init_ar9_epilogue()
+ print ""
+ print "[TARGET]"
+ ar9_target()
+ print ""
+ print "[HOST]"
+ print "PROMPT \"ar9> \""
+ print ""
+ break
+ default:
+ }
+
+ switch (board) {
+ case "p2601hnfx":
+ print "[FLASH]"
+ flash_p2601hnfx()
+ print ""
+ break
+ default:
+ }
+}
--- /dev/null
+++ b/tools/lantiq_ram_extract_magic.awk
@@ -0,0 +1,69 @@
+#
+# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+#
+# Usage:
+# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+BEGIN {
+ print "/* "
+ print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
+ print " * "
+ print " * This file has been generated with lantiq_ram_extract_magic.awk script. "
+ print " * "
+ print " * SPDX-License-Identifier: GPL-2.0+ "
+ print " */ "
+ print ""
+
+ mc_dc_value=0
+ mc_dc_number=0
+ right_section=0
+ mc_dc_value_print=0
+ mc_dc_number_print=0
+}
+
+/t2,[0-9]+$/ {
+ if (right_section) {
+ split($4, tmp, ",")
+ mc_dc_value=sprintf("%X", tmp[2])
+ mc_dc_value_print=1
+ }
+}
+
+/t2,0x[0-9a-f]+$/ {
+ if (right_section) {
+ split($4, tmp, ",0x")
+ mc_dc_value=sprintf("%s", tmp[2])
+ mc_dc_value=toupper(mc_dc_value)
+ mc_dc_value_print=1
+ }
+}
+
+/t2,[0-9]+\(t1\)$/ {
+ if (right_section) {
+ split($4, tmp, ",")
+ split(tmp[2], tmp, "(")
+ mc_dc_number=tmp[1]/16
+ mc_dc_number_print=1
+ }
+}
+
+{
+ if (right_section && mc_dc_number_print && mc_dc_value_print) {
+ if (mc_dc_number < 10)
+ print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
+ else
+ print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
+ mc_dc_value_print=0
+ mc_dc_number_print=0
+ }
+
+ if ($4 == "t1,t1,0x1000")
+ right_section=1
+
+
+ if ($4 == "t2,736(t1)")
+ right_section=0
+}
--- /dev/null
+++ b/tools/lantiq_ram_init_uart.awk
@@ -0,0 +1,117 @@
+#!/usr/bin/awk -f
+#
+# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
+# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#
+# Usage:
+# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+function print_header()
+{
+ print "; "
+ print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
+ print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
+ print "; "
+ print "; This file has been generated with lantiq_ram_init_uart.awk script. "
+ print "; "
+ print "; SPDX-License-Identifier: GPL-2.0+ "
+ print ""
+}
+
+function mc_danube_prologue()
+{
+ /* Clear access error log registers */
+ print "0xbf800010", "0x0"
+ print "0xbf800020", "0x0"
+
+ /* Enable DDR and SRAM module in memory controller */
+ print "0xbf800060", "0x5"
+
+ /* Clear start bit of DDR memory controller */
+ print "0xbf801030", "0x0"
+}
+
+function mc_ar9_prologue()
+{
+ /* Clear access error log registers */
+ print "0xbf800010", "0x0"
+ print "0xbf800020", "0x0"
+
+ /* Enable FPI, DDR and SRAM module in memory controller */
+ print "0xbf800060", "0xD"
+
+ /* Clear start bit of DDR memory controller */
+ print "0xbf801030", "0x0"
+}
+
+function mc_ddr1_epilogue()
+{
+ /* Set start bit of DDR memory controller */
+ print "0xbf801030", "0x100"
+}
+
+function mc_ddr2_prologue()
+{
+ /* Put memory controller in inactive mode */
+ print "0xbf401070", "0x0"
+}
+
+function mc_ddr2_epilogue(mc_ccr07_value)
+{
+ /* Put memory controller in active mode */
+ mc_ccr07_value = or(mc_ccr07_value, 0x100)
+ printf("0xbf401070 0x%x\n", mc_ccr07_value)
+}
+
+BEGIN {
+ switch (soc) {
+ case "danube":
+ reg_base = 0xbf801000
+ print_header()
+ mc_danube_prologue()
+ break
+ case "ar9":
+ reg_base = 0xbf801000
+ print_header()
+ mc_ar9_prologue()
+ break
+ case "vr9":
+ reg_base = 0xbf401000
+ print_header()
+ mc_ddr2_prologue()
+ break
+ default:
+ print "Invalid or no value for soc specified!"
+ exit 1
+ }
+
+ mc_ccr07_value = 0
+}
+
+/^#define/ {
+ /* CCR07 contains MC enable bit and must not be set here */
+ if (tolower($2) == "mc_ccr07_value")
+ mc_ccr07_value = strtonum($3)
+ if (tolower($2) == "mc_dc03_value")
+ /* CCR07 contains MC enable bit and must not be set here */
+ else
+ printf("0x%x %s\n", reg_base, tolower($3))
+
+ reg_base += 0x10
+}
+
+END {
+ switch (soc) {
+ case "danube":
+ case "ar9":
+ mc_ddr1_epilogue()
+ break
+ case "vr9":
+ mc_ddr2_epilogue(mc_ccr07_value)
+ break
+ default:
+ }
+}

223
package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch Normal file
View File

@@ -0,0 +1,223 @@
From 43b9a7c9b903302c56d0a1d292a146dbf4de8e49 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 12 Aug 2013 01:17:08 +0200
Subject: tools: lantiq: add NAND SPL support
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/tools/ltq-boot-image.c
+++ b/tools/ltq-boot-image.c
@@ -14,7 +14,8 @@
enum image_types {
IMAGE_NONE,
- IMAGE_SFSPL
+ IMAGE_SFSPL,
+ IMAGE_NANDSPL
};
/* Lantiq non-volatile bootstrap command IDs */
@@ -43,6 +44,8 @@ enum nvb_cmd_flags {
struct args {
enum image_types type;
__u32 entry_addr;
+ off_t uboot_offset;
+ unsigned int page_size;
const char *uboot_bin;
const char *spl_bin;
const char *out_bin;
@@ -50,10 +53,11 @@ struct args {
static void usage_msg(const char *name)
{
- fprintf(stderr, "%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\n",
+ fprintf(stderr, "%s: [-h] -t type -e entry-addr [-x uboot-offset] [-p page-size] -u uboot-bin [-s spl-bin] -o out-bin\n",
name);
fprintf(stderr, " Image types:\n"
- " sfspl - SPL + [compressed] U-Boot for SPI flash\n");
+ " sfspl - SPL + [compressed] U-Boot for SPI flash\n"
+ " nandspl - SPL + [compressed] U-Boot for NAND flash\n");
}
static enum image_types parse_image_type(const char *type)
@@ -64,6 +68,9 @@ static enum image_types parse_image_type
if (!strncmp(type, "sfspl", 6))
return IMAGE_SFSPL;
+ if (!strncmp(type, "nandspl", 6))
+ return IMAGE_NANDSPL;
+
return IMAGE_NONE;
}
@@ -73,7 +80,7 @@ static int parse_args(int argc, char *ar
memset(arg, 0, sizeof(*arg));
- while ((opt = getopt(argc, argv, "ht:e:u:s:o:")) != -1) {
+ while ((opt = getopt(argc, argv, "ht:e:x:p:u:s:o:")) != -1) {
switch (opt) {
case 'h':
usage_msg(argv[0]);
@@ -84,6 +91,12 @@ static int parse_args(int argc, char *ar
case 'e':
arg->entry_addr = strtoul(optarg, NULL, 16);
break;
+ case 'x':
+ arg->uboot_offset = strtoul(optarg, NULL, 16);
+ break;
+ case 'p':
+ arg->page_size = strtoul(optarg, NULL, 10);
+ break;
case 'u':
arg->uboot_bin = optarg;
break;
@@ -114,11 +127,22 @@ static int parse_args(int argc, char *ar
goto parse_error;
}
- if (arg->type == IMAGE_SFSPL && !arg->spl_bin) {
+ if ((arg->type == IMAGE_SFSPL || arg->type == IMAGE_NANDSPL) &&
+ !arg->spl_bin) {
fprintf(stderr, "Missing SPL binary\n");
goto parse_error;
}
+ if (arg->type == IMAGE_NANDSPL && !arg->uboot_offset) {
+ fprintf(stderr, "Missing U-Boot offset\n");
+ goto parse_error;
+ }
+
+ if (arg->type == IMAGE_NANDSPL && !arg->page_size) {
+ fprintf(stderr, "Missing NAND page size\n");
+ goto parse_error;
+ }
+
return 0;
parse_error:
@@ -174,6 +198,19 @@ static int write_nvb_start_header(int fd
return write_header(fd, hdr, sizeof(hdr));
}
+#if 0
+static int write_nvb_regcfg_header(int fd, __u32 addr)
+{
+ __u32 hdr[2];
+
+ hdr[0] = build_nvb_command(NVB_CMD_REGCFG, NVB_FLAG_SDBG |
+ NVB_FLAG_DBG);
+ hdr[1] = cpu_to_be32(addr);
+
+ return write_header(fd, hdr, sizeof(hdr));
+}
+#endif
+
static int open_input_bin(const char *name, void **ptr, size_t *size)
{
struct stat sbuf;
@@ -238,9 +275,37 @@ static int open_output_bin(const char *n
return fd;
}
-static int create_sfspl(const struct args *arg)
+static int pad_to_offset(int fd, off_t offset)
{
- int out_fd, uboot_fd, spl_fd, ret;
+ off_t pos;
+ size_t size;
+ ssize_t n;
+ __u8 *buf;
+
+ pos = lseek(fd, 0, SEEK_CUR);
+ size = offset - pos;
+
+ buf = malloc(size);
+ if (!buf) {
+ fprintf(stderr, "Failed to malloc buffer\n");
+ return -1;
+ }
+
+ memset(buf, 0xff, size);
+ n = write(fd, buf, size);
+ free(buf);
+
+ if (n != size) {
+ fprintf(stderr, "Failed to write pad bytes\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int create_spl_image(const struct args *arg)
+{
+ int out_fd, uboot_fd, spl_fd, ret = 0;
void *uboot_ptr, *spl_ptr;
size_t uboot_size, spl_size;
@@ -256,9 +321,22 @@ static int create_sfspl(const struct arg
if (0 > uboot_fd)
goto err_uboot;
+#if 0
+ ret = write_nvb_regcfg_header(out_fd, 0);
+ if (ret)
+ goto err_write;
+#endif
+
ret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr);
if (ret)
goto err_write;
+#if 0
+ if (arg->page_size) {
+ ret = pad_to_offset(out_fd, arg->page_size);
+ if (ret)
+ goto err_write;
+ }
+#endif
ret = copy_bin(out_fd, spl_ptr, spl_size);
if (ret)
@@ -268,16 +346,16 @@ static int create_sfspl(const struct arg
if (ret)
goto err_write;
+ if (arg->uboot_offset) {
+ ret = pad_to_offset(out_fd, arg->uboot_offset);
+ if (ret)
+ goto err_write;
+ }
+
ret = copy_bin(out_fd, uboot_ptr, uboot_size);
if (ret)
goto err_write;
- close_input_bin(uboot_fd, uboot_ptr, uboot_size);
- close_input_bin(spl_fd, spl_ptr, spl_size);
- close(out_fd);
-
- return 0;
-
err_write:
close_input_bin(uboot_fd, uboot_ptr, uboot_size);
err_uboot:
@@ -285,7 +363,7 @@ err_uboot:
err_spl:
close(out_fd);
err:
- return -1;
+ return ret;
}
int main(int argc, char *argv[])
@@ -299,7 +377,8 @@ int main(int argc, char *argv[])
switch (arg.type) {
case IMAGE_SFSPL:
- ret = create_sfspl(&arg);
+ case IMAGE_NANDSPL:
+ ret = create_spl_image(&arg);
break;
default:
fprintf(stderr, "Image type not implemented\n");

46
package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch Normal file
View File

@@ -0,0 +1,46 @@
From 2e01dc015bc8bb9ca45f369025c342ede990863e Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 12 Aug 2013 01:16:09 +0200
Subject: Makefile: add Lantiq NAND SPL images
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/.gitignore
+++ b/.gitignore
@@ -54,6 +54,9 @@
/u-boot.ltq.lzma.norspl
/u-boot.ltq.lzo.norspl
/u-boot.ltq.norspl
+/u-boot.ltq.lzma.nandspl
+/u-boot.ltq.lzo.nandspl
+/u-boot.ltq.nandspl
/u-boot.lzma.img
/u-boot.lzo.img
--- a/Makefile
+++ b/Makefile
@@ -599,6 +599,24 @@ $(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boo
$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
-s $(obj)spl/u-boot-spl.bin -u $< -o $@
+$(obj)u-boot.ltq.nandspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
+ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
+ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
+ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \
+ -s $(obj)spl/u-boot-spl.bin -u $< -o $@
+
+$(obj)u-boot.ltq.lzo.nandspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
+ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
+ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
+ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \
+ -s $(obj)spl/u-boot-spl.bin -u $< -o $@
+
+$(obj)u-boot.ltq.lzma.nandspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
+ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \
+ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \
+ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \
+ -s $(obj)spl/u-boot-spl.bin -u $< -o $@
+
$(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
cat $(obj)spl/u-boot-spl.bin $< > $@

165
package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch Normal file
View File

@@ -0,0 +1,165 @@
From e17398316e82d8b28217232b4fd6030c65138e74 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 12 Aug 2013 01:18:00 +0200
Subject: MIPS: lantiq: add NAND SPL support
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/arch/mips/cpu/mips32/lantiq-common/spl.c
+++ b/arch/mips/cpu/mips32/lantiq-common/spl.c
@@ -8,6 +8,7 @@
#include <image.h>
#include <version.h>
#include <spi_flash.h>
+#include <nand.h>
#include <linux/compiler.h>
#include <lzma/LzmaDec.h>
#include <linux/lzo.h>
@@ -63,6 +64,18 @@
#define spl_boot_nor_flash 0
#endif
+#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)
+#define spl_boot_nand_flash 1
+#else
+#define spl_boot_nand_flash 0
+#ifndef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#endif
+#ifndef CONFIG_SYS_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0
+#endif
+#endif
+
#define spl_sync() __asm__ __volatile__("sync");
struct spl_image {
@@ -337,6 +350,58 @@ static int spl_load_nor_flash(struct spl
return ret;
}
+static int spl_load_nand_flash(struct spl_image *spl)
+{
+ image_header_t *hdr;
+ int ret;
+ unsigned long loadaddr;
+
+ /*
+ * Image format:
+ *
+ * - 12 byte non-volatile bootstrap header
+ * - SPL binary
+ * - 12 byte non-volatile bootstrap header
+ * - padding bytes up to CONFIG_SYS_NAND_U_BOOT_OFFS
+ * - 64 byte U-Boot mkimage header
+ * - U-Boot binary
+ */
+ spl->data_addr = CONFIG_SYS_NAND_U_BOOT_OFFS;
+
+ spl_puts("SPL: initializing NAND flash\n");
+ nand_init();
+
+ spl_debug("SPL: reading image header at page offset %lx\n",
+ spl->data_addr);
+
+ hdr = (image_header_t *) CONFIG_LOADADDR;
+ ret = nand_spl_load_image(spl->data_addr,
+ CONFIG_SYS_NAND_PAGE_SIZE, hdr);
+ if (ret)
+ return ret;
+
+ spl_debug("SPL: checking image header at address %p\n", hdr);
+
+ ret = spl_parse_image(hdr, spl);
+ if (ret)
+ return ret;
+
+ if (spl_is_compressed(spl))
+ loadaddr = CONFIG_LOADADDR;
+ else
+ loadaddr = spl->entry_addr;
+
+ spl_puts("SPL: loading U-Boot to RAM\n");
+
+ ret = nand_spl_load_image(spl->data_addr, spl->data_size,
+ (void *) loadaddr);
+
+ if (spl_is_compressed(spl))
+ ret = spl_uncompress(spl, loadaddr);
+
+ return ret;
+}
+
static int spl_load(struct spl_image *spl)
{
int ret;
@@ -345,6 +410,8 @@ static int spl_load(struct spl_image *sp
ret = spl_load_spi_flash(spl);
else if (spl_boot_nor_flash)
ret = spl_load_nor_flash(spl);
+ else if (spl_boot_nand_flash)
+ ret = spl_load_nand_flash(spl);
else
ret = 1;
--- a/arch/mips/include/asm/lantiq/config.h
+++ b/arch/mips/include/asm/lantiq/config.h
@@ -40,6 +40,26 @@
#define CONFIG_SPI_SPL_SIMPLE
#endif
+/*
+ * NAND flash SPL
+ * BOOT CFG 06 only (address cycle based probing, 2KB or 512B page size)
+ */
+#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_ECC
+
+/* use software ECC until driver supports HW ECC */
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_ECCSIZE 256
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63}
+#endif
+
#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)
#define CONFIG_SPL
#endif
@@ -148,6 +168,21 @@
#define CONFIG_ENV_LOAD_UBOOT_SF
#endif
+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
+#define CONFIG_ENV_WRITE_UBOOT_NAND \
+ "write-uboot-nand=" \
+ "nand erase 0 $filesize && " \
+ "nand write $fileaddr 0 $filesize\0"
+
+#define CONFIG_ENV_LOAD_UBOOT_NAND \
+ "load-uboot-nandspl=tftpboot u-boot.ltq.nandspl\0" \
+ "load-uboot-nandspl-lzo=tftpboot u-boot.ltq.lzo.nandspl\0" \
+ "load-uboot-nandspl-lzma=tftpboot u-boot.ltq.lzma.nandspl\0"
+#else
+#define CONFIG_ENV_WRITE_UBOOT_NAND
+#define CONFIG_ENV_LOAD_UBOOT_NAND
+#endif
+
#define CONFIG_ENV_LANTIQ_DEFAULTS \
CONFIG_ENV_CONSOLEDEV \
CONFIG_ENV_ADDCONSOLE \
@@ -159,6 +194,8 @@
CONFIG_ENV_LOAD_UBOOT_NOR \
CONFIG_ENV_SF_PROBE \
CONFIG_ENV_WRITE_UBOOT_SF \
- CONFIG_ENV_LOAD_UBOOT_SF
+ CONFIG_ENV_LOAD_UBOOT_SF \
+ CONFIG_ENV_WRITE_UBOOT_NAND \
+ CONFIG_ENV_LOAD_UBOOT_NAND
#endif /* __LANTIQ_CONFIG_H__ */

30
package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch Normal file
View File

@@ -0,0 +1,30 @@
From 7361581a1baaec43058f5b9350c32c7ac4e58064 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 12 Aug 2013 00:11:16 +0200
Subject: MIPS: vrx200: add NAND SPL support
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/arch/mips/cpu/mips32/vrx200/config.mk
+++ b/arch/mips/cpu/mips32/vrx200/config.mk
@@ -27,4 +27,9 @@ ALL-y += $(obj)u-boot.ltq.norspl
ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
endif
+ifdef CONFIG_SYS_BOOT_NANDSPL
+ALL-y += $(obj)u-boot.ltq.nandspl
+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.nandspl
+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.nandspl
+endif
endif
--- a/arch/mips/include/asm/arch-vrx200/config.h
+++ b/arch/mips/include/asm/arch-vrx200/config.h
@@ -167,7 +167,7 @@
#define CONFIG_SYS_TEXT_BASE 0xB0000000
#endif
-#if defined(CONFIG_SYS_BOOT_SFSPL)
+#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SPL_TEXT_BASE 0xBE220000
#endif

51
package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch Normal file
View File

@@ -0,0 +1,51 @@
From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Sat, 17 Aug 2013 03:44:46 +0200
Subject: MIPS: lantiq: add default openwrt config
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/openwrt-lantiq-common.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OPENWRT_LANTIQ_COMMON_H
+#define __OPENWRT_LANTIQ_COMMON_H
+
+/* Commands */
+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_TFTPPUT
+#endif
+
+/* Compression */
+#define CONFIG_LZMA
+
+/* Auto boot */
+#define CONFIG_BOOTDELAY 2
+
+/* Environment */
+#if !defined(CONFIG_SYS_BOOT_RAM)
+#define CONFIG_BOOTCOMMAND \
+ "bootm ${kernel_addr}"
+#endif
+
+/* Ethernet */
+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
+#define CONFIG_ETHADDR 00:01:02:03:04:05
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_IPADDR 192.168.1.1
+#endif
+
+/* Unnecessary */
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#endif /* __OPENWRT_LANTIQ_COMMON_H */

39
package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch Normal file
View File

@@ -0,0 +1,39 @@
From: Antonios Vamporakis <ant@area128.com>
Date: Tue, 31 Dec 2013 01:05:42 +0100
Subject: [PATCH] lzma: fix buffer bound check error
Variable uncompressedSize references the space available, while outSizeFull is
the actual expected uncompressed size. Using the wrong value causes LzmaDecode
to return SZ_ERROR_INPUT_EOF. Problem was introduced in commit afca294. While
at it add additional debug message.
Signed-off-by: Antonios Vamporakis <ant@area128.com>
CC: Kees Cook <keescook@chromium.org>
CC: Simon Glass <sjg@chromium.org>
CC: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
CC: Luka Perkov <luka@openwrt.org>
---
lib/lzma/LzmaTools.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/lib/lzma/LzmaTools.c
+++ b/lib/lzma/LzmaTools.c
@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned c
return SZ_ERROR_OUTPUT_EOF;
/* Decompress */
- outProcessed = *uncompressedSize;
+ outProcessed = outSizeFull;
WATCHDOG_RESET();
@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned c
inStream + LZMA_DATA_OFFSET, &compressedSize,
inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
*uncompressedSize = outProcessed;
+
+ debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed);
+
if (res != SZ_OK) {
return res;
}

18
package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch Normal file
View File

@@ -0,0 +1,18 @@
From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sun, 20 Oct 2013 19:39:17 +0200
Subject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
VERSION = 2013
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -openwrt4
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else

148
package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch Normal file
View File

@@ -0,0 +1,148 @@
From patchwork Tue Jan 20 11:28:45 2015
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image
From: Ben Mulvihill <ben.mulvihill@gmail.com>
X-Patchwork-Id: 431024
Message-Id: <1421753325.25187.58.camel@merveille.lan>
To: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: OpenWrt Development List <openwrt-devel@lists.openwrt.org>
Date: Tue, 20 Jan 2015 12:28:45 +0100
On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote:
> On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote:
> > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote:
> > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill <ben.mulvihill@gmail.com>:
> > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote:
> > > >> On 19/01/15 10:46, Ben Mulvihill wrote:
> > > >> > Hello,
> > > >> >
> > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq
> > > >> > ar9), and am wondering where to initialise the cgu, in the case
> > > >> > of a ramboot image for uart booting. Normally the cgu is initialised
> > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The
> > > >> > result is that the board boots with the wrong cgu settings, which
> > > >> > sends the console haywire. So far I have tried two solutions:
> > > >>
> > > >> Another option is to try and not change anything. The console is already
> > > >> configured and running. The ram does need config.
> > > >>
> > > >> I was used to seeing the ramboot version running at half clock speed, at
> > > >> least on danube, previous to ar9.
> > > >>
> > > >> Conor
> > > >
> > > > Hi Conor,
> > > >
> > > > Thanks for the reply. But with the latest uboot-lantiq, not changing
> > > > anything means that I don't get a usable console. With an older
> > > > version I do at least get a uboot console, but no linux console when
> > > > I boot openwrt. Correcting the cgu settings solves both problems.
> > > >
> > >
> > > could you try this?
> > >
> > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c
> > > b/arch/mips/cpu/mips32/arx100/cgu.c
> > > index 6e71ee7..e0afbda 100644
> > > --- a/arch/mips/cpu/mips32/arx100/cgu.c
> > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c
> > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void)
> > >
> > > unsigned long ltq_get_bus_clock(void)
> > > {
> > > - u32 fpi_sel;
> > > - unsigned long clk;
> > > -
> > > - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
> > > -
> > > - if (fpi_sel)
> > > - clk = ltq_get_io_region_clock() / 2;
> > > - else
> > > - clk = ltq_get_io_region_clock();
> > > -
> > > - return clk;
> > > + return ltq_get_io_region_clock();
> > > }
> > >
> > > the UART driver calculates the baudrate from the FPI bus clock, but
> > > FPI_SEL is not available on AR9. FPI bus clock is always the same as
> > > DDR clock, Obviously a copy&paste error from VR9 code ;)
> > >
> >
> > No, even with this patch, I still don't get a working console I'm
> > afraid. If I don't set anything explicitly, the board comes up with
> > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ |
> > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK.
> > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ?
> > I don't understand what CGU_SYS_PPESEL_250_MHZ does?
> > The "right setting", as set by the stock uboot, is 0x80.
>
> P.S. There also seems to be a discrepancy between the uboot and
> linux code. I take it from what you say above that fpi clock, ddr
> clock and io region clock are all the same. Now if the least
> significant bit of CGU_SYS is set, then according to the uboot
> code - function ltq_get_bus_clock() - their value is one
> third of the system clock. But according to the linux code
> - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c -
> their value in this case is equal to the system clock.
>
> Or am I getting muddled? It's past my bedtime!
>
>
Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1
out. A patch along these lines should fix it:
--- a/arch/mips/cpu/mips32/arx100/cgu.c
+++ b/arch/mips/cpu/mips32/arx100/cgu.c
@@ -10,12 +10,17 @@
#include <asm/lantiq/clk.h>
#include <asm/lantiq/io.h>
-#define CGU_SYS_DDR_SEL (1 << 0)
-#define CGU_SYS_CPU_SEL (1 << 2)
+#define CGU_SYS_DDR_SHIFT 0
+#define CGU_SYS_CPU_SHIFT 2
#define CGU_SYS_SYS_SHIFT 3
+#define CGU_SYS_FPI_SHIFT 6
+#define CGU_SYS_PPE_SHIFT 7
+
+#define CGU_SYS_DDR_MASK (1 << CGU_SYS_DDR_SHIFT)
+#define CGU_SYS_CPU_MASK (1 << CGU_SYS_CPU_SHIFT)
#define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT)
-#define CGU_SYS_FPI_SEL (1 << 6)
-#define CGU_SYS_PPE_SEL (1 << 7)
+#define CGU_SYS_FPI_MASK (1 << CGU_SYS_FPI_SHIFT)
+#define CGU_SYS_PPE_MASK (1 << CGU_SYS_PPE_SHIFT)
struct ltq_cgu_regs {
u32 rsvd0;
@@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo
u32 ddr_sel;
unsigned long clk;
- ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);
+ ddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT);
if (ddr_sel)
clk = ltq_get_system_clock() / 3;
@@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void)
u32 cpu_sel;
unsigned long clk;
- cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);
+ cpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT);
if (cpu_sel)
clk = ltq_get_io_region_clock();
@@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void)
u32 fpi_sel;
unsigned long clk;
- fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
+ fpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT);
if (fpi_sel)
clk = ltq_get_io_region_clock() / 2;

97
package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch Normal file
View File

@@ -0,0 +1,97 @@
From b11c5d1dc29e81326d1215011d19377737082aeb Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 1 Jul 2015 16:36:43 +0200
Subject: [PATCH] MIPS: change 'extern inline' to 'static inline'
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.
Reported-by: Andy Kennedy <andy.kennedy@adtran.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/include/asm/io.h | 12 ++++++------
arch/mips/include/asm/system.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -118,7 +118,7 @@ static inline void set_io_port_base(unsi
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
-extern inline phys_addr_t virt_to_phys(volatile void * address)
+static inline phys_addr_t virt_to_phys(volatile void * address)
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
@@ -127,7 +127,7 @@ extern inline phys_addr_t virt_to_phys(v
#endif
}
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
@@ -139,7 +139,7 @@ extern inline void * phys_to_virt(unsign
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
@@ -148,7 +148,7 @@ extern inline unsigned long virt_to_bus(
#endif
}
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
@@ -166,12 +166,12 @@ extern unsigned long isa_slot_offset;
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
#if 0
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -23,7 +23,7 @@
#include <linux/kernel.h>
#endif
-extern __inline__ void
+static __inline__ void
__sti(void)
{
__asm__ __volatile__(
@@ -47,7 +47,7 @@ __sti(void)
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
-extern __inline__ void
+static __inline__ void
__cli(void)
{
__asm__ __volatile__(
@@ -208,7 +208,7 @@ do { \
* For 32 and 64 bit operands we can take advantage of ll and sc.
* FIXME: This doesn't work for R3000 machines.
*/
-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
{
#ifdef CONFIG_CPU_HAS_LLSC
unsigned long dummy;

26
package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch Normal file
View File

@@ -0,0 +1,26 @@
From 3422299dc28fa8257677d03cc1253e3c9bf17e9f Mon Sep 17 00:00:00 2001
From: Jeroen Hofstee <jeroen@myspectrum.nl>
Date: Thu, 26 Jun 2014 20:18:31 +0200
Subject: [PATCH] common: main.c: make show_boot_progress __weak
This not only looks a bit better it also prevents a
warning with W=1 (no previous prototype).
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
---
common/main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/common/main.c
+++ b/common/main.c
@@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
-void inline __show_boot_progress (int val) {}
-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
+__weak void show_boot_progress(int val) {}
#define MAX_DELAY_STOP_STR 32

852
package/boot/uboot-lantiq/patches/0028-gcc-compat.patch Normal file
View File

@@ -0,0 +1,852 @@
From 9b2c282b348dfe966bbba967dc7a45ce817cce50 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 29 Feb 2016 11:34:15 -0500
Subject: [PATCH] compiler*.h: sync include/linux/compiler*.h with Linux
4.5-rc6
Copy these from Linux v4.5-rc6 tag.
This is needed so that we can keep up with newer gcc versions. Note
that we don't have the uapi/ hierarchy from the kernel so continue to
use <linux/types.h>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
include/linux/compiler-gcc.h | 266 ++++++++++++++++++++++++++++++++++------
include/linux/compiler-gcc3.h | 21 ----
include/linux/compiler-gcc4.h | 63 ----------
include/linux/compiler-intel.h | 45 +++++++
include/linux/compiler.h | 270 +++++++++++++++++++++++++++++++++++++++--
5 files changed, 534 insertions(+), 131 deletions(-)
delete mode 100644 include/linux/compiler-gcc3.h
delete mode 100644 include/linux/compiler-gcc4.h
create mode 100644 include/linux/compiler-intel.h
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 9896e54..22ab246 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -5,11 +5,28 @@
/*
* Common definitions for all gcc versions go here.
*/
-
+#define GCC_VERSION (__GNUC__ * 10000 \
+ + __GNUC_MINOR__ * 100 \
+ + __GNUC_PATCHLEVEL__)
/* Optimization barrier */
+
/* The "volatile" is due to gcc bugs */
#define barrier() __asm__ __volatile__("": : :"memory")
+/*
+ * This version is i.e. to prevent dead stores elimination on @ptr
+ * where gcc and llvm may behave differently when otherwise using
+ * normal barrier(): while gcc behavior gets along with a normal
+ * barrier(), llvm needs an explicit input variable to be assumed
+ * clobbered. The issue is as follows: while the inline asm might
+ * access any memory it wants, the compiler could have fit all of
+ * @ptr into memory registers instead, and since @ptr never escaped
+ * from that, it proofed that the inline asm wasn't touching any of
+ * it. This version works well with both compilers, i.e. we're telling
+ * the compiler that the inline asm absolutely may see the contents
+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
+ */
+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
/*
* This macro obfuscates arithmetic on a variable address so that gcc
@@ -29,41 +46,63 @@
* the inline assembly constraint from =g to =r, in this particular
* case either is valid.
*/
-#define RELOC_HIDE(ptr, off) \
- ({ unsigned long __ptr; \
- __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
- (typeof(ptr)) (__ptr + (off)); })
+#define RELOC_HIDE(ptr, off) \
+({ \
+ unsigned long __ptr; \
+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
+ (typeof(ptr)) (__ptr + (off)); \
+})
+
+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
+#define OPTIMIZER_HIDE_VAR(var) \
+ __asm__ ("" : "=r" (var) : "0" (var))
+#ifdef __CHECKER__
+#define __must_be_array(a) 0
+#else
/* &a[0] degrades to a pointer: a different type from an array */
-#define __must_be_array(a) \
- BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
+#endif
/*
* Force always-inline if the user requests it so via the .config,
* or if gcc is too old:
*/
-#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
!defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-# define inline inline __attribute__((always_inline))
-# define __inline__ __inline__ __attribute__((always_inline))
-# define __inline __inline __attribute__((always_inline))
+#define inline inline __attribute__((always_inline)) notrace
+#define __inline__ __inline__ __attribute__((always_inline)) notrace
+#define __inline __inline __attribute__((always_inline)) notrace
+#else
+/* A lot of inline functions can cause havoc with function tracing */
+#define inline inline notrace
+#define __inline__ __inline__ notrace
+#define __inline __inline notrace
#endif
-#define __deprecated __attribute__((deprecated))
-#ifndef __packed
-# define __packed __attribute__((packed))
-#endif
-#define __weak __attribute__((weak))
+#define __always_inline inline __attribute__((always_inline))
+#define noinline __attribute__((noinline))
+
+#define __deprecated __attribute__((deprecated))
+#define __packed __attribute__((packed))
+#define __weak __attribute__((weak))
+#define __alias(symbol) __attribute__((alias(#symbol)))
/*
- * it doesn't make sense on ARM (currently the only user of __naked) to trace
- * naked functions because then mcount is called without stack and frame pointer
- * being set up and there is no chance to restore the lr register to the value
- * before mcount was called.
+ * it doesn't make sense on ARM (currently the only user of __naked)
+ * to trace naked functions because then mcount is called without
+ * stack and frame pointer being set up and there is no chance to
+ * restore the lr register to the value before mcount was called.
+ *
+ * The asm() bodies of naked functions often depend on standard calling
+ * conventions, therefore they must be noinline and noclone.
+ *
+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
+ * See GCC PR44290.
*/
-#define __naked __attribute__((naked)) notrace
+#define __naked __attribute__((naked)) noinline __noclone notrace
-#define __noreturn __attribute__((noreturn))
+#define __noreturn __attribute__((noreturn))
/*
* From the GCC manual:
@@ -75,19 +114,170 @@
* would be.
* [...]
*/
-#ifndef __pure
-# define __pure __attribute__((pure))
-#endif
-#ifndef __aligned
-# define __aligned(x) __attribute__((aligned(x)))
-#endif
-#define __printf(a,b) __attribute__((format(printf,a,b)))
-#define noinline __attribute__((noinline))
-#define __attribute_const__ __attribute__((__const__))
-#define __maybe_unused __attribute__((unused))
-#define __always_unused __attribute__((unused))
-
-#define __gcc_header(x) #x
-#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
-#define gcc_header(x) _gcc_header(x)
-#include gcc_header(__GNUC__)
+#define __pure __attribute__((pure))
+#define __aligned(x) __attribute__((aligned(x)))
+#define __printf(a, b) __attribute__((format(printf, a, b)))
+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
+#define __attribute_const__ __attribute__((__const__))
+#define __maybe_unused __attribute__((unused))
+#define __always_unused __attribute__((unused))
+
+/* gcc version specific checks */
+
+#if GCC_VERSION < 30200
+# error Sorry, your compiler is too old - please upgrade it.
+#endif
+
+#if GCC_VERSION < 30300
+# define __used __attribute__((__unused__))
+#else
+# define __used __attribute__((__used__))
+#endif
+
+#ifdef CONFIG_GCOV_KERNEL
+# if GCC_VERSION < 30400
+# error "GCOV profiling support for gcc versions below 3.4 not included"
+# endif /* __GNUC_MINOR__ */
+#endif /* CONFIG_GCOV_KERNEL */
+
+#if GCC_VERSION >= 30400
+#define __must_check __attribute__((warn_unused_result))
+#endif
+
+#if GCC_VERSION >= 40000
+
+/* GCC 4.1.[01] miscompiles __weak */
+#ifdef __KERNEL__
+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
+# error Your version of gcc miscompiles the __weak directive
+# endif
+#endif
+
+#define __used __attribute__((__used__))
+#define __compiler_offsetof(a, b) \
+ __builtin_offsetof(a, b)
+
+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#endif
+
+#if GCC_VERSION >= 40300
+/* Mark functions as cold. gcc will assume any path leading to a call
+ * to them will be unlikely. This means a lot of manual unlikely()s
+ * are unnecessary now for any paths leading to the usual suspects
+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
+ * older compilers]
+ *
+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
+ * in the preprocessor, but we can live with this because they're unreleased.
+ * Maketime probing would be overkill here.
+ *
+ * gcc also has a __attribute__((__hot__)) to move hot functions into
+ * a special section, but I don't see any sense in this right now in
+ * the kernel context
+ */
+#define __cold __attribute__((__cold__))
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#ifndef __CHECKER__
+# define __compiletime_warning(message) __attribute__((warning(message)))
+# define __compiletime_error(message) __attribute__((error(message)))
+#endif /* __CHECKER__ */
+#endif /* GCC_VERSION >= 40300 */
+
+#if GCC_VERSION >= 40500
+/*
+ * Mark a position in code as unreachable. This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased. Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone __attribute__((__noclone__))
+
+#endif /* GCC_VERSION >= 40500 */
+
+#if GCC_VERSION >= 40600
+/*
+ * When used with Link Time Optimization, gcc can optimize away C functions or
+ * variables which are referenced only from assembly code. __visible tells the
+ * optimizer that something else uses this function or variable, thus preventing
+ * this.
+ */
+#define __visible __attribute__((externally_visible))
+#endif
+
+
+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
+/*
+ * __assume_aligned(n, k): Tell the optimizer that the returned
+ * pointer can be assumed to be k modulo n. The second argument is
+ * optional (default 0), so we use a variadic macro to make the
+ * shorthand.
+ *
+ * Beware: Do not apply this to functions which may return
+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
+ * returning extra information in the low bits (but in that case the
+ * compiler should see some alignment anyway, when the return value is
+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
+ */
+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
+#endif
+
+/*
+ * GCC 'asm goto' miscompiles certain code sequences:
+ *
+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
+ *
+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
+ *
+ * (asm goto is automatically volatile - the naming reflects this.)
+ */
+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
+
+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
+#if GCC_VERSION >= 40400
+#define __HAVE_BUILTIN_BSWAP32__
+#define __HAVE_BUILTIN_BSWAP64__
+#endif
+#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600)
+#define __HAVE_BUILTIN_BSWAP16__
+#endif
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+
+#if GCC_VERSION >= 50000
+#define KASAN_ABI_VERSION 4
+#elif GCC_VERSION >= 40902
+#define KASAN_ABI_VERSION 3
+#endif
+
+#if GCC_VERSION >= 40902
+/*
+ * Tell the compiler that address safety instrumentation (KASAN)
+ * should not be applied to that function.
+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ */
+#define __no_sanitize_address __attribute__((no_sanitize_address))
+#endif
+
+#endif /* gcc version >= 40000 specific checks */
+
+#if !defined(__noclone)
+#define __noclone /* not needed */
+#endif
+
+#if !defined(__no_sanitize_address)
+#define __no_sanitize_address
+#endif
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h
deleted file mode 100644
index 2befe65..0000000
--- a/include/linux/compiler-gcc3.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __LINUX_COMPILER_H
-#error "Please don't include <linux/compiler-gcc3.h> directly, include <linux/compiler.h> instead."
-#endif
-
-#if __GNUC_MINOR__ >= 3
-# define __used __attribute__((__used__))
-#else
-# define __used __attribute__((__unused__))
-#endif
-
-#if __GNUC_MINOR__ >= 4
-#define __must_check __attribute__((warn_unused_result))
-#endif
-
-/*
- * A trick to suppress uninitialized variable warning without generating any
- * code
- */
-#define uninitialized_var(x) x = x
-
-#define __always_inline inline __attribute__((always_inline))
diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
deleted file mode 100644
index 27d11ca..0000000
--- a/include/linux/compiler-gcc4.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef __LINUX_COMPILER_H
-#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead."
-#endif
-
-/* GCC 4.1.[01] miscompiles __weak */
-#ifdef __KERNEL__
-# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1
-# error Your version of gcc miscompiles the __weak directive
-# endif
-#endif
-
-#define __used __attribute__((__used__))
-#define __must_check __attribute__((warn_unused_result))
-#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
-#ifndef __always_inline
-# define __always_inline inline __attribute__((always_inline))
-#endif
-
-/*
- * A trick to suppress uninitialized variable warning without generating any
- * code
- */
-#define uninitialized_var(x) x = x
-
-#if __GNUC_MINOR__ >= 3
-/* Mark functions as cold. gcc will assume any path leading to a call
- to them will be unlikely. This means a lot of manual unlikely()s
- are unnecessary now for any paths leading to the usual suspects
- like BUG(), printk(), panic() etc. [but let's keep them for now for
- older compilers]
-
- Early snapshots of gcc 4.3 don't support this and we can't detect this
- in the preprocessor, but we can live with this because they're unreleased.
- Maketime probing would be overkill here.
-
- gcc also has a __attribute__((__hot__)) to move hot functions into
- a special section, but I don't see any sense in this right now in
- the kernel context */
-#define __cold __attribute__((__cold__))
-
-
-#if __GNUC_MINOR__ >= 5
-/*
- * Mark a position in code as unreachable. This can be used to
- * suppress control flow warnings after asm blocks that transfer
- * control elsewhere.
- *
- * Early snapshots of gcc 4.5 don't support this and we can't detect
- * this in the preprocessor, but we can live with this because they're
- * unreleased. Really, we need to have autoconf for the kernel.
- */
-#define unreachable() __builtin_unreachable()
-#endif
-
-#endif
-
-#if __GNUC_MINOR__ > 0
-#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-#endif
-#if __GNUC_MINOR__ >= 4
-#define __compiletime_warning(message) __attribute__((warning(message)))
-#define __compiletime_error(message) __attribute__((error(message)))
-#endif
diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h
new file mode 100644
index 0000000..d4c7113
--- /dev/null
+++ b/include/linux/compiler-intel.h
@@ -0,0 +1,45 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-intel.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#ifdef __ECC
+
+/* Some compiler specific definitions are overwritten here
+ * for Intel ECC compiler
+ */
+
+#include <asm/intrinsics.h>
+
+/* Intel ECC compiler doesn't support gcc specific asm stmts.
+ * It uses intrinsics to do the equivalent things.
+ */
+#undef barrier
+#undef barrier_data
+#undef RELOC_HIDE
+#undef OPTIMIZER_HIDE_VAR
+
+#define barrier() __memory_barrier()
+#define barrier_data(ptr) barrier()
+
+#define RELOC_HIDE(ptr, off) \
+ ({ unsigned long __ptr; \
+ __ptr = (unsigned long) (ptr); \
+ (typeof(ptr)) (__ptr + (off)); })
+
+/* This should act as an optimization barrier on var.
+ * Given that this compiler does not have inline assembly, a compiler barrier
+ * is the best we can do.
+ */
+#define OPTIMIZER_HIDE_VAR(var) barrier()
+
+/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */
+#define __must_be_array(a) 0
+
+#endif
+
+#ifndef __HAVE_BUILTIN_BSWAP16__
+/* icc has this, but it's called _bswap16 */
+#define __HAVE_BUILTIN_BSWAP16__
+#define __builtin_bswap16 _bswap16
+#endif
+
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 5be3dab..020ad16 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -5,16 +5,24 @@
#ifdef __CHECKER__
# define __user __attribute__((noderef, address_space(1)))
-# define __kernel /* default address space */
+# define __kernel __attribute__((address_space(0)))
# define __safe __attribute__((safe))
# define __force __attribute__((force))
# define __nocast __attribute__((nocast))
# define __iomem __attribute__((noderef, address_space(2)))
+# define __must_hold(x) __attribute__((context(x,1,1)))
# define __acquires(x) __attribute__((context(x,0,1)))
# define __releases(x) __attribute__((context(x,1,0)))
# define __acquire(x) __context__(x,1)
# define __release(x) __context__(x,-1)
# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0)
+# define __percpu __attribute__((noderef, address_space(3)))
+# define __pmem __attribute__((noderef, address_space(5)))
+#ifdef CONFIG_SPARSE_RCU_POINTER
+# define __rcu __attribute__((noderef, address_space(4)))
+#else
+# define __rcu
+#endif
extern void __chk_user_ptr(const volatile void __user *);
extern void __chk_io_ptr(const volatile void __iomem *);
#else
@@ -27,20 +35,32 @@ extern void __chk_io_ptr(const volatile void __iomem *);
# define __chk_user_ptr(x) (void)0
# define __chk_io_ptr(x) (void)0
# define __builtin_warning(x, y...) (1)
+# define __must_hold(x)
# define __acquires(x)
# define __releases(x)
# define __acquire(x) (void)0
# define __release(x) (void)0
# define __cond_lock(x,c) (c)
+# define __percpu
+# define __rcu
+# define __pmem
#endif
+/* Indirect macros required for expanded argument pasting, eg. __LINE__. */
+#define ___PASTE(a,b) a##b
+#define __PASTE(a,b) ___PASTE(a,b)
+
#ifdef __KERNEL__
#ifdef __GNUC__
#include <linux/compiler-gcc.h>
#endif
+#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__)
+#define notrace __attribute__((hotpatch(0,0)))
+#else
#define notrace __attribute__((no_instrument_function))
+#endif
/* Intel compiler defines __GNUC__. So we will overwrite implementations
* coming from above header files here
@@ -49,6 +69,13 @@ extern void __chk_io_ptr(const volatile void __iomem *);
# include <linux/compiler-intel.h>
#endif
+/* Clang compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __clang__
+#include <linux/compiler-clang.h>
+#endif
+
/*
* Generic compiler-dependent macros required for kernel
* build go below this comment. Actual compiler/compiler version
@@ -117,7 +144,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
*/
#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
#define __trace_if(cond) \
- if (__builtin_constant_p((cond)) ? !!(cond) : \
+ if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
({ \
int ______r; \
static struct ftrace_branch_data \
@@ -144,6 +171,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
# define barrier() __memory_barrier()
#endif
+#ifndef barrier_data
+# define barrier_data(ptr) barrier()
+#endif
+
/* Unreachable code */
#ifndef unreachable
# define unreachable() do { } while (1)
@@ -156,6 +187,135 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
(typeof(ptr)) (__ptr + (off)); })
#endif
+#ifndef OPTIMIZER_HIDE_VAR
+#define OPTIMIZER_HIDE_VAR(var) barrier()
+#endif
+
+/* Not-quite-unique ID. */
+#ifndef __UNIQUE_ID
+# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__)
+#endif
+
+#include <linux/types.h>
+
+#define __READ_ONCE_SIZE \
+({ \
+ switch (size) { \
+ case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \
+ case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \
+ case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \
+ case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \
+ default: \
+ barrier(); \
+ __builtin_memcpy((void *)res, (const void *)p, size); \
+ barrier(); \
+ } \
+})
+
+static __always_inline
+void __read_once_size(const volatile void *p, void *res, int size)
+{
+ __READ_ONCE_SIZE;
+}
+
+#ifdef CONFIG_KASAN
+/*
+ * This function is not 'inline' because __no_sanitize_address confilcts
+ * with inlining. Attempt to inline it may cause a build failure.
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ * '__maybe_unused' allows us to avoid defined-but-not-used warnings.
+ */
+static __no_sanitize_address __maybe_unused
+void __read_once_size_nocheck(const volatile void *p, void *res, int size)
+{
+ __READ_ONCE_SIZE;
+}
+#else
+static __always_inline
+void __read_once_size_nocheck(const volatile void *p, void *res, int size)
+{
+ __READ_ONCE_SIZE;
+}
+#endif
+
+static __always_inline void __write_once_size(volatile void *p, void *res, int size)
+{
+ switch (size) {
+ case 1: *(volatile __u8 *)p = *(__u8 *)res; break;
+ case 2: *(volatile __u16 *)p = *(__u16 *)res; break;
+ case 4: *(volatile __u32 *)p = *(__u32 *)res; break;
+ case 8: *(volatile __u64 *)p = *(__u64 *)res; break;
+ default:
+ barrier();
+ __builtin_memcpy((void *)p, (const void *)res, size);
+ barrier();
+ }
+}
+
+/*
+ * Prevent the compiler from merging or refetching reads or writes. The
+ * compiler is also forbidden from reordering successive instances of
+ * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the
+ * compiler is aware of some particular ordering. One way to make the
+ * compiler aware of ordering is to put the two invocations of READ_ONCE,
+ * WRITE_ONCE or ACCESS_ONCE() in different C statements.
+ *
+ * In contrast to ACCESS_ONCE these two macros will also work on aggregate
+ * data types like structs or unions. If the size of the accessed data
+ * type exceeds the word size of the machine (e.g., 32 bits or 64 bits)
+ * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a
+ * compile-time warning.
+ *
+ * Their two major use cases are: (1) Mediating communication between
+ * process-level code and irq/NMI handlers, all running on the same CPU,
+ * and (2) Ensuring that the compiler does not fold, spindle, or otherwise
+ * mutilate accesses that either do not require ordering or that interact
+ * with an explicit memory barrier or atomic instruction that provides the
+ * required ordering.
+ */
+
+#define __READ_ONCE(x, check) \
+({ \
+ union { typeof(x) __val; char __c[1]; } __u; \
+ if (check) \
+ __read_once_size(&(x), __u.__c, sizeof(x)); \
+ else \
+ __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \
+ __u.__val; \
+})
+#define READ_ONCE(x) __READ_ONCE(x, 1)
+
+/*
+ * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need
+ * to hide memory access from KASAN.
+ */
+#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0)
+
+#define WRITE_ONCE(x, val) \
+({ \
+ union { typeof(x) __val; char __c[1]; } __u = \
+ { .__val = (__force typeof(x)) (val) }; \
+ __write_once_size(&(x), __u.__c, sizeof(x)); \
+ __u.__val; \
+})
+
+/**
+ * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering
+ * @cond: boolean expression to wait for
+ *
+ * Equivalent to using smp_load_acquire() on the condition variable but employs
+ * the control dependency of the wait to reduce the barrier on many platforms.
+ *
+ * The control dependency provides a LOAD->STORE order, the additional RMB
+ * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
+ * aka. ACQUIRE.
+ */
+#define smp_cond_acquire(cond) do { \
+ while (!(cond)) \
+ cpu_relax(); \
+ smp_rmb(); /* ctrl + rmb := acquire */ \
+} while (0)
+
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
@@ -228,7 +388,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
/*
* Rather then using noinline to prevent stack consumption, use
- * noinline_for_stack instead. For documentaiton reasons.
+ * noinline_for_stack instead. For documentation reasons.
*/
#define noinline_for_stack noinline
@@ -270,11 +430,28 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
# define __section(S) __attribute__ ((__section__(#S)))
#endif
+#ifndef __visible
+#define __visible
+#endif
+
+/*
+ * Assume alignment of return value.
+ */
+#ifndef __assume_aligned
+#define __assume_aligned(a, ...)
+#endif
+
+
/* Are two types/vars the same type (ignoring qualifiers)? */
#ifndef __same_type
# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
#endif
+/* Is this type a native word size -- useful for atomic operations */
+#ifndef __native_word
+# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
+#endif
+
/* Compile time object size, -1 for unknown */
#ifndef __compiletime_object_size
# define __compiletime_object_size(obj) -1
@@ -284,7 +461,48 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
#endif
#ifndef __compiletime_error
# define __compiletime_error(message)
+/*
+ * Sparse complains of variable sized arrays due to the temporary variable in
+ * __compiletime_assert. Unfortunately we can't just expand it out to make
+ * sparse see a constant array size without breaking compiletime_assert on old
+ * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.
+ */
+# ifndef __CHECKER__
+# define __compiletime_error_fallback(condition) \
+ do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
+# endif
#endif
+#ifndef __compiletime_error_fallback
+# define __compiletime_error_fallback(condition) do { } while (0)
+#endif
+
+#define __compiletime_assert(condition, msg, prefix, suffix) \
+ do { \
+ bool __cond = !(condition); \
+ extern void prefix ## suffix(void) __compiletime_error(msg); \
+ if (__cond) \
+ prefix ## suffix(); \
+ __compiletime_error_fallback(__cond); \
+ } while (0)
+
+#define _compiletime_assert(condition, msg, prefix, suffix) \
+ __compiletime_assert(condition, msg, prefix, suffix)
+
+/**
+ * compiletime_assert - break build and emit msg if condition is false
+ * @condition: a compile-time constant condition to check
+ * @msg: a message to emit if condition is false
+ *
+ * In tradition of POSIX assert, this macro will break the build if the
+ * supplied condition is *false*, emitting the supplied error message if the
+ * compiler has support to do so.
+ */
+#define compiletime_assert(condition, msg) \
+ _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
+
+#define compiletime_assert_atomic_type(t) \
+ compiletime_assert(__native_word(t), \
+ "Need native word sized stores/loads for atomicity.")
/*
* Prevent the compiler from merging or refetching accesses. The compiler
@@ -293,11 +511,45 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
* to make the compiler aware of ordering is to put the two invocations of
* ACCESS_ONCE() in different C statements.
*
- * This macro does absolutely -nothing- to prevent the CPU from reordering,
- * merging, or refetching absolutely anything at any time. Its main intended
- * use is to mediate communication between process-level code and irq/NMI
- * handlers, all running on the same CPU.
+ * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE
+ * on a union member will work as long as the size of the member matches the
+ * size of the union and the size is smaller than word size.
+ *
+ * The major use cases of ACCESS_ONCE used to be (1) Mediating communication
+ * between process-level code and irq/NMI handlers, all running on the same CPU,
+ * and (2) Ensuring that the compiler does not fold, spindle, or otherwise
+ * mutilate accesses that either do not require ordering or that interact
+ * with an explicit memory barrier or atomic instruction that provides the
+ * required ordering.
+ *
+ * If possible use READ_ONCE()/WRITE_ONCE() instead.
*/
-#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
-
+#define __ACCESS_ONCE(x) ({ \
+ __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \
+ (volatile typeof(x) *)&(x); })
+#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x))
+
+/**
+ * lockless_dereference() - safely load a pointer for later dereference
+ * @p: The pointer to load
+ *
+ * Similar to rcu_dereference(), but for situations where the pointed-to
+ * object's lifetime is managed by something other than RCU. That
+ * "something other" might be reference counting or simple immortality.
+ */
+#define lockless_dereference(p) \
+({ \
+ typeof(p) _________p1 = READ_ONCE(p); \
+ smp_read_barrier_depends(); /* Dependency order vs. p above. */ \
+ (_________p1); \
+})
+
+/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */
+#ifdef CONFIG_KPROBES
+# define __kprobes __attribute__((__section__(".kprobes.text")))
+# define nokprobe_inline __always_inline
+#else
+# define __kprobes
+# define nokprobe_inline inline
+#endif
#endif /* __LINUX_COMPILER_H */
--
2.7.4

142
package/boot/uboot-lantiq/patches/0029-net-Use_packed_structures-for_networking.patch Normal file
View File

@@ -0,0 +1,142 @@
From 704f3acfcf55343043bbed01c5fb0a0094a68e8a Mon Sep 17 00:00:00 2001
From: Denis Pynkin <denis.pynkin@collabora.com>
Date: Fri, 21 Jul 2017 19:28:42 +0300
Subject: [PATCH] net: Use packed structures for networking
PXE boot is broken with GCC 7.1 due option '-fstore-merging' enabled
by default for '-O2':
BOOTP broadcast 1
data abort
pc : [<8ff8bb30>] lr : [<00004f1f>]
reloc pc : [<17832b30>] lr : [<878abf1f>]
sp : 8f558bc0 ip : 00000000 fp : 8ffef5a4
r10: 8ffed248 r9 : 8f558ee0 r8 : 8ffef594
r7 : 0000000e r6 : 8ffed700 r5 : 00000000 r4 : 8ffed74e
r3 : 00060101 r2 : 8ffed230 r1 : 8ffed706 r0 : 00000ddd
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
Core reason is usage of structures for network headers without packed
attribute.
Reviewed-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com>
Signed-off-by: Denis Pynkin <denis.pynkin@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
include/net.h | 14 +++++++-------
net/bootp.h | 2 +-
net/dns.h | 2 +-
net/nfs.h | 2 +-
net/sntp.h | 2 +-
5 files changed, 11 insertions(+), 11 deletions(-)
--- a/include/net.h
+++ b/include/net.h
@@ -203,7 +203,7 @@ struct ethernet_hdr {
uchar et_dest[6]; /* Destination node */
uchar et_src[6]; /* Source node */
ushort et_protlen; /* Protocol or length */
-};
+} __attribute__((packed));
/* Ethernet header size */
#define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr))
@@ -219,7 +219,7 @@ struct e802_hdr {
uchar et_snap2;
uchar et_snap3;
ushort et_prot; /* 802 protocol */
-};
+} __attribute__((packed));
/* 802 + SNAP + ethernet header size */
#define E802_HDR_SIZE (sizeof(struct e802_hdr))
@@ -233,7 +233,7 @@ struct vlan_ethernet_hdr {
ushort vet_vlan_type; /* PROT_VLAN */
ushort vet_tag; /* TAG of VLAN */
ushort vet_type; /* protocol type */
-};
+} __attribute__((packed));
/* VLAN Ethernet header size */
#define VLAN_ETHER_HDR_SIZE (sizeof(struct vlan_ethernet_hdr))
@@ -260,7 +260,7 @@ struct ip_hdr {
ushort ip_sum; /* checksum */
IPaddr_t ip_src; /* Source IP address */
IPaddr_t ip_dst; /* Destination IP address */
-};
+} __attribute__((packed));
#define IP_OFFS 0x1fff /* ip offset *= 8 */
#define IP_FLAGS 0xe000 /* first 3 bits */
@@ -288,7 +288,7 @@ struct ip_udp_hdr {
ushort udp_dst; /* UDP destination port */
ushort udp_len; /* Length of UDP packet */
ushort udp_xsum; /* Checksum */
-};
+} __attribute__((packed));
#define IP_UDP_HDR_SIZE (sizeof(struct ip_udp_hdr))
#define UDP_HDR_SIZE (IP_UDP_HDR_SIZE - IP_HDR_SIZE)
@@ -327,7 +327,7 @@ struct arp_hdr {
uchar ar_tha[]; /* Target hardware address */
uchar ar_tpa[]; /* Target protocol address */
#endif /* 0 */
-};
+} __attribute__((packed));
#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */
@@ -362,7 +362,7 @@ struct icmp_hdr {
} frag;
uchar data[0];
} un;
-};
+} __attribute__((packed));
#define ICMP_HDR_SIZE (sizeof(struct icmp_hdr))
#define IP_ICMP_HDR_SIZE (IP_HDR_SIZE + ICMP_HDR_SIZE)
--- a/net/bootp.h
+++ b/net/bootp.h
@@ -49,7 +49,7 @@ struct Bootp_t {
char bp_sname[64]; /* Server host name */
char bp_file[128]; /* Boot file name */
char bp_vend[OPT_FIELD_SIZE]; /* Vendor information */
-};
+} __attribute__((packed));
#define BOOTP_HDR_SIZE sizeof(struct Bootp_t)
--- a/net/dns.h
+++ b/net/dns.h
@@ -29,7 +29,7 @@ struct header {
uint16_t nauth; /* Authority PRs */
uint16_t nother; /* Other PRs */
unsigned char data[1]; /* Data, variable length */
-};
+} __attribute__((packed));
extern void DnsStart(void); /* Begin DNS */
--- a/net/sntp.h
+++ b/net/sntp.h
@@ -51,7 +51,7 @@ struct sntp_pkt_t {
unsigned long long originate_timestamp;
unsigned long long receive_timestamp;
unsigned long long transmit_timestamp;
-};
+} __attribute__((packed));
extern void SntpStart(void); /* Begin SNTP */
--- a/net/nfs.h
+++ b/net/nfs.h
@@ -68,7 +68,7 @@ struct rpc_t {
uint32_t data[19];
} reply;
} u;
-};
+} __attribute__((packed));
extern void NfsStart(void); /* Begin NFS */

306
package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch Normal file
View File

@@ -0,0 +1,306 @@
--- /dev/null
+++ b/board/lantiq/easy50712/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy50712/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy50712/ddr_settings.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x13c
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0xd00
+#define MC_DC22_VALUE 0xd0d
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x62
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/lantiq/easy50712/easy50712.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* SPI/CS output (low-active) for serial flash */
+ gpio_direction_output(22, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+
+ /* enable CLK_OUT2 for external switch */
+ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate HRST line to release reset of ADM6996I switch */
+ ltq_reset_once(LTQ_RESET_HARD, 200000);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ switch (cs) {
+ case 2:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,6 +502,9 @@ Active mips mips32 au1x0
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
--- /dev/null
+++ b/include/configs/easy50712.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY50712"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 2
+#define CONFIG_ENV_SPI_MAX_HZ 20000000
+#define CONFIG_ENV_SPI_MODE 0
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (128 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR
+
+#endif /* __CONFIG_H */

379
package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch Normal file
View File

@@ -0,0 +1,379 @@
--- /dev/null
+++ b/board/lantiq/easy80920/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy80920/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy80920/ddr_settings.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141b42
+#define MC_CCR42_VALUE 0x141b42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/lantiq/easy80920/easy80920.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* SPI CS 0.4 to serial flash */
+ gpio_direction_output(10, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ if (cs == 4)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -509,6 +509,11 @@ Active mips mips32 incai
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
--- /dev/null
+++ b/include/configs/easy80920.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY80920"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 4
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
+#define CONFIG_SPL_SPI_MODE 0
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
+#define CONFIG_SYS_NAND_PAGE_COUNT 128
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+#define CONFIG_SYS_DRAM_PROBE
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_SFSPL)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ CONFIG_ENV_UPDATE_UBOOT_SF \
+ CONFIG_ENV_UPDATE_UBOOT_NAND
+
+#endif /* __CONFIG_H */

244
package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch Normal file
View File

@@ -0,0 +1,244 @@
From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: MIPS: add board support for Arcadyan ARV4519
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv4519pw/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv4519pw/arv4519pw.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv4519pw/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv4519pw/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x131
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5A
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,6 +502,9 @@ Active mips mips32 au1x0
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/arv4519pw.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV4519PW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV4519PW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Brnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

244
package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch Normal file
View File

@@ -0,0 +1,244 @@
From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: MIPS: add board support for Arcadyan ARV7518
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv7518pw/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv7518pw/arv7518pw.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv7518pw/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv7518pw/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -505,6 +505,9 @@ Active mips mips32 au1x0
Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/arv7518pw.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV7518PW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV7518PW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Brnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

250
package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch Normal file
View File

@@ -0,0 +1,250 @@
From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel.golle@gmail.com>
Date: Fri, 8 Mar 2013 13:29:04 +0200
Subject: MIPS: add board support for AudioCodes MP-252
Signed-off-by: Daniel Golle <dgolle@allnet.de>
--- /dev/null
+++ b/board/audiocodes/acmp252/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/audiocodes/acmp252/acmp252.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com>
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* Activate reset line of ADM6996I switch */
+ gpio_direction_output(19, 0);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate reset line of ADM6996I switch */
+ gpio_set_value(19, 1);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
--- /dev/null
+++ b/board/audiocodes/acmp252/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/audiocodes/acmp252/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x403
+#define MC_DC08_VALUE 0x103
+#define MC_DC09_VALUE 0x80B
+#define MC_DC10_VALUE 0x304
+#define MC_DC11_VALUE 0xD03
+#define MC_DC12_VALUE 0x2C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x13C
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x402
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5C
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2D93
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -508,6 +508,8 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
+Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/acmp252.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com>
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ACMP252"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "AudioCodes MP-252"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

356
package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch Normal file
View File

@@ -0,0 +1,356 @@
From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: MIPS: add board support for AVM FritzBox 3370
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/avm/fb3370/Makefile
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/avm/fb3370/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/avm/fb3370/ddr_settings.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141B42
+#define MC_CCR42_VALUE 0x141B42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/avm/fb3370/fb3370.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* SPI CS 0.4 to serial flash */
+ gpio_direction_output(10, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ if (cs == 4)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -517,6 +517,9 @@ Active mips mips32 incai
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/fb3370.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "FB3370"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "AVM FritzBox 3370"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
+
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 4
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
+#define CONFIG_SPL_SPI_MODE 0
+
+#define CONFIG_SYS_DRAM_PROBE
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
+
+#if defined(CONFIG_SYS_BOOT_SFSPL)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#if defined(CONFIG_SYS_BOOT_EVA)
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_SF
+
+#endif /* __CONFIG_H */

249
package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch Normal file
View File

@@ -0,0 +1,249 @@
From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: MIPS: add board support for Gigaset SX76X
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/gigaset/sx76x/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/gigaset/sx76x/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/gigaset/sx76x/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x202
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xF3E
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0xF00
+#define MC_DC22_VALUE 0xF0F
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x63
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x100
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x514
+#define MC_DC29_VALUE 0x2D89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x2002
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/gigaset/sx76x/sx76x.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* Activate reset line of ADM6996I switch */
+ gpio_direction_output(19, 0);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate reset line of ADM6996I switch */
+ gpio_set_value(19, 1);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -510,6 +510,8 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
+Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube gigaset sx76x gigasx76x_ram sx76x:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/sx76x.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "GIGASX76X"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Gigaset sx76x"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

303
package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch Normal file
View File

@@ -0,0 +1,303 @@
From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001
From: Luka Perkov <luka@openwrt.org>
Date: Tue, 6 Aug 2013 22:51:00 +0200
Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx
Signed-off-by: Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/board/zyxel/p2812hnufx/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/zyxel/p2812hnufx/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/zyxel/p2812hnufx/ddr_settings.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * The values have been extracted from original ZyXEL U-Boot.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141B42
+#define MC_CCR42_VALUE 0x141B42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/zyxel/p2812hnufx/p2812hnufx.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -527,6 +527,8 @@ Active mips mips32 vrx20
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
--- /dev/null
+++ b/include/configs/p2812hnufx.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "P-2812HNU-Fx"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */
+
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
+
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
+
+#define CONFIG_SYS_DRAM_PROBE
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NAND
+
+#endif /* __CONFIG_H */

244
package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch Normal file
View File

@@ -0,0 +1,244 @@
From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001
From: Oliver Muth <dr.o.muth@gmx.de>
Date: Sat, 12 Oct 2013 16:49:53 +0200
Subject: MIPS: add board support for Arcadyan ARV752DPW
Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv752dpw/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv752dpw/arv752dpw.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Realtek rtl8306 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+static struct switch_device rtl8306_dev = {
+ .name = "rtl8306",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&rtl8306_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv752dpw/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv752dpw/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -508,6 +508,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN -
+Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR -
+Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM -
Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv752dpw.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV752DPW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_RTL8306
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Brnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

246
package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch Normal file
View File

@@ -0,0 +1,246 @@
From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001
From: Oliver Muth <dr.o.muth@gmx.de>
Date: Sat, 12 Oct 2013 16:49:53 +0200
Subject: MIPS: add board support for Arcadyan ARV752DPW22
Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv752dpw22/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv752dpw22/arv752dpw22.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv752dpw22/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv752dpw22/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -511,6 +511,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN -
Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR -
Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM -
+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN -
+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR -
+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM -
Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv752dpw22.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV752DPW22"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW22"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Burnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

271
package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch Normal file
View File

@@ -0,0 +1,271 @@
From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001
From: Matti Laakso <malaakso@elisanet.fi>
Date: Sat, 2 Mar 2013 23:34:00 +0100
Subject: MIPS: add board support for Arcadyan ARV7510
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/board/arcadyan/arv7510pw/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv7510pw/arv7510pw.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+
+static void gpio_init(void)
+{
+ /* Initialize SSIO GPIOs */
+ gpio_set_altfunc(4, 1, 0, 1);
+ gpio_set_altfunc(5, 1, 0, 1);
+ gpio_set_altfunc(6, 1, 0, 1);
+ ltq_gpio_init();
+
+ /* Power led on */
+ gpio_direction_output(76, 1);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: ADM6996I */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate HRST line to release reset of ADM6996I switch */
+ ltq_reset_once(LTQ_RESET_HARD, 200000);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv7510pw/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv7510pw/ddr_settings.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x120
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x52
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -505,6 +505,9 @@ Active mips mips32 au1x0
Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv7510pw.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV7510PW"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* SSIO */
+#define CONFIG_LTQ_SSIO_SHIFT_REGS
+#define CONFIG_LTQ_SSIO_EDGE_FALLING
+#define CONFIG_LTQ_SSIO_GPHY1_MODE 0
+#define CONFIG_LTQ_SSIO_GPHY2_MODE 0
+#define CONFIG_LTQ_SSIO_INIT_VALUE 0
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Brnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Buffered write broken in ARV7510PW */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0060000\0"
+
+#endif /* __CONFIG_H */

240
package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch Normal file
View File

@@ -0,0 +1,240 @@
--- /dev/null
+++ b/board/arcadyan/arv7510pw22/arv7510pw22.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ /* Switch on Power LED */
+ gpio_direction_output(2, 0);
+ gpio_set_value(2, 0);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv7510pw22/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv7510pw22/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/arcadyan/arv7510pw22/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/boards.cfg
+++ b/boards.cfg
@@ -508,6 +508,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_brn arv7510pw22:SYS_BOOT_BRN Álvaro Fernández Rojas <noltari@gmail.com>
+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_nor arv7510pw22:SYS_BOOT_NOR Álvaro Fernández Rojas <noltari@gmail.com>
+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_ram arv7510pw22:SYS_BOOT_RAM Álvaro Fernández Rojas <noltari@gmail.com>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv7510pw22.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV7510PW22"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW22"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Burnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0060000\0"
+
+#endif /* __CONFIG_H */

307
package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch Normal file
View File

@@ -0,0 +1,307 @@
--- /dev/null
+++ b/board/arcadyan/vgv7510kw22/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+#define GPIO_POWER_GREEN 14
+#define GPIO_POWER_RED 28
+
+static void gpio_init(void)
+{
+ /* Turn on the green power LED */
+ gpio_direction_output(GPIO_POWER_GREEN, 0);
+
+ /* Turn off the red power LED */
+ gpio_direction_output(GPIO_POWER_RED, 1);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+void show_boot_progress(int arg)
+{
+ if (!do_gpio_init)
+ return 0;
+
+ if (arg >= 0) {
+ /* Success - turn off the red power LED and turn on the green power LED */
+ gpio_set_value(GPIO_POWER_RED, 1);
+ gpio_set_value(GPIO_POWER_GREEN, 0);
+ } else {
+ /* Failure - turn off green power LED and turn on red power LED */
+ gpio_set_value(GPIO_POWER_GREEN, 1);
+ gpio_set_value(GPIO_POWER_RED, 0);
+ }
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* unused */
+ { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* unused */
+ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* Internal GPHY0 with 10/100 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
+ /* Internal GPHY0 with 10/100 firmware for LAN port 1 */
+ { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
+ /* Internal GPHY1 with 10/100 firmware for LAN port 4 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
+ /* Internal GPHY1 with 10/100 firmware for LAN port 3 */
+ { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ if (ltq_chip_version_get() == 1)
+ ltq_gphy_phy22f_a1x_load(fw_addr);
+ else
+ ltq_gphy_phy22f_a2x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
--- /dev/null
+++ b/board/arcadyan/vgv7510kw22/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/vgv7510kw22/ddr_settings.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
+ *
+ * The values have been extracted from original brnboot.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x100
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000401
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x2040F
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141B42
+#define MC_CCR42_VALUE 0x141B42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x2040F
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- a/boards.cfg
+++ b/boards.cfg
@@ -531,6 +531,9 @@ Active mips mips32 incai
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/vgv7510kw22.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "VGV7510KW22"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ "kernel_addr=0xB0080000\0"
+
+#endif /* __CONFIG_H */

241
package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch Normal file
View File

@@ -0,0 +1,241 @@
--- /dev/null
+++ b/board/arcadyan/arv8539pw22/Makefile
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
--- /dev/null
+++ b/board/arcadyan/arv8539pw22/arv8539pw22.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Atheros ar8216 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device ar8216_dev = {
+ .name = "ar8216",
+ .cpu_port = 0,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&ar8216_dev);
+}
+
--- /dev/null
+++ b/board/arcadyan/arv8539pw22/config.mk
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+
--- /dev/null
+++ b/board/arcadyan/arv8539pw22/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x134
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5B
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -520,6 +520,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN -
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR -
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM -
+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_brn arv8539pw22:SYS_BOOT_BRN -
+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_nor arv8539pw22:SYS_BOOT_NOR -
+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_ram arv8539pw22:SYS_BOOT_RAM -
Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv8539pw22.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV8539PW22"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Speedport W 504V Typ A"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_AR8216
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Burnboot loadable image */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_OVERWRITE 1
+#endif
+
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyS1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */

290
package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch Normal file
View File

@@ -0,0 +1,290 @@
--- /dev/null
+++ b/board/arcadyan/vgv7519/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/vgv7519/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/vgv7519/ddr_settings.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
+ *
+ * The values have been extracted from original brnboot.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x100
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000401
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x2040F
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141B42
+#define MC_CCR42_VALUE 0x141B42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x2040F
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/arcadyan/vgv7519/vgv7519.c
@@ -0,0 +1,95 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+#define GPIO_GPHY_RESET 47
+
+static void gpio_init(void)
+{
+ /* Disable reset on external eth PHY */
+ gpio_direction_output(GPIO_GPHY_RESET, 1);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ if (ltq_chip_version_get() == 1)
+ ltq_gphy_phy22f_a1x_load(fw_addr);
+ else
+ ltq_gphy_phy22f_a2x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -537,6 +537,9 @@ Active mips mips32 incai
Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_brn vgv7519:SYS_BOOT_BRN Mathias Kresin <dev@kresin.me>
+Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_nor vgv7519:SYS_BOOT_NOR Eddi De Pieri <eddi@depieri.net>
+Active mips mips32 vrx200 arcadyan vgv7519 vgv7519_ram vgv7519:SYS_BOOT_RAM Eddi De Pieri <eddi@depieri.net>
Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/vgv7519.h
@@ -0,0 +1,64 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "VGV7519"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan VGV7519"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE }
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ "kernel_addr=0xB0080000\0"
+
+#endif /* __CONFIG_H */

277
package/boot/uboot-lantiq/patches/0115-MIPS-add-board-support-for-Arcadyan-ARV7506PW11.patch Normal file
View File

@@ -0,0 +1,277 @@
--- /dev/null
+++ b/board/arcadyan/arv7506pw11/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/arcadyan/arv7506pw11/arv7506pw11.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+#if defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#else
+#define do_gpio_init 0
+#endif
+
+#define GPIO_POWER_GREEN 3
+#define GPIO_POWER_RED 6
+#define GPIO_GPHY_RESET 19
+
+static void gpio_init(void)
+{
+ /* Reset switch to have him in a clean state on reboot */
+ gpio_direction_output(GPIO_GPHY_RESET, 0);
+ udelay(20);
+ gpio_direction_output(GPIO_GPHY_RESET, 1);
+
+ /* Turn on the green power LED */
+ gpio_direction_output(GPIO_POWER_GREEN, 0);
+
+ /* Turn off the red power LED */
+ gpio_direction_output(GPIO_POWER_RED, 1);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+void show_boot_progress(int arg)
+{
+ if (!do_gpio_init)
+ return 0;
+
+ if (arg >= 0) {
+ /* Success - turn off the red power LED and turn on the green power LED */
+ gpio_set_value(GPIO_POWER_RED, 1);
+ gpio_set_value(GPIO_POWER_GREEN, 0);
+ } else {
+ /* Failure - turn off green power LED and turn on red power LED */
+ gpio_set_value(GPIO_POWER_GREEN, 1);
+ gpio_set_value(GPIO_POWER_RED, 0);
+ }
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Realtek rtl8306 switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+static struct switch_device rtl8306_dev = {
+ .name = "rtl8306",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ return switch_device_register(&rtl8306_dev);
+}
--- /dev/null
+++ b/board/arcadyan/arv7506pw11/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/arcadyan/arv7506pw11/ddr_settings.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
+ *
+ * This file has been generated with lantiq_ram_extract_magic.awk script.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70A
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xC02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x142
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xD
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03
+#define MC_DC21_VALUE 0x1300
+#define MC_DC22_VALUE 0x1313
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x68
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4E20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -505,6 +505,9 @@ Active mips mips32 au1x0
Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
+Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_brn arv7506pw11:SYS_BOOT_BRN Mathias Kresin <dev@kresin.me>
+Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_nor arv7506pw11:SYS_BOOT_NOR Mathias Kresin <dev@kresin.me>
+Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_ram arv7506pw11:SYS_BOOT_RAM Mathias Kresin <dev@kresin.me>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
--- /dev/null
+++ b/include/configs/arv7506pw11.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "ARV7506PW11"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Arcadyan ARV7506PW11"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_RTL8306
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_BRN)
+#define CONFIG_SYS_TEXT_BASE 0x80002000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DISABLE_CACHE
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (64 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ "kernel_addr=0xB0050000\0"
+
+#endif /* __CONFIG_H */

344
package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch Normal file
View File

@@ -0,0 +1,344 @@
--- /dev/null
+++ b/board/bt/bthomehubv5a/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/bt/bthomehubv5a/bthomehubv5a.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Based on p2812hnufx.c: (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+#define GPIO_POWER_GREEN 14
+#define GPIO_POWER_RED 12
+
+static void gpio_init(void)
+{
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+
+ /* Turn on the green power LED */
+ gpio_direction_output(GPIO_POWER_GREEN, 0);
+
+ /* Turn off the red power LED */
+ gpio_direction_output(GPIO_POWER_RED, 1);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+void show_boot_progress(int arg)
+{
+ if (!do_gpio_init)
+ return 0;
+
+ if (arg >= 0) {
+ /* Success - turn off the red power LED and turn on the green power LED */
+ gpio_set_value(GPIO_POWER_RED, 1);
+ gpio_set_value(GPIO_POWER_GREEN, 0);
+ } else {
+ /* Failure - turn off green power LED and turn on red power LED */
+ gpio_set_value(GPIO_POWER_GREEN, 1);
+ gpio_set_value(GPIO_POWER_RED, 0);
+ }
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 3 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 4 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 1 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FE0000;
+
+ ltq_gphy_phy11g_a2x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
--- /dev/null
+++ b/board/bt/bthomehubv5a/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/bt/bthomehubv5a/ddr_settings.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * The values have been taken from the HH5A GPL source.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000101
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000401
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141b42
+#define MC_CCR42_VALUE 0x141b42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- a/boards.cfg
+++ b/boards.cfg
@@ -546,6 +546,8 @@ Active mips mips32 vrx20
Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 bt bthomehubv5a bthomehubv5a_nandspl bthomehubv5a:SYS_BOOT_NANDSPL Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Active mips mips32 vrx200 bt bthomehubv5a bthomehubv5a_ram bthomehubv5a:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- /dev/null
+++ b/include/configs/bthomehubv5a.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2016 Mathias Kresin <openwrt@kresin.me>
+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Based on p2812hnufx.h: (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "BTHOMEHUBV5A"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "BT Home Hub 5A"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a ML01G100BHI00 NAND flash */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
+#define CONFIG_LTQ_SPL_MC_TUNE
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
+
+/* MTD devices */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT "nand0=nand-xway"
+#define MTDPARTS_DEFAULT "mtdparts=nand-xway:0x07e80000@0x100000(UBI)"
+
+/* UBI */
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/* Environment */
+#if defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_SPL_TPL_OFFS 0x800
+#define CONFIG_SPL_TPL_SIZE 0x5000
+#define CONFIG_SPL_MC_TUNE_OFFS 0x5800
+#define CONFIG_SPL_U_BOOT_OFFS 0x6000
+#define CONFIG_SPL_U_BOOT_SIZE 0x3a000
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (640 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "mtdparts default; ubi part UBI; ubi read ${loadaddr} kernel; bootm ${loadaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS
+
+#endif /* __CONFIG_H */

18
package/boot/uboot-lantiq/patches/100-portability.patch Normal file
View File

@@ -0,0 +1,18 @@
--- a/include/image.h
+++ b/include/image.h
@@ -17,7 +17,6 @@
#define __IMAGE_H__
#include "compiler.h"
-#include <asm/byteorder.h>
/* Define this to avoid #ifdefs later on */
struct lmb;
@@ -36,6 +35,7 @@ struct lmb;
#include <lmb.h>
#include <asm/u-boot.h>
+#include <asm/byteorder.h>
#include <command.h>
/* Take notice of the 'ignore' property for hashes */