domenico/openwrt-18.06
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit

Browse Source
This commit is contained in:
domenico
2025-06-24 15:51:28 +02:00
commit 22031d9dab
6862 changed files with 1462554 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

260
package/boot/uboot-sunxi/Makefile Normal file
View File

@@ -0,0 +1,260 @@
#
# Copyright (C) 2013-2016 OpenWrt.org
# Copyright (C) 2017 Yousong Zhou
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2017.11
PKG_HASH:=6a018fd3caf58f3dcfa23ee989a82bd35df03af71872b9dca8c6d758a0d26c05
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=sunxi
UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin
UENV:=default
HIDDEN:=1
endef
define U-Boot/A10-OLinuXino-Lime
BUILD_SUBTARGET:=cortexa8
NAME:=A10 OLinuXino LIME
BUILD_DEVICES:=sun4i-a10-olinuxino-lime
endef
define U-Boot/A13-OLinuXino
BUILD_SUBTARGET:=cortexa8
NAME:=A13 OlinuXino
BUILD_DEVICES:=sun5i-a13-olinuxino
endef
define U-Boot/A20-OLinuXino-Lime
BUILD_SUBTARGET:=cortexa7
NAME:=A20 OLinuXino LIME
BUILD_DEVICES:=sun7i-a20-olinuxino-lime
endef
define U-Boot/A20-OLinuXino-Lime2
BUILD_SUBTARGET:=cortexa7
NAME:=A20 OLinuXino LIME2
BUILD_DEVICES:=sun7i-a20-olinuxino-lime2
endef
define U-Boot/A20-OLinuXino-Lime2-eMMC
BUILD_SUBTARGET:=cortexa7
NAME:=A20 OLinuXino LIME2 eMMC
BUILD_DEVICES:=sun7i-a20-olinuxino-lime2-emmc
endef
define U-Boot/A20-OLinuXino_MICRO
BUILD_SUBTARGET:=cortexa7
NAME:=A20 OLinuXino MICRO
BUILD_DEVICES:=sun7i-a20-olinuxino-micro
endef
define U-Boot/Bananapi
BUILD_SUBTARGET:=cortexa7
NAME:=Bananapi
BUILD_DEVICES:=sun7i-a20-bananapi
endef
define U-Boot/Bananapro
BUILD_SUBTARGET:=cortexa7
NAME:=Bananapro
BUILD_DEVICES:=sun7i-a20-bananapro
endef
define U-Boot/Cubieboard
BUILD_SUBTARGET:=cortexa8
NAME:=Cubieboard
BUILD_DEVICES:=sun4i-a10-cubieboard
endef
define U-Boot/Cubieboard2
BUILD_SUBTARGET:=cortexa7
NAME:=Cubieboard2
BUILD_DEVICES:=sun7i-a20-cubieboard2
endef
define U-Boot/Cubietruck
BUILD_SUBTARGET:=cortexa7
NAME:=Cubietruck
BUILD_DEVICES:=sun7i-a20-cubietruck
endef
define U-Boot/Hummingbird_A31
BUILD_SUBTARGET:=cortexa7
NAME:=Hummingbird A31 board
endef
define U-Boot/Marsboard_A10
BUILD_SUBTARGET:=cortexa8
NAME:=Marsboard
BUILD_DEVICES:=sun4i-a10-marsboard
endef
define U-Boot/Mele_M9
BUILD_SUBTARGET:=cortexa7
NAME:=Mele M9 (A31)
BUILD_DEVICES:=sun6i-a31-m9
endef
define U-Boot/OLIMEX_A13_SOM
BUILD_SUBTARGET:=cortexa8
NAME:=Olimex A13 SOM
BUILD_DEVICES:=sun5i-a13-olimex-som
endef
define U-Boot/Linksprite_pcDuino
BUILD_SUBTARGET:=cortexa8
NAME:=Linksprite pcDuino
BUILD_DEVICES:=sun4i-a10-pcduino
endef
define U-Boot/Linksprite_pcDuino3
BUILD_SUBTARGET:=cortexa7
NAME:=Linksprite pcDuino3
BUILD_DEVICES:=sun7i-a20-pcduino3
endef
define U-Boot/Lamobo_R1
BUILD_SUBTARGET:=cortexa7
NAME:=Lamobo R1
BUILD_DEVICES:=sun7i-a20-lamobo-r1
endef
define U-Boot/nanopi_m1_plus
BUILD_SUBTARGET:=cortexa7
NAME:=NanoPi M1 Plus (H3)
BUILD_DEVICES:=sun8i-h3-nanopi-m1-plus
endef
define U-Boot/nanopi_neo
BUILD_SUBTARGET:=cortexa7
NAME:=U-Boot for NanoPi NEO (H3)
BUILD_DEVICES:=sun8i-h3-nanopi-neo
endef
define U-Boot/orangepi_r1
BUILD_SUBTARGET:=cortexa7
NAME:=Orange Pi R1 (H2+)
BUILD_DEVICES:=sun8i-h2-plus-orangepi-r1
endef
define U-Boot/orangepi_pc
BUILD_SUBTARGET:=cortexa7
NAME:=Orange Pi PC (H3)
BUILD_DEVICES:=sun8i-h3-orangepi-pc
endef
define U-Boot/orangepi_plus
BUILD_SUBTARGET:=cortexa7
NAME:=Orange Pi Plus (H3)
BUILD_DEVICES:=sun8i-h3-orangepi-plus
endef
define U-Boot/orangepi_2
BUILD_SUBTARGET:=cortexa7
NAME:=Orange Pi 2 (H3)
BUILD_DEVICES:=sun8i-h3-orangepi-2
endef
define U-Boot/pangolin
BUILD_SUBTARGET:=cortexa7
NAME:=Theobroma A31-yQ7 devboard
UENV:=pangolin
endef
define U-Boot/nanopi_neo_plus2
BUILD_SUBTARGET:=cortexa53
NAME:=NanoPi NEO Plus2 (H5)
BUILD_DEVICES:=sun50i-h5-nanopi-neo-plus2
DEPENDS:=+PACKAGE_u-boot-nanopi_neo_plus2:arm-trusted-firmware-sunxi
UENV:=a64
endef
define U-Boot/pine64_plus
BUILD_SUBTARGET:=cortexa53
NAME:=Pine64 Plus A64
BUILD_DEVICES:=sun50i-a64-pine64-plus
DEPENDS:=+PACKAGE_u-boot-pine64_plus:arm-trusted-firmware-sunxi
UENV:=a64
endef
define U-Boot/sopine_baseboard
BUILD_SUBTARGET:=cortexa53
NAME:=Sopine Baseboard
BUILD_DEVICES:=sun50i-a64-sopine-baseboard
DEPENDS:=+PACKAGE_u-boot-sopine_baseboard:arm-trusted-firmware-sunxi
UENV:=a64
endef
define U-Boot/orangepi_zero_plus
BUILD_SUBTARGET:=cortexa53
NAME:=Xunlong Orange Pi Zero Plus
BUILD_DEVICES:=sun50i-h5-orangepi-zero-plus
DEPENDS:=+PACKAGE_u-boot-orangepi_zero_plus:arm-trusted-firmware-sunxi
UENV:=a64
endef
UBOOT_TARGETS := \
A10-OLinuXino-Lime \
A13-OLinuXino \
A20-OLinuXino-Lime \
A20-OLinuXino-Lime2 \
A20-OLinuXino-Lime2-eMMC \
A20-OLinuXino_MICRO \
Bananapi \
Bananapro \
Cubieboard \
Cubieboard2 \
Cubietruck \
Hummingbird_A31 \
Marsboard_A10 \
Mele_M9 \
OLIMEX_A13_SOM \
Linksprite_pcDuino \
Linksprite_pcDuino3 \
Lamobo_R1 \
nanopi_m1_plus \
nanopi_neo \
nanopi_neo_plus2 \
orangepi_r1 \
orangepi_pc \
orangepi_plus \
orangepi_2 \
pangolin \
pine64_plus \
sopine_baseboard \
orangepi_zero_plus
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/bl31.bin
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
ifeq ($(SUBTARGET),cortexa53)
cat $(PKG_BUILD_DIR)/spl/sunxi-spl.bin $(PKG_BUILD_DIR)/u-boot.itb > $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot-with-spl.bin
else
$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot-with-spl.bin
endif
mkimage -C none -A arm -T script -d uEnv-$(UENV).txt \
$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
endef
define Package/u-boot/install/default
endef
$(eval $(call BuildPackage/U-Boot))

20
package/boot/uboot-sunxi/patches/002-add-olimex-a13-som.patch Normal file
View File

@@ -0,0 +1,20 @@
--- /dev/null
+++ b/configs/OLIMEX_A13_SOM_defconfig
@@ -0,0 +1,17 @@
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SYS_NS16550=y
+CONFIG_SUNXI_NO_PMIC=y
+CONFIG_USB_EHCI_HCD=y

377
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch Normal file
View File

@@ -0,0 +1,377 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -261,6 +261,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31-pangolin.dtb \
sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-inet-q972.dtb \
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -679,6 +679,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PB5", "PB6";
+ allwinner,function = "i2c3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--- /dev/null
+++ b/arch/arm/dts/sun6i-a31-pangolin.dts
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Theobroma Systems A31 Pangolin";
+ compatible = "tsd,a31-pangolin", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ snps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,m25p40";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ /* external pull-ups missing for some pins */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_pangolin: mmc0_cd_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ leds_pins_pangolin: led_pins@0 {
+ allwinner,pins = "PH7", "PC16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11",
+ "PC12","PC13","PC14","PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp221: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ dcdc1-supply = <&vcc_3v0>;
+ dcdc5-supply = <&vcc_dram>;
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ vcc_3v0: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ vdd_gpu: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ vdd_sys_dll: dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys-dll";
+ };
+
+ vcc_dram: dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+ };
+
+ vcc_wifi: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+
+ avcc: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PD23";
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+};
--- /dev/null
+++ b/configs/pangolin_defconfig
@@ -0,0 +1,36 @@
+CONFIG_SUNXI_PANGOLIN=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-pangolin"
+CONFIG_VIDEO_VGA_VIA_LCD=y
+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CHANNELS=1
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=70
+CONFIG_AXP_DCDC1_VOLT=3300
+CONFIG_AXP_ALDO1_VOLT=0
+CONFIG_AXP_ALDO2_VOLT=1800
+CONFIG_AXP_ALDO3_VOLT=3000
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_AXP_ELDO1_VOLT=1200
+CONFIG_AXP_ELDO2_VOLT=2500
+CONFIG_AXP_ELDO3_VOLT=3300
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_CONS_INDEX=3
+# Vbus gpio for usb1
+CONFIG_USB1_VBUS_PIN=""
+# No Vbus gpio for usb2
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_IMLS=n
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SUNXI_SPI=y
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -752,6 +752,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+choice
+ prompt "Sunxi Board Variant"
+ optional
+
+config SUNXI_PANGOLIN
+ bool "Theobroma A31 uQ7 Board"
+
+endchoice
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig

12
package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch Normal file
View File

@@ -0,0 +1,12 @@
GNU nano 2.7.4 File: 062-A20-improve-gmac-upload.patch
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -24,6 +24,7 @@ CONFIG_DFU_RAM=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_SUN7I_GMAC=y
+CONFIG_GMAC_TX_DELAY=1
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_SCSI=y

32
package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch Normal file
View File

@@ -0,0 +1,32 @@
From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 6 Jan 2015 15:47:18 +0100
Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
This change syncs up the multipliers and dividers used to initialize
PLL1 (i.e. the fast clock driving the ARM cores) with the values used
in Allwinner's Boot1 on sun6i.
More specifically, the following settings are now used:
* up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
* up to 1152MHz: mul=3, div=2 (unchanged)
* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -113,11 +113,12 @@ void clock_set_pll1(unsigned int clk)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;
- int k = 1;
- int m = 1;
+ int k = 2;
+ int m = 2;
if (clk > 1152000000) {
- k = 2;
+ k = 4;
+ m = 2;
} else if (clk > 768000000) {
k = 3;
m = 2;

69
package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch Normal file
View File

@@ -0,0 +1,69 @@
From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 6 Jan 2015 21:26:44 +0100
Subject: sun6i: Fix and document PLL LDO voltage selection
The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
their meaning reversed. This is fixed by this change-set. With this
changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
as setting the voltage to 1.37v (which it had done all along, even
though stating a different target voltage).
After changing the PLL LDO setting, it will take a little while for
the voltage output to settle. A sdelay()-based loop waits the same
order of magnitude as Boot1.
Furthermore, a bit of documentation is added to clarify that the
required setting for the PLL LDO is 1.37v as per the A31 manual.
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -26,13 +26,26 @@ void clock_init_safe(void)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- /* Set PLL ldo voltage without this PLL6 does not work properly */
+ /* Set PLL ldo voltage without this PLL6 does not work properly.
+ *
+ * As the A31 manual states, that "before enable PLL, PLLVDD
+ * LDO should be set to 1.37v", we need to configure this to 2.5v
+ * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
+ */
clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
PRCM_PLL_CTRL_LDO_KEY);
clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+ /* Give the PLL LDO voltage setting some time to take hold.
+ * Notes:
+ * 1) We need to use sdelay() as the timers aren't set up yet.
+ * 2) The 100k iterations come from Boot1, which spin's for 100k
+ * iterations through a loop.
+ */
+ sdelay(100000);
#endif
#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -111,13 +111,13 @@
#define PRCM_PLL_CTRL_LDO_OUT_MASK \
__PRCM_PLL_CTRL_LDO_OUT(0x7)
/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
- __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+ __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)

16
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch Normal file
View File

@@ -0,0 +1,16 @@
From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:52:01 +0200
Subject: sun6i: define alternate-function for UART2 on GPG
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -186,6 +186,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
+#define SUN6I_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN6I_GPH_PWM 2

30
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch Normal file
View File

@@ -0,0 +1,30 @@
From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:53:11 +0200
Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -124,6 +124,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -256,6 +256,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)

23
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch Normal file
View File

@@ -0,0 +1,23 @@
From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:59:38 +0200
Subject: ARM: sunxi: Make CONS_INDEX configurable
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -416,6 +416,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 5
+ default 1
+ ---help---
+ Defines the UART port used for serial output. It starts at 1 so UART0 is 1,
+ UART1 is 2 and so on.
+
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
default n

35
package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch Normal file
View File

@@ -0,0 +1,35 @@
From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Wed, 19 Jul 2017 22:23:15 +0200
Subject: mkimage: check environment for dtc binary location
Currently mkimage assumes the dtc binary is in the path and fails
otherwise. This patch makes it check the DTC environment variable first
for the dtc binary and then fall back to the default path. This makes
it possible to call the u-boot build with make DTC=... and build a fit
image with the dtc binary not being the the default path.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Simon Glass <sjg@chromium.org>
---
tools/fit_image.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -650,9 +650,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {
+ const char* dtc = getenv("DTC");
+
+ if (!dtc)
+ dtc = MKIMAGE_DTC;
+
/* dtc -I dts -O dtb -p 500 datafile > tmpfile */
snprintf(cmd, sizeof(cmd), "%s %s \"%s\" > \"%s\"",
- MKIMAGE_DTC, params->dtc, params->datafile, tmpfile);
+ dtc, params->dtc, params->datafile, tmpfile);
debug("Trying to execute \"%s\"\n", cmd);
} else {
snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",

28
package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch Normal file
View File

@@ -0,0 +1,28 @@
From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Mon, 1 Jan 2018 23:10:56 +0100
Subject: sunxi: deactivate binman
Use the old way to generate the images instead of binman.
binman needs python with swig to avoid this host tool dependency use the
old way of generating images.
---
Makefile | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--- a/Makefile
+++ b/Makefile
@@ -1144,9 +1144,10 @@ u-boot-x86-16bit.bin: u-boot FORCE
endif
ifneq ($(CONFIG_ARCH_SUNXI),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb \
- checkbinman FORCE
- $(call if_changed,binman)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+ $(call if_changed,pad_cat)
endif
ifneq ($(CONFIG_TEGRA),)

165
package/boot/uboot-sunxi/patches/220-add-sunxi50i-nanopi-neo-plus2.patch Normal file
View File

@@ -0,0 +1,165 @@
From 77f54e8698001d8a987f2aa4870f71b65dc089eb Mon Sep 17 00:00:00 2001
In-Reply-To: <20170921152217.4011-1-antony@phenome.org>
References: <20170921152217.4011-1-antony@phenome.org>
From: Antony Antony <antony@phenome.org>
Date: Thu, 21 Sep 2017 13:34:07 +0200
Subject: [PATCH v5 1/2] sun50i: h5: Add NanoPi Neo Plus2 DT initial support
Add initial DT for NanoPi NEO Plus2 by FriendlyARM
- Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
- 1 GB DDR3 RAM
- 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
- micro SD card slot
- Gigabit Ethernet (external RTL8211E-VB-CG chip)
- 802.11 b/g/n WiFi, Bluetooth 4.0 (Ampak AP6212A module)
- 2x USB 2.0 host ports
Signed-off-by: Antony Antony <antony@phenome.org>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 106 ++++++++++++++++++++++++++++
configs/nanopi_neo_plus2_defconfig | 18 +++++
3 files changed, 125 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts
create mode 100644 configs/nanopi_neo_plus2_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -337,6 +337,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-nanopi-neo2.dtb \
+ sun50i-h5-nanopi-neo-plus2.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO Plus 2";
+ compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

52
package/boot/uboot-sunxi/patches/221-compatible-old-dtc.patch Normal file
View File

@@ -0,0 +1,52 @@
Revert the commit c0e032e0090d65 ("scripts/dtc: Update to upstream
version v1.4.3")
OpenWrt uses the dtc from the kernel also in u-boot, but when we compile
against kernel 4.9 we run into some errors because it is too old now.
Add the options only when they are supported to make it compatible with
dtc from kernel 4.9.
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -172,6 +172,11 @@ ld-version = $(shell $(LD) --version | $
# Usage: $(call ld-ifversion, -ge, 22252, y)
ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4))
+# dtc-option
+# Usage: DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+dtc-option = $(call try-run,\
+ echo '/dts-v1/; / {};' | $(DTC) $(1),$(1),$(2))
+
######
###
--- a/scripts/Makefile.extrawarn
+++ b/scripts/Makefile.extrawarn
@@ -58,8 +58,8 @@ endif
KBUILD_CFLAGS += $(warning)
-dtc-warning-2 += -Wnode_name_chars_strict
-dtc-warning-2 += -Wproperty_name_chars_strict
+dtc-warning-2 += $(call dtc-option,-Wnode_name_chars_strict)
+dtc-warning-2 += $(call dtc-option,-Wproperty_name_chars_strict)
dtc-warning := $(dtc-warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
dtc-warning += $(dtc-warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
@@ -70,11 +70,11 @@ DTC_FLAGS += $(dtc-warning)
else
# Disable noisy checks by default
-DTC_FLAGS += -Wno-unit_address_vs_reg
-DTC_FLAGS += -Wno-simple_bus_reg
-DTC_FLAGS += -Wno-unit_address_format
-DTC_FLAGS += -Wno-pci_bridge
-DTC_FLAGS += -Wno-pci_device_bus_num
-DTC_FLAGS += -Wno-pci_device_reg
+DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+DTC_FLAGS += $(call dtc-option,-Wno-simple_bus_reg)
+DTC_FLAGS += $(call dtc-option,-Wno-unit_address_format)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_bridge)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_device_bus_num)
+DTC_FLAGS += $(call dtc-option,-Wno-pci_device_reg)
endif

157
package/boot/uboot-sunxi/patches/320-sunxi-Add-support-for-Orange-Pi-R1.patch Normal file
View File

@@ -0,0 +1,157 @@
From 068fb0d5728c5ec93cb961718d59e7c718886edd Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Tue, 26 Sep 2017 22:16:59 +0200
Subject: sunxi: Add support for Orange Pi R1
The device tree files are also submitted for inclusion into the Linux
kernel.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts | 77 ++++++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 ++
configs/orangepi_r1_defconfig | 26 ++++++++++
4 files changed, 109 insertions(+)
create mode 100644 arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts
create mode 100644 configs/orangepi_r1_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -318,6 +318,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-bananapi-m3.dtb \
sun8i-a83t-cubietruck-plus.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-orangepi-2.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* Orange Pi R1 is based on Orange Pi Zero design */
+#include "sun8i-h2-plus-orangepi-zero.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1";
+ compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
+
+ /delete-node/ reg_vcc_wifi;
+
+ /*
+ * Ths pin of this regulator is the same with the Wi-Fi extra
+ * regulator on the original Zero. However it's used for USB
+ * Ethernet rather than the Wi-Fi now.
+ */
+ reg_vcc_usb_eth: reg-vcc-usb-ethernet {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc-usb-ethernet";
+ enable-active-high;
+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ aliases {
+ ethernet1 = &rtl8189etv;
+ };
+};
+
+&ohci1 {
+ /*
+ * RTL8152B USB-Ethernet adapter is connected to USB1,
+ * and it's a USB 2.0 device. So the OHCI1 controller
+ * can be left disabled.
+ */
+ status = "disabled";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc_usb_eth>;
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -326,6 +326,11 @@ M: Jagan Teki <jagan@amarulasolutions.co
S: Maintained
F: configs/orangepi_prime_defconfig
+ORANGEPI R1 BOARD
+M: Hauke Mehrtens <hauke@hauke-m.de>
+S: Maintained
+F: configs/orangepi_r1_defconfig
+
PINE64 BOARDS
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
--- /dev/null
+++ b/configs/orangepi_r1_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y

148
package/boot/uboot-sunxi/patches/400-ARM-dts-orange-pi-zero-plus.patch Normal file
View File

@@ -0,0 +1,148 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -339,6 +339,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
--- /dev/null
+++ b/configs/orangepi_zero_plus_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero Plus";
+ compatible = "xunlong,orangepizero-zero-plus", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};

5
package/boot/uboot-sunxi/uEnv-a64.txt Normal file
View File

@@ -0,0 +1,5 @@
setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage
setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb
setenv bootargs console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rootwait earlycon=uart,mmio32,0x01c28000
setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
run uenvcmd

6
package/boot/uboot-sunxi/uEnv-default.txt Normal file
View File

@@ -0,0 +1,6 @@
setenv fdt_high ffffffff
setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage
setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb
setenv bootargs console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rootwait
setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
run uenvcmd

6
package/boot/uboot-sunxi/uEnv-pangolin.txt Normal file
View File

@@ -0,0 +1,6 @@
setenv fdt_high ffffffff
setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage
setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb
setenv bootargs console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootwait
setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
run uenvcmd