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domenico
2025-06-24 15:51:28 +02:00
commit 22031d9dab
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34
target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h Normal file
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/*
* Compex's MyLoader specific definitions
*
* Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_FW_MYLOADER_H
#define _ASM_MIPS_FW_MYLOADER_H
#include <linux/myloader.h>
struct myloader_info {
uint32_t vid;
uint32_t did;
uint32_t svid;
uint32_t sdid;
uint8_t macs[MYLO_ETHADDR_COUNT][6];
};
#ifdef CONFIG_MYLOADER
extern struct myloader_info *myloader_get_info(void) __init;
#else
static inline struct myloader_info *myloader_get_info(void)
{
return NULL;
}
#endif /* CONFIG_MYLOADER */
#endif /* _ASM_MIPS_FW_MYLOADER_H */

65
target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h Normal file
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/*
* Atheros AR71xx SoC specific platform data definitions
*
* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ATH79_PLATFORM_H
#define __ASM_MACH_ATH79_PLATFORM_H
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/phy.h>
#include <linux/spi/spi.h>
struct ag71xx_switch_platform_data {
u8 phy4_mii_en:1;
u8 phy_poll_mask;
};
struct ag71xx_platform_data {
phy_interface_t phy_if_mode;
u32 phy_mask;
int speed;
int duplex;
u32 reset_bit;
u8 mac_addr[ETH_ALEN];
struct device *mii_bus_dev;
u8 has_gbit:1;
u8 is_ar91xx:1;
u8 is_ar7240:1;
u8 is_ar724x:1;
u8 has_ar8216:1;
u8 use_flow_control:1;
u8 enable_sgmii_fixup:1;
u8 disable_inline_checksum_engine:1;
struct ag71xx_switch_platform_data *switch_data;
void (*ddr_flush)(void);
void (*set_speed)(int speed);
void (*update_pll)(u32 pll_10, u32 pll_100, u32 pll_1000);
unsigned int max_frame_len;
unsigned int desc_pktlen_mask;
};
struct ag71xx_mdio_platform_data {
u32 phy_mask;
u8 builtin_switch:1;
u8 is_ar7240:1;
u8 is_ar9330:1;
u8 is_ar934x:1;
unsigned long mdio_clock;
unsigned long ref_clock;
void (*reset)(struct mii_bus *bus);
};
#endif /* __ASM_MACH_ATH79_PLATFORM_H */

84
target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h Normal file
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/*
* MikroTik RouterBOARD 750 definitions
*
* Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _MACH_RB750_H
#define _MACH_RB750_H
#include <linux/bitops.h>
#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
#define RB750_GPIO_BTN_RESET 1
#define RB750_GPIO_SPI_CS0 2
#define RB750_GPIO_LED_ACT 12
#define RB750_GPIO_LED_PORT1 13
#define RB750_GPIO_LED_PORT2 14
#define RB750_GPIO_LED_PORT3 15
#define RB750_GPIO_LED_PORT4 16
#define RB750_GPIO_LED_PORT5 17
#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE)
#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
#define RB7XX_GPIO_NAND_NCE 0
#define RB7XX_GPIO_MON 9
#define RB7XX_GPIO_LED_ACT 11
#define RB7XX_GPIO_USB_POWERON 13
#define RB7XX_NAND_NCE BIT(RB7XX_GPIO_NAND_NCE)
#define RB7XX_LED_ACT BIT(RB7XX_GPIO_LED_ACT)
#define RB7XX_MONITOR BIT(RB7XX_GPIO_MON)
#define RB7XX_USB_POWERON BIT(RB7XX_GPIO_USB_POWERON)
struct rb750_led_data {
char *name;
char *default_trigger;
u32 mask;
int active_low;
};
struct rb750_led_platform_data {
int num_leds;
struct rb750_led_data *leds;
void (*latch_change)(u32 clear, u32 set);
};
struct rb7xx_nand_platform_data {
u32 nce_line;
void (*enable_pins)(void);
void (*disable_pins)(void);
void (*latch_change)(u32, u32);
};
#endif /* _MACH_RB750_H */

43
target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h Normal file
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/*
* SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards
*
* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
*
* This file was based on the patches for Linux 2.6.27.39 published by
* MikroTik for their RouterBoard 4xx series devices.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#define CPLD_GPIO_nLED1 0
#define CPLD_GPIO_nLED2 1
#define CPLD_GPIO_nLED3 2
#define CPLD_GPIO_nLED4 3
#define CPLD_GPIO_FAN 4
#define CPLD_GPIO_ALE 5
#define CPLD_GPIO_CLE 6
#define CPLD_GPIO_nCE 7
#define CPLD_GPIO_nLED5 8
#define CPLD_NUM_GPIOS 9
#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1)
#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2)
#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3)
#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4)
#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN)
#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE)
#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE)
#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE)
#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5)
struct rb4xx_cpld_platform_data {
unsigned gpio_base;
};
extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value);
extern int rb4xx_cpld_read(unsigned char *rx_buf,
unsigned cnt);
extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count);