Initial commit
This commit is contained in:
domenico
374
target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
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374
target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
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@@ -0,0 +1,374 @@
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/*
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* Cavium CNS3xxx I2C Host Controller
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*
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* Copyright 2010 Cavium Network
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* Copyright 2012 Gateworks Corporation
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* Chris Lang <clang@gateworks.com>
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* Tim Harvey <tharvey@gateworks.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <linux/wait.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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/*
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* We need the memory map
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*/
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#define I2C_MEM_MAP_ADDR(x) (i2c->base + x)
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#define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
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#define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x00)
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#define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x04)
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#define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x08)
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#define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x0C)
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#define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x10)
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#define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x14)
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#define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x18)
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#define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x1C)
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#define I2C_BUS_ERROR_FLAG (0x1)
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#define I2C_ACTION_DONE_FLAG (0x2)
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#define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31)
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#define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31)
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#define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03
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#define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc
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#define TWI_TIMEOUT (10*HZ)
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#define I2C_100KHZ 100000
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#define I2C_200KHZ 200000
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#define I2C_300KHZ 300000
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#define I2C_400KHZ 400000
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#define CNS3xxx_I2C_CLK I2C_100KHZ
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#define STATE_DONE 1
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#define STATE_ERROR 2
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struct cns3xxx_i2c {
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struct device *dev;
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void __iomem *base; /* virtual */
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wait_queue_head_t wait;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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u8 state; /* see STATE_ */
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u8 error; /* see TWI_STATUS register */
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int rd_wr_len;
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u8 *buf;
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};
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static u32 cns3xxx_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static int
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cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg)
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{
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struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap);
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int i, j;
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u8 buf[1] = { 0 };
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if (msg->len == 0) {
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/*
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* We are probably doing a probe for a device here,
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* so set the length to one, and data to 0
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*/
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msg->len = 1;
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i2c->buf = buf;
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} else {
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i2c->buf = msg->buf;
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}
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if (msg->flags & I2C_M_TEN) {
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printk
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("%s:%d: Presently the driver does not handle extended addressing\n",
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__FUNCTION__, __LINE__);
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return -EINVAL;
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}
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i2c->msg = msg;
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for (i = 0; i < msg->len; i++) {
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if (msg->len - i >= 4)
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i2c->rd_wr_len = 3;
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else
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i2c->rd_wr_len = msg->len - i - 1;
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// Set Data Width and TWI_EN
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I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
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// Clear Write Reg
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I2C_WRITE_DATA_REG = 0;
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// Set the slave address
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I2C_SLAVE_ADDRESS_REG = (msg->addr << 1);
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// Are we Writing
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if (!(msg->flags & I2C_M_RD)) {
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I2C_CONTROLLER_REG |= (1 << 4);
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if (i != 0) {
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/*
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* We need to set the address in the first byte.
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* The base address is going to be in buf[0] and then
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* it needs to be incremented by i - 1.
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*/
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i2c->buf--;
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*i2c->buf = buf[0] + i - 1;
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if (i2c->rd_wr_len < 3) {
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i += i2c->rd_wr_len;
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i2c->rd_wr_len++;
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I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
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} else {
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i += i2c->rd_wr_len - 1;
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}
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} else {
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i += i2c->rd_wr_len;
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buf[0] = *i2c->buf;
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}
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for (j = 0; j <= i2c->rd_wr_len; j++) {
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I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j));
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}
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} else {
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i += i2c->rd_wr_len;
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}
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// Start the Transfer
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i2c->state = 0; // Clear out the State
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i2c->error = 0;
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I2C_CONTROLLER_REG |= (1 << 6);
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if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
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(i2c->state == STATE_DONE), TWI_TIMEOUT)) {
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if (i2c->state == STATE_ERROR) {
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dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error);
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return -EAGAIN; // try again
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}
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} else {
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dev_err(i2c->dev, "controller timed out "
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"waiting for start condition to finish\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int
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cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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int i;
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int ret;
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for (i = 0; i < num; i++)
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{
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ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]);
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if (ret < 0) {
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return ret;
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}
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}
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return num;
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}
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static struct i2c_algorithm cns3xxx_i2c_algo = {
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.master_xfer = cns3xxx_i2c_xfer,
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.functionality = cns3xxx_i2c_func,
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};
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static struct i2c_adapter cns3xxx_i2c_adapter = {
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.owner = THIS_MODULE,
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.algo = &cns3xxx_i2c_algo,
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.algo_data = NULL,
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.nr = 0,
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.name = "CNS3xxx I2C 0",
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.retries = 5,
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};
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static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
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{
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struct clk *clk;
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clk = devm_clk_get(i2c->dev, "cpu");
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if (WARN_ON(!clk))
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return;
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/* Disable the I2C */
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I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
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/* Check the Reg Dump when testing */
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I2C_TIME_OUT_REG =
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(((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
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1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
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I2C_TWI_OUT_DLY_REG |= 0x3;
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/* Enable The Interrupt */
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CNS3xxx_I2C_ENABLE_INTR();
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/* Clear Interrupt Status (0x2 | 0x1) */
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I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
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/* Enable the I2C Controller */
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CNS3xxx_I2C_ENABLE();
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}
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static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id)
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{
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struct cns3xxx_i2c *i2c = dev_id;
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int i;
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uint32_t stat = I2C_INTERRUPT_STATUS_REG;
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/* Clear Interrupt */
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I2C_INTERRUPT_STATUS_REG |= 0x1;
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if (stat & I2C_BUS_ERROR_FLAG) {
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i2c->state = STATE_ERROR;
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i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8;
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} else {
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if (i2c->msg->flags & I2C_M_RD) {
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for (i = 0; i <= i2c->rd_wr_len; i++)
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{
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*i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff);
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}
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}
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i2c->state = STATE_DONE;
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}
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wake_up(&i2c->wait);
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return IRQ_HANDLED;
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}
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static int cns3xxx_i2c_probe(struct platform_device *pdev)
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{
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struct cns3xxx_i2c *i2c;
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struct resource *res, *res2;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__);
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return -ENODEV;
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}
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res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res2) {
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printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__);
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return -ENODEV;
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}
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i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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if (!request_mem_region(res->start, res->end - res->start + 1,
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pdev->name)) {
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dev_err(&pdev->dev, "Memory region busy\n");
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ret = -EBUSY;
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goto request_mem_failed;
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}
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i2c->dev = &pdev->dev;
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i2c->base = ioremap(res->start, res->end - res->start + 1);
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if (!i2c->base) {
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dev_err(&pdev->dev, "Unable to map registers\n");
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ret = -EIO;
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goto map_failed;
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}
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cns3xxx_i2c_adapter_init(i2c);
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init_waitqueue_head(&i2c->wait);
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ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c);
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if (ret) {
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dev_err(&pdev->dev, "Cannot claim IRQ\n");
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goto request_irq_failed;
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}
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platform_set_drvdata(pdev, i2c);
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i2c->adap = cns3xxx_i2c_adapter;
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i2c_set_adapdata(&i2c->adap, i2c);
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i2c->adap.dev.parent = &pdev->dev;
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/* add i2c adapter to i2c tree */
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ret = i2c_add_numbered_adapter(&i2c->adap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add adapter\n");
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goto add_adapter_failed;
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}
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return 0;
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add_adapter_failed:
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free_irq(res2->start, i2c);
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request_irq_failed:
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iounmap(i2c->base);
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map_failed:
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release_mem_region(res->start, res->end - res->start + 1);
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request_mem_failed:
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kfree(i2c);
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return ret;
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}
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static int cns3xxx_i2c_remove(struct platform_device *pdev)
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{
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struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev);
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struct resource *res;
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/* disable i2c logic */
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CNS3xxx_I2C_DISABLE_INTR();
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CNS3xxx_I2C_DISABLE();
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/* remove adapter & data */
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i2c_del_adapter(&i2c->adap);
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platform_set_drvdata(pdev, NULL);
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (res)
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free_irq(res->start, i2c);
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iounmap(i2c->base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res)
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release_mem_region(res->start, res->end - res->start + 1);
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kfree(i2c);
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return 0;
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}
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static struct platform_driver cns3xxx_i2c_driver = {
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.probe = cns3xxx_i2c_probe,
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.remove = cns3xxx_i2c_remove,
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.driver = {
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.owner = THIS_MODULE,
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.name = "cns3xxx-i2c",
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},
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};
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static int __init cns3xxx_i2c_init(void)
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{
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return platform_driver_register(&cns3xxx_i2c_driver);
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}
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static void __exit cns3xxx_i2c_exit(void)
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{
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platform_driver_unregister(&cns3xxx_i2c_driver);
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}
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module_init(cns3xxx_i2c_init);
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module_exit(cns3xxx_i2c_exit);
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MODULE_AUTHOR("Cavium Networks");
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MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller");
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MODULE_LICENSE("GPL");
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