Initial commit

target/linux/ipq40xx/Makefile

@@ -0,0 +1,22 @@
+include $(TOPDIR)/rules.mk
+
+ARCH:=arm
+BOARD:=ipq40xx
+BOARDNAME:=Qualcomm Atheros IPQ40XX
+FEATURES:=squashfs fpu ramdisk nand
+CPU_TYPE:=cortex-a7
+CPU_SUBTYPE:=neon-vfpv4
+MAINTAINER:=John Crispin <john@phrozen.org>
+
+KERNEL_PATCHVER:=4.14
+
+KERNELNAME:=zImage Image dtbs
+
+include $(INCLUDE_DIR)/target.mk
+DEFAULT_PACKAGES += \
+	kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
+	kmod-ath10k wpad-mini \
+	kmod-usb3 kmod-usb-dwc3-of-simple kmod-usb-phy-qcom-dwc3 \
+	ath10k-firmware-qca4019
+
+$(eval $(call BuildTarget))

target/linux/ipq40xx/base-files/etc/board.d/01_leds

@@ -0,0 +1,47 @@
+#!/bin/sh
+#
+# Copyright (C) 2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+boardname="${board##*,}"
+
+case "$board" in
+asus,rt-ac58u)
+	ucidef_set_led_wlan "wlan2g" "WLAN2G" "${boardname}:blue:wlan2G" "phy0tpt"
+	ucidef_set_led_wlan "wlan5g" "WLAN5G" "${boardname}:blue:wlan5G" "phy1tpt"
+	ucidef_set_led_usbport "usb" "USB" "${boardname}:blue:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1"
+	ucidef_set_led_netdev "wan" "WAN" "${boardname}:blue:wan" "eth1"
+	ucidef_set_led_switch "lan" "LAN" "${boardname}:blue:lan" "switch0" "0x1e"
+	;;
+avm,fritzbox-4040)
+	ucidef_set_led_wlan "wlan" "WLAN" "fritz4040:green:wlan" "phy0tpt" "phy1tpt"
+	ucidef_set_led_netdev "wan" "WAN" "fritz4040:green:wan" "eth1"
+	ucidef_set_led_switch "lan" "LAN" "fritz4040:green:lan" "switch0" "0x1e"
+	;;
+glinet,gl-b1300)
+	ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wlan" "phy0tpt"
+	;;
+netgear,ex6100v2 |\
+netgear,ex6150v2)
+	ucidef_set_led_wlan "wlan2g" "WLAN2G" "ex61x0v2:green:router" "phy0tpt"
+	ucidef_set_led_wlan "wlan5g" "WLAN5G" "ex61x0v2:green:client" "phy1tpt"
+	;;
+meraki,mr33)
+	ucidef_set_interface_lan "eth0"
+	;;
+zyxel,wre6606)
+	ucidef_set_led_wlan "wlan2g" "WLAN2G" "${boardname}:green:wlan2g" "phy0tpt"
+	ucidef_set_led_wlan "wlan5g" "WLAN5G" "${boardname}:green:wlan5g" "phy1tpt"
+	;;
+*)
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/ipq40xx/base-files/etc/board.d/02_network

@@ -0,0 +1,58 @@
+#!/bin/sh
+#
+# Copyright (c) 2015 The Linux Foundation. All rights reserved.
+# Copyright (c) 2011-2015 OpenWrt.org
+#
+
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+8dev,jalapeno)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	;;
+asus,rt-ac58u)
+	CI_UBIPART=UBI_DEV
+	wan_mac_addr=$(mtd_get_mac_binary_ubi Factory 20486)
+	lan_mac_addr=$(mtd_get_mac_binary_ubi Factory 4102)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	ucidef_add_switch "switch0" \
+		"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
+	ucidef_set_interface_macaddr "lan" "$lan_mac_addr"
+	ucidef_set_interface_macaddr "wan" "$wan_mac_addr"
+	;;
+avm,fritzbox-4040)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	ucidef_add_switch "switch0" \
+		"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
+	;;
+compex,wpj428)
+	ucidef_set_interface_lan "eth0 eth1"
+	;;
+glinet,gl-b1300)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	ucidef_add_switch "switch0" \
+		"0u@eth0" "3:lan" "4:lan"
+	;;
+openmesh,a42 |\
+openmesh,a62)
+	ucidef_set_interfaces_lan_wan "eth1" "eth0"
+	;;
+meraki,mr33 |\
+netgear,ex6100v2 |\
+netgear,ex6150v2 |\
+zyxel,wre6606)
+	ucidef_set_interface_lan "eth0"
+	;;
+*)
+	echo "Unsupported hardware. Network interfaces not intialized"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches

@@ -0,0 +1,17 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+compex,wpj428)
+	ucidef_add_gpio_switch "sim_card_select" "SIM card select" "3" "0"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/ipq40xx/base-files/etc/diag.sh

@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /lib/functions/leds.sh
+
+boot="$(get_dt_led boot)"
+failsafe="$(get_dt_led failsafe)"
+running="$(get_dt_led running)"
+upgrade="$(get_dt_led upgrade)"
+
+get_status_led() {
+	status_led="$boot"
+}
+
+set_state() {
+	status_led="$boot"
+
+	case "$1" in
+	preinit)
+		status_led_blink_preinit
+		;;
+	failsafe)
+		status_led_off
+		[ -n "$running" ] && {
+			status_led="$running"
+			status_led_off
+		}
+		status_led="$failsafe"
+		status_led_blink_failsafe
+		;;
+	preinit_regular)
+		status_led_blink_preinit_regular
+		;;
+	upgrade)
+		[ -n "$running" ] && {
+			status_led="$upgrade"
+			status_led_blink_preinit_regular
+		}
+		;;
+	done)
+		status_led_off
+		[ -n "$running" ] && {
+			status_led="$running"
+			status_led_on
+		}
+		;;
+	esac
+}

target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata

@@ -0,0 +1,193 @@
+#!/bin/sh
+
+# xor multiple hex values of the same length
+xor() {
+	local val
+	local ret="0x$1"
+	local retlen=${#1}
+
+	shift
+	while [ -n "$1" ]; do
+		val="0x$1"
+		ret=$((ret ^ val))
+		shift
+	done
+
+	printf "%0${retlen}x" "$ret"
+}
+
+ath10kcal_die() {
+	echo "ath10cal: " "$*"
+	exit 1
+}
+
+ath10kcal_extract() {
+	local part=$1
+	local offset=$2
+	local count=$3
+	local mtd
+
+	mtd=$(find_mtd_chardev $part)
+	[ -n "$mtd" ] || \
+		ath10kcal_die "no mtd device found for partition $part"
+
+	dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \
+		ath10kcal_die "failed to extract calibration data from $mtd"
+}
+
+ath10kcal_ubi_extract() {
+	local part=$1
+	local offset=$2
+	local count=$3
+	local ubidev
+	local ubi
+
+	. /lib/upgrade/nand.sh
+
+	ubidev=$(nand_find_ubi $CI_UBIPART)
+	ubi=$(nand_find_volume $ubidev $part)
+	[ -n "$ubi" ] || \
+		ath10kcal_die "no UBI volume found for $part"
+
+	dd if=/dev/$ubi of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \
+		ath10kcal_die "failed to extract from $ubi"
+}
+
+ath10kcal_patch_mac() {
+	local mac=$1
+
+	[ -z "$mac" ] && return
+
+	macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=6 count=6
+}
+
+ath10kcal_patch_mac_crc() {
+	local mac=$1
+	local mac_offset=6
+	local chksum_offset=2
+	local xor_mac
+	local xor_fw_mac
+	local xor_fw_chksum
+
+	xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
+	xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}"
+
+	ath10kcal_patch_mac "$mac" && {
+		xor_mac=${mac//:/}
+		xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}"
+
+		xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
+		xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac)
+
+		printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \
+			dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$chksum_offset count=2
+	}
+}
+
+ath10kcal_is_caldata_valid() {
+	local expected="$1"
+
+	magic=$(hexdump -v -n 2 -e '1/1 "%02x"' /lib/firmware/$FIRMWARE)
+	[[ "$magic" == "$expected" ]]
+	return $?
+}
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+board=$(board_name)
+
+
+case "$FIRMWARE" in
+"ath10k/cal-pci-0000:01:00.0.bin")
+	case "$board" in
+	meraki,mr33)
+		ath10kcal_ubi_extract "ART" 36864 2116
+		ath10kcal_is_caldata_valid "4408" || ath10kcal_extract "ART" 36864 2116
+		ath10kcal_patch_mac $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +1)
+		;;
+	esac
+	;;
+"ath10k/pre-cal-pci-0000:01:00.0.bin")
+	case "$board" in
+	openmesh,a62)
+		ath10kcal_extract "0:ART" 36864 12064
+		;;
+	esac
+	;;
+"ath10k/pre-cal-ahb-a000000.wifi.bin")
+	case "$board" in
+	8dev,jalapeno |\
+	glinet,gl-b1300 |\
+	qcom,ap-dk01.1-c1)
+		ath10kcal_extract "ART" 4096 12064
+		;;
+	asus,rt-ac58u)
+		CI_UBIPART=UBI_DEV
+		ath10kcal_ubi_extract "Factory" 4096 12064
+		;;
+	avm,fritzbox-4040)
+		/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
+		;;
+	meraki,mr33)
+		ath10kcal_ubi_extract "ART" 4096 12064
+		ath10kcal_is_caldata_valid "202f" || ath10kcal_extract "ART" 4096 12064
+		ath10kcal_patch_mac_crc $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +2)
+		;;
+	netgear,ex6100v2 |\
+	netgear,ex6150v2)
+		ath10kcal_extract "ART" 4096 12064
+		ath10kcal_patch_mac_crc $(mtd_get_mac_binary dnidata 0)
+		;;
+	compex,wpj428 |\
+	openmesh,a42 |\
+	openmesh,a62)
+		ath10kcal_extract "0:ART" 4096 12064
+		;;
+	zyxel,wre6606)
+		ath10kcal_extract "ART" 4096 12064
+		ath10kcal_patch_mac_crc $(macaddr_add $(cat /sys/class/net/eth0/address) -2)
+		;;
+	esac
+	;;
+"ath10k/pre-cal-ahb-a800000.wifi.bin")
+	case "$board" in
+	8dev,jalapeno |\
+	glinet,gl-b1300 |\
+	qcom,ap-dk01.1-c1)
+		ath10kcal_extract "ART" 20480 12064
+		;;
+	asus,rt-ac58u)
+		CI_UBIPART=UBI_DEV
+		ath10kcal_ubi_extract "Factory" 20480 12064
+		;;
+	avm,fritzbox-4040)
+		/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
+		;;
+	meraki,mr33)
+		ath10kcal_ubi_extract "ART" 20480 12064
+		ath10kcal_is_caldata_valid "202f" || ath10kcal_extract "ART" 20480 12064
+		ath10kcal_patch_mac_crc $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +3)
+		;;
+	netgear,ex6100v2 |\
+	netgear,ex6150v2)
+		ath10kcal_extract "ART" 20480 12064
+		ath10kcal_patch_mac_crc $(mtd_get_mac_binary dnidata 12)
+		;;
+	compex,wpj428 |\
+	openmesh,a42 |\
+	openmesh,a62)
+		ath10kcal_extract "0:ART" 20480 12064
+		;;
+	zyxel,wre6606)
+		ath10kcal_extract "ART" 20480 12064
+		ath10kcal_patch_mac_crc $(macaddr_add $(cat /sys/class/net/eth0/address) -1)
+		;;
+	esac
+	;;
+*)
+	exit 1
+	;;
+esac

target/linux/ipq40xx/base-files/etc/inittab

@@ -0,0 +1,4 @@
+# Copyright (c) 2013 The Linux Foundation. All rights reserved.
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+ttyMSM0::askfirst:/usr/libexec/login.sh

target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh

@@ -0,0 +1,14 @@
+#!/bin/sh
+
+. /lib/functions.sh
+
+preinit_set_mac_address() {
+	case $(board_name) in
+	meraki,mr33)
+		mac_lan=$(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102)
+		[ -n "$mac_lan" ] && ip link set dev eth0 address "$mac_lan"
+		;;
+	esac
+}
+
+boot_hook_add preinit_main preinit_set_mac_address

target/linux/ipq40xx/base-files/lib/upgrade/openmesh.sh

@@ -0,0 +1,113 @@
+# The U-Boot loader of the OpenMesh devices requires image sizes and
+# checksums to be provided in the U-Boot environment.
+# The OpenMesh devices come with 2 main partitions - while one is active
+# sysupgrade will flash the other. The boot order is changed to boot the
+# newly flashed partition. If the new partition can't be booted due to
+# upgrade failures the previously used partition is loaded.
+
+platform_do_upgrade_openmesh() {
+	local tar_file="$1"
+	local restore_backup
+	local primary_kernel_mtd
+
+	local setenv_script="/tmp/fw_env_upgrade"
+
+	local kernel_mtd="$(find_mtd_index $PART_NAME)"
+	local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
+	local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
+
+	# detect to which flash region the new image is written to.
+	#
+	# 1. check what is the mtd index for the first flash region on this
+	#    device
+	# 2. check if the target partition ("inactive") has the mtd index of
+	#    the first flash region
+	#
+	#    - when it is: the new bootseq will be 1,2 and the first region is
+	#      modified
+	#    - when it isnt: bootseq will be 2,1 and the second region is
+	#      modified
+	#
+	# The detection has to be done via the hardcoded mtd partition because
+	# the current boot might be done with the fallback region. Let us
+	# assume that the current bootseq is 1,2. The bootloader detected that
+	# the image in flash region 1 is corrupt and thus switches to flash
+	# region 2. The bootseq in the u-boot-env is now still the same and
+	# the sysupgrade code can now only rely on the actual mtd indexes and
+	# not the bootseq variable to detect the currently booted flash
+	# region/image.
+	#
+	# In the above example, an implementation which uses bootseq ("1,2") to
+	# detect the currently booted image would assume that region 1 is booted
+	# and then overwrite the variables for the wrong flash region (aka the
+	# one which isn't modified). This could result in a device which doesn't
+	# boot anymore to Linux until it was reflashed with ap51-flash.
+	local next_boot_part="1"
+	case "$(board_name)" in
+	openmesh,a42)
+		primary_kernel_mtd=8
+		;;
+	openmesh,a62)
+		primary_kernel_mtd=10
+		;;
+	*)
+		echo "failed to detect primary kernel mtd partition for board"
+		return 1
+		;;
+	esac
+	[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
+
+	local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
+	board_dir=${board_dir%/}
+
+	local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
+	local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
+	# rootfs without EOF marker
+	rootfs_length=$((rootfs_length-4))
+
+	local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
+	# md5 checksum of rootfs with EOF marker
+	local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
+
+	#
+	# add tar support to get_image() to use default_do_upgrade() instead?
+	#
+
+	# take care of restoring a saved config
+	[ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}"
+
+	mtd -q erase inactive
+	tar xf $tar_file ${board_dir}/root -O | mtd -n -p $kernel_length $restore_backup write - $PART_NAME
+	tar xf $tar_file ${board_dir}/kernel -O | mtd -n write - $PART_NAME
+
+	# prepare new u-boot env
+	if [ "$next_boot_part" = "1" ]; then
+		echo "bootseq 1,2" > $setenv_script
+	else
+		echo "bootseq 2,1" > $setenv_script
+	fi
+
+	printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
+	printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
+	printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
+	printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
+
+	printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
+	printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
+	printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
+	printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
+
+	# store u-boot env changes
+	fw_setenv -s $setenv_script || {
+		echo "failed to update U-Boot environment"
+		return 1
+	}
+}
+
+# create /var/lock for the lock "fw_setenv.lock" of fw_setenv
+# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA
+platform_add_ramfs_ubootenv()
+{
+	mkdir -p $RAM_ROOT/var/lock
+}
+append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv

target/linux/ipq40xx/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,73 @@
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+RAMFS_COPY_BIN='fw_printenv fw_setenv'
+RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
+
+platform_check_image() {
+	case "$(board_name)" in
+	asus,rt-ac58u)
+		CI_UBIPART="UBI_DEV"
+		local ubidev=$(nand_find_ubi $CI_UBIPART)
+		local asus_root=$(nand_find_volume $ubidev jffs2)
+
+		[ -n "$asus_root" ] || return 0
+
+		cat << EOF
+jffs2 partition is still present.
+There's probably no space left
+to install the filesystem.
+
+You need to delete the jffs2 partition first:
+# ubirmvol /dev/ubi0 --name=jffs2
+
+Once this is done. Retry.
+EOF
+		return 1
+		;;
+	esac
+	return 0;
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	8dev,jalapeno)
+		nand_do_upgrade "$ARGV"
+		;;
+	asus,rt-ac58u)
+		CI_UBIPART="UBI_DEV"
+		CI_KERNPART="linux"
+		nand_do_upgrade "$1"
+		;;
+	openmesh,a42 |\
+	openmesh,a62)
+		PART_NAME="inactive"
+		platform_do_upgrade_openmesh "$ARGV"
+		;;
+	meraki,mr33)
+		CI_KERNPART="part.safe"
+		nand_do_upgrade "$1"
+		;;
+	*)
+		default_do_upgrade "$ARGV"
+		;;
+	esac
+}
+
+platform_nand_pre_upgrade() {
+	case "$(board_name)" in
+	asus,rt-ac58u)
+		CI_UBIPART="UBI_DEV"
+		CI_KERNPART="linux"
+		;;
+	meraki,mr33)
+		CI_KERNPART="part.safe"
+		;;
+	esac
+}
+
+blink_led() {
+	. /etc/diag.sh; set_state upgrade
+}
+
+append sysupgrade_pre_upgrade blink_led

target/linux/ipq40xx/config-4.14

@@ -0,0 +1,485 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_AR40XX_PHY=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+# CONFIG_ARCH_MSM8X60 is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_QCOM_CPUIDLE=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+CONFIG_BUS_TOPOLOGY_ADHOC=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ESSEDMA=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_LP5562=y
+CONFIG_LEDS_LP55XX_COMMON=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ40XX=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+# CONFIG_MFD_QCOM_RPM is not set
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSM_BUS_SCALING=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_SPINAND_MT29F=y
+CONFIG_MTD_SPINAND_ONDIEECC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K=y
+CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPTEE=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_UFS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_IPQ8074 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_IOMMU is not set
+CONFIG_QCOM_PM=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SCM_32=y
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMP2P is not set
+# CONFIG_QCOM_SMSM is not set
+CONFIG_QCOM_TCSR=y
+# CONFIG_QCOM_TSENS is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QRTR is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+# CONFIG_RPMSG_QCOM_SMD is not set
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_FSL=y
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TEE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_IPQ4019_PHY=y
+CONFIG_USB_PHY=y
+# CONFIG_USB_QCOM_8X16_PHY is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-a42.dts

@@ -0,0 +1,216 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "OpenMesh A42";
+	compatible = "openmesh,a42", "qcom,ipq4019";
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@194b000 {
+			/* select hostmode */
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		red {
+			label = "a42:red:status";
+			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-off";
+		};
+
+		power: green {
+			label = "a42:green:status";
+			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "a42:blue:status";
+			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-off";
+		};
+	};
+
+	watchdog {
+		compatible = "linux,wdt-gpio";
+		gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+		hw_algo = "toggle";
+		/* hw_margin_ms is actually 300s but driver limits it to 60s */
+		hw_margin_ms = <60000>;
+		always-running;
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		/* partitions are passed via bootloader */
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac0 {
+	qcom,phy_mdio_addr = <4>;
+	qcom,poll_required = <1>;
+	qcom,forced_speed = <1000>;
+	qcom,forced_duplex = <1>;
+	vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+	qcom,phy_mdio_addr = <3>;
+	qcom,poll_required = <1>;
+	qcom,forced_speed = <1000>;
+	qcom,forced_duplex = <1>;
+	vlan_tag = <1 0x10>;
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "OM-A42";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "OM-A42";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts

@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4018-ex61x0v2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Netgear EX6100v2";
+	compatible = "netgear,ex6100v2", "qcom,ipq4019";
+};
+
+&wifi0 {
+	qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
+};
+
+&wifi1 {
+	qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts

@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4018-ex61x0v2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Netgear EX6150v2";
+	compatible = "netgear,ex6150v2", "qcom,ipq4019";
+};
+
+&wifi0 {
+	qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
+};
+
+&wifi1 {
+	qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi

@@ -0,0 +1,307 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "Netgear EX61X0v2";
+	compatible = "netgear,ex61x0v2", "qcom,ipq4019";
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+			qcom,num_gmac = <1>;
+		};
+	};
+
+	aliases {
+		led-boot = &power_amber;
+		led-failsafe = &power_amber;
+		led-running = &power_green;
+		led-upgrade = &power_amber;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	led_spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		ranges;
+
+		gpio-sck = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		led_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <1000000>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_amber: power_amber {
+			label = "ex61x0v2:amber:power";
+			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		power_green: power_green {
+			label = "ex61x0v2:green:power";
+			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		right {
+			label = "ex61x0v2:blue:right";
+			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		left {
+			label = "ex61x0v2:blue:left";
+			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		client_green {
+			label = "ex61x0v2:green:client";
+			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		client_red {
+			label = "ex61x0v2:red:client";
+			gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		router_green {
+			label = "ex61x0v2:green:router";
+			gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		router_red {
+			label = "ex61x0v2:red:router";
+			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "ex61x0v2:green:wps";
+			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	mx25l12805d@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+
+			partition1@40000 {
+				label = "MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+
+			partition2@60000 {
+				label = "QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+
+			partition3@c0000 {
+				label = "CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+
+			partition4@d0000 {
+				label = "DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+
+			partition5@E0000 {
+				label = "APPSBLENV";
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+
+			partition6@F0000 {
+				label = "APPSBL";
+				reg = <0x000f0000 0x00080000>;
+				read-only;
+			};
+
+			partition7@170000 {
+				label = "ART";
+				reg = <0x00170000 0x00010000>;
+				read-only;
+			};
+
+			partition8@180000 {
+				label = "config";
+				reg = <0x00180000 0x00010000>;
+				read-only;
+			};
+
+			partition9@190000 {
+				label = "pot";
+				reg = <0x00190000 0x00010000>;
+				read-only;
+			};
+
+			partition10@1a0000 {
+				label = "dnidata";
+				reg = <0x001a0000 0x00010000>;
+				read-only;
+			};
+
+			partition11@1b0000 {
+				label = "firmware";
+				reg = <0x001b0000 0x00e10000>;
+			};
+
+			partition12@fc0000 {
+				label = "language";
+				reg = <0x00fc0000 0x00040000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+};
+
+&wifi1 {
+	status = "okay";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-fritz4040.dts

@@ -0,0 +1,303 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "AVM FRITZ!Box 4040";
+	compatible = "avm,fritzbox-4040", "qcom,ipq4019";
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &flash;
+		led-running = &power;
+		led-upgrade = &flash;
+	};
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3@8af8800 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		wifi@a000000 {
+			status = "okay";
+			qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
+		};
+
+		wifi@a800000 {
+			status = "okay";
+			qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		qca8075: ess-switch@c000000 {
+			status = "okay";
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			enable-usb-power {
+				gpio-hog;
+				line-name = "enable USB3 power";
+				gpios = <7 GPIO_ACTIVE_HIGH>;
+				output-high;
+			};
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wlan {
+			label = "wlan";
+			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "fritz4040:green:wlan";
+			gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		panic: info_red {
+			label = "fritz4040:red:info";
+			gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		wan {
+			label = "fritz4040:green:wan";
+			gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		power: power {
+			label = "fritz4040:green:power";
+			gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		lan {
+			label = "fritz4040:green:lan";
+			gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
+		};
+
+		flash: info_amber {
+			label = "fritz4040:amber:info";
+			gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		mux {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+
+		mux_cs {
+			function = "gpio";
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	mx25l25635f@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		status = "okay";
+		m25p,fast-read;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition1@40000 {
+				label = "MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+			partition2@60000 {
+				label = "QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+			partition3@c0000 {
+				label = "CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+			partition4@d0000 {
+				label = "DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+			partition5@e0000 {
+				label = "APPSBLENV"; /* uboot env - empty */
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+			partition6@f0000 {
+				label = "urlader"; /* APPSBL */
+				reg = <0x000f0000 0x0002dc000>;
+				read-only;
+			};
+			partition7@11dc00 {
+				/* make a backup of this partition! */
+				label = "urlader_config";
+				reg = <0x0011dc00 0x00002400>;
+				read-only;
+			};
+			partition8@120000 {
+				label = "tffs1";
+				reg = <0x00120000 0x00080000>;
+				read-only;
+			};
+			partition9@1a0000 {
+				label = "tffs2";
+				reg = <0x001a0000 0x00080000>;
+				read-only;
+			};
+			partition10@220000 {
+				label = "uboot";
+				reg = <0x00220000 0x00080000>;
+				read-only;
+			};
+			partition11@2A0000 {
+				label = "firmware";
+				reg = <0x002a0000 0x01c60000>;
+			};
+			partition12@1f00000 {
+				label = "jffs2";
+				reg = <0x01f00000 0x00100000>;
+			};
+		};
+	};
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts

@@ -0,0 +1,267 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "8devices Jalapeno";
+	compatible = "8dev,jalapeno", "qcom,ipq4019";
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+			pinctrl-0 = <&mdio_pins>;
+			pinctrl-names = "default";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		counter@4a1000 {
+			compatible = "qcom,qca-gcnt";
+			reg = <0x4a1000 0x4>;
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			/* select hostmode */
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+			status = "okay";
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3: usb3@8af8800 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+			switch_lan_bmp = <0x10>; /* lan port bitmap */
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio_pinmux {
+		pinmux_1 {
+			pins = "gpio53";
+			function = "mdio";
+		};
+		pinmux_2 {
+			pins = "gpio52";
+			function = "mdc";
+		};
+		pinconf {
+			pins = "gpio52", "gpio53";
+			bias-pull-up;
+		};
+	};
+
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <2>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio54", "gpio59";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition1@40000 {
+				label = "MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+			partition2@60000 {
+				label = "QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+			partition3@c0000 {
+				label = "CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+			partition4@d0000 {
+				label = "DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+			partition5@e0000 {
+				label = "APPSBLENV"; /* uboot env*/
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+			partition5@f0000 {
+				label = "APPSBL"; /* uboot */
+				reg = <0x000f0000 0x00080000>;
+				read-only;
+			};
+			partition5@170000 {
+				label = "ART";
+				reg = <0x00170000 0x00010000>;
+				read-only;
+			};
+		};
+	};
+
+	mt29f@1 {
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "spinand,mt29f", "w25n01gv";
+		reg = <1>;
+		spi-max-frequency = <24000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "ubi";
+				reg = <0x00000000 0x08000000>;
+			};
+		};
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac0 {
+	qcom,poll_required = <1>;
+	qcom,poll_required_dynamic = <1>;
+	qcom,phy_mdio_addr = <3>;
+	vlan_tag = <1 0x10>;
+};
+
+&gmac1 {
+	qcom,poll_required = <1>;
+	qcom,poll_required_dynamic = <1>;
+	qcom,phy_mdio_addr = <4>;
+	vlan_tag = <2 0x20>;
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts

@@ -0,0 +1,298 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "ASUS RT-AC58U";
+	compatible = "asus,rt-ac58u", "qcom,ipq4019";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x8000000>;
+	};
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3@8af8800 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		wifi@a000000 {
+			status = "okay";
+			qcom,ath10k-calibration-variant = "RT-AC58U";
+		};
+
+		wifi@a800000 {
+			status = "okay";
+			qcom,ath10k-calibration-variant = "RT-AC58U";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power: status {
+			label = "rt-ac58u:blue:status";
+			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan {
+			label = "rt-ac58u:blue:wan";
+			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan2G {
+			label = "rt-ac58u:blue:wlan2G";
+			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan5G {
+			label = "rt-ac58u:blue:wlan5G";
+			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		usb {
+			label = "rt-ac58u:blue:usb";
+			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		lan {
+			label = "rt-ac58u:blue:lan";
+			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		mux {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+
+		mux_cs {
+			function = "gpio";
+			pins = "gpio54", "gpio59";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
+		   <&tlmm 59 GPIO_ACTIVE_HIGH>;
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		/*
+		 * U-boot looks for "n25q128a11" node,
+		 * if we don't have it, it will spit out the following warning:
+		 * "ipq: fdt fixup unable to find compatible node".
+		 */
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition1@40000 {
+				label = "MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+			partition2@60000 {
+				label = "QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+			partition3@c0000 {
+				label = "CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+			partition4@d0000 {
+				label = "DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+			partition5@e0000 {
+				label = "APPSBLENV"; /* uboot env*/
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+			partition5@f0000 {
+				label = "APPSBL"; /* uboot */
+				reg = <0x000f0000 0x00080000>;
+				read-only;
+			};
+			partition5@170000 {
+				label = "ART";
+				reg = <0x00170000 0x00010000>;
+				read-only;
+			};
+			/* 0x00180000 - 0x00200000 unused */
+		};
+	};
+
+	mt29f@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "spinand,mt29f";
+		reg = <1>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "ubi";
+				reg = <0x00000000 0x08000000>;
+			};
+		};
+	};
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts

@@ -0,0 +1,261 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "ZyXEL WRE6606";
+	compatible = "zyxel,wre6606", "qcom,ipq4019";
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	chosen {
+		bootargs-append = " mtdparts=";
+	};
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+			qcom,num_gmac = <1>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		wps {
+			label = "wre6606:green:wps";
+			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan5g_green {
+			label = "wre6606:green:wlan5g";
+			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		power: power {
+			label = "wre6606:green:power";
+			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan5g_red {
+			label = "wre6606:red:wlan5g";
+			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan2g_red {
+			label = "wre6606:red:wlan2g";
+			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan2g_green {
+			label = "wre6606:green:wlan2g";
+			gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	mx25l12805d@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+
+			partition1@40000 {
+				label = "MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+
+			partition2@60000 {
+				label = "QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+
+			partition3@c0000 {
+				label = "CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+
+			partition4@d0000 {
+				label = "DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+
+			partition5@E0000 {
+				label = "APPSBLENV";
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+
+			partition6@F0000 {
+				label = "APPSBL";
+				reg = <0x000f0000 0x00080000>;
+				read-only;
+			};
+
+			partition7@170000 {
+				label = "ART";
+				reg = <0x00170000 0x00010000>;
+				read-only;
+			};
+
+			partition8@180000 {
+				label = "firmware";
+				reg = <0x00180000 0x00ce0000>;
+			};
+
+			partition9@e60000 {
+				label = "manufacture";
+				reg = <0x00e60000 0x00050000>;
+				read-only;
+			};
+
+			partition10@eb0000 {
+				label = "storage";
+				reg = <0x00eb0000 0x00150000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-a62.dts

@@ -0,0 +1,240 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "OpenMesh A62";
+	compatible = "openmesh,a62", "qcom,ipq4019";
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@194b000 {
+			/* select hostmode */
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			switch_lan_bmp = <0x10>;
+			switch_wan_bmp = <0x20>;
+
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART >;
+		};
+	};
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		red {
+			label = "a62:red:status";
+			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-off";
+		};
+
+		power: green {
+			label = "a62:green:status";
+			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue {
+			label = "a62:blue:status";
+			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-off";
+		};
+	};
+
+	watchdog {
+		compatible = "linux,wdt-gpio";
+		gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+		hw_algo = "toggle";
+		/* hw_margin_ms is actually 300s but driver limits it to 60s */
+		hw_margin_ms = <60000>;
+		always-running;
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio16", "gpio17";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio13", "gpio14", "gpio15";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio12";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	enable-usb-power {
+		gpio-hog;
+		gpios = <58 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "enable USB2 power";
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		/* partitions are passed via bootloader */
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac0 {
+	qcom,phy_mdio_addr = <3>;
+	qcom,poll_required = <1>;
+	qcom,forced_speed = <1000>;
+	qcom,forced_duplex = <1>;
+	vlan_tag = <1 0x10>;
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+
+		ath10k@0,0 {
+			compatible = "qcom,ath10k";
+			status = "okay";
+			reg = <0 0 0 0 0>;
+			device_type = "pci";
+			qcom,ath10k-calibration-variant = "OM-A62";
+		};
+	};
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "OM-A62";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "OM-A62";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

@@ -0,0 +1,21 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

@@ -0,0 +1,177 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+	compatible = "qcom,ipq4019";
+
+	soc {
+		pinctrl@1000000 {
+			serial_0_pins: serial_pinmux {
+				mux {
+					pins = "gpio16", "gpio17";
+					function = "blsp_uart0";
+					bias-disable;
+				};
+			};
+
+			serial_1_pins: serial1_pinmux {
+				mux {
+					pins = "gpio8", "gpio9";
+					function = "blsp_uart1";
+					bias-disable;
+				};
+			};
+
+			spi_0_pins: spi_0_pinmux {
+				pinmux {
+					function = "blsp_spi0";
+					pins = "gpio13", "gpio14", "gpio15";
+				};
+				pinmux_cs {
+					function = "gpio";
+					pins = "gpio12";
+				};
+				pinconf {
+					pins = "gpio13", "gpio14", "gpio15";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				pinconf_cs {
+					pins = "gpio12";
+					drive-strength = <2>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			i2c_0_pins: i2c_0_pinmux {
+				pinmux {
+					function = "blsp_i2c0";
+					pins = "gpio10", "gpio11";
+				};
+				pinconf {
+					pins = "gpio10", "gpio11";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			nand_pins: nand_pins {
+
+				pullups {
+					pins = "gpio52", "gpio53", "gpio58",
+						"gpio59";
+					function = "qpic";
+					bias-pull-up;
+				};
+
+				pulldowns {
+					pins = "gpio54", "gpio55", "gpio56",
+						"gpio57", "gpio60", "gpio61",
+						"gpio62", "gpio63", "gpio64",
+						"gpio65", "gpio66", "gpio67",
+						"gpio68", "gpio69";
+					function = "qpic";
+					bias-pull-down;
+				};
+			};
+		};
+
+		blsp_dma: dma@7884000 {
+			status = "okay";
+		};
+
+		spi_0: spi@78b5000 {
+			pinctrl-0 = <&spi_0_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+			cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+			mx25l25635e@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0>;
+				compatible = "mx25l25635e";
+				spi-max-frequency = <24000000>;
+			};
+		};
+
+		i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+			pinctrl-0 = <&i2c_0_pins>;
+			pinctrl-names = "default";
+
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_0_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		serial@78b0000 {
+			pinctrl-0 = <&serial_1_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3_ss_phy: ssphy@9a000 {
+			status = "okay";
+		};
+
+		usb3_hs_phy: hsphy@a6000 {
+			status = "okay";
+		};
+
+		usb3: usb3@8af8800 {
+			status = "okay";
+		};
+
+		usb2_hs_phy: hsphy@a8000 {
+			status = "okay";
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+
+		cryptobam: dma@8e04000 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		qpic_bam: dma@7984000 {
+			status = "okay";
+		};
+
+		nand: qpic-nand@79b0000 {
+			pinctrl-0 = <&nand_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+	};
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts

@@ -0,0 +1,270 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
+ * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "Compex WPJ428";
+	compatible = "compex,wpj428", "qcom,ipq4019";
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@194b000 {
+			/* select hostmode */
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2: usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3: usb3@8af8800 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			switch_lan_bmp = <0x10>;
+			switch_wan_bmp = <0x20>;
+
+			status = "okay";
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	aliases {
+		led-boot = &status;
+		led-failsafe = &status;
+		led-upgrade = &status;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status: rss4 {
+			label = "wpj428:green:rss4";
+			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		rss3 {
+			label = "wpj428:green:rss3";
+			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	beeper: beeper {
+		compatible = "gpio-beeper";
+		gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pin {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pin_cs {
+			function = "gpio";
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition0@0 {
+				label = "0:SBL1";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition1@40000 {
+				label = "0:MIBIB";
+				reg = <0x00040000 0x00020000>;
+				read-only;
+			};
+			partition2@60000 {
+				label = "0:QSEE";
+				reg = <0x00060000 0x00060000>;
+				read-only;
+			};
+			partition3@c0000 {
+				label = "0:CDT";
+				reg = <0x000c0000 0x00010000>;
+				read-only;
+			};
+			partition4@d0000 {
+				label = "0:DDRPARAMS";
+				reg = <0x000d0000 0x00010000>;
+				read-only;
+			};
+			partition5@e0000 {
+				label = "0:APPSBLENV"; /* uboot env*/
+				reg = <0x000e0000 0x00010000>;
+				read-only;
+			};
+			partition5@f0000 {
+				label = "0:APPSBL"; /* uboot */
+				reg = <0x000f0000 0x00080000>;
+				read-only;
+			};
+			partition5@170000 {
+				label = "0:ART";
+				reg = <0x00170000 0x00010000>;
+				read-only;
+			};
+			partition6@180000 {
+				label = "firmware";
+				reg = <0x00180000 0x01e80000>;
+			};
+		};
+	};
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac0 {
+	qcom,phy_mdio_addr = <4>;
+	qcom,poll_required = <1>;
+	qcom,forced_speed = <1000>;
+	qcom,forced_duplex = <1>;
+	vlan_tag = <2 0x20>;
+};
+
+&gmac1 {
+	qcom,phy_mdio_addr = <3>;
+	qcom,poll_required = <1>;
+	qcom,forced_speed = <1000>;
+	qcom,forced_duplex = <1>;
+	vlan_tag = <1 0x10>;
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+};
+
+&wifi1 {
+	status = "okay";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts

@@ -0,0 +1,271 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "GL.iNet GL-B1300";
+	compatible = "glinet,gl-b1300", "qcom,ipq4019";
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+		};
+
+		ess-psgmii@98000 {
+			status = "okay";
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			/* select hostmode */
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+			status = "okay";
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		usb2@60f8800 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		usb3@8af8800 {
+			status = "okay";
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			status = "okay";
+			switch_lan_bmp = <0x18>;
+			switch_wan_bmp = <0x20>;
+		};
+
+		edma@c080000 {
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power: power {
+			label = "gl-b1300:green:power";
+			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		mesh {
+			label = "gl-b1300:green:mesh";
+			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		wlan {
+			label = "gl-b1300:green:wlan";
+			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+	mx25l25635f@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		SBL1@0 {
+			label = "SBL1";
+			reg = <0x0 0x40000>;
+			read-only;
+		};
+
+		MIBIB@40000 {
+			label = "MIBIB";
+			reg = <0x40000 0x20000>;
+			read-only;
+		};
+
+		QSEE@60000 {
+			label = "QSEE";
+			reg = <0x60000 0x60000>;
+			read-only;
+		};
+
+		CDT@c0000 {
+			label = "CDT";
+			reg = <0xc0000 0x10000>;
+			read-only;
+		};
+
+		DDRPARAMS@d0000 {
+			label = "DDRPARAMS";
+			reg = <0xd0000 0x10000>;
+			read-only;
+		};
+
+		APPSBLENV@e0000 {
+			label = "APPSBLENV";
+			reg = <0xe0000 0x10000>;
+			read-only;
+		};
+
+		APPSBL@f0000 {
+			label = "APPSBL";
+			reg = <0xf0000 0x80000>;
+			read-only;
+		};
+
+		ART@170000 {
+			label = "ART";
+			reg = <0x170000 0x10000>;
+			read-only;
+		};
+
+		firmware@180000 {
+			label = "firmware";
+			reg = <0x180000 0x1e80000>;
+		};
+	};
+};
+
+&tlmm {
+	serial_pins: serial_pinmux {
+		mux {
+			pins = "gpio60", "gpio61";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pinmux {
+		pinmux {
+			function = "blsp_spi0";
+			pins = "gpio55", "gpio56", "gpio57";
+		};
+		pinmux_cs {
+			function = "gpio";
+			pins = "gpio54";
+		};
+		pinconf {
+			pins = "gpio55", "gpio56", "gpio57";
+			drive-strength = <12>;
+			bias-disable;
+		};
+		pinconf_cs {
+			pins = "gpio54";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "GL-B1300";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "GL-B1300";
+};

target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4029-mr33.dts

@@ -0,0 +1,381 @@
+/*
+ * Device Tree Source for Meraki MR33 (Stinkbug)
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+#include "qcom-ipq4019.dtsi"
+#include "qcom-ipq4019-bus.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "Meraki MR33 Access Point";
+	compatible = "meraki,mr33", "qcom,ipq4019";
+
+	aliases {
+		led-boot = &status_green;
+		led-failsafe = &status_red;
+		led-running = &status_green;
+		led-upgrade = &power_orange;
+	};
+
+	/* Do we really need this defined? */
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		mdio@90000 {
+			status = "okay";
+			pinctrl-0 = <&mdio_pins>;
+			pinctrl-names = "default";
+			/delete-node/ ethernet-phy@0;
+			/delete-node/ ethernet-phy@2;
+			/delete-node/ ethernet-phy@3;
+			/delete-node/ ethernet-phy@4;
+		};
+
+		/* It is a 56-bit counter that supplies the count to the ARM arch
+		   timers and without upstream driver */
+		counter@4a1000 {
+			compatible = "qcom,qca-gcnt";
+			reg = <0x4a1000 0x4>;
+		};
+
+		ess_tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
+		};
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_0_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		serial@78b0000 {
+			pinctrl-0 = <&serial_1_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+
+			bluetooth {
+				compatible = "ti,cc2650";
+				enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+			};
+		};
+
+		crypto@8e3a000 {
+			status = "okay";
+		};
+
+		watchdog@b017000 {
+			status = "okay";
+		};
+
+		ess-switch@c000000 {
+			switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
+			switch_lan_bmp = <0x0>; /* lan port bitmap */
+			switch_wan_bmp = <0x10>; /* wan port bitmap */
+		};
+
+		edma@c080000 {
+			qcom,single-phy;
+			qcom,num_gmac = <1>;
+			phy-mode = "rgmii-rxid";
+			status = "okay";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_orange: power {
+			label = "mr33:orange:power";
+			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
+			panic-indicator;
+		};
+	};
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&gmac0 {
+	qcom,phy_mdio_addr = <1>;
+	qcom,poll_required = <1>;
+	vlan_tag = <0 0x20>;
+};
+
+&i2c_0 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	at24@50 {
+		compatible = "atmel,24c64";
+		pagesize = <32>;
+		reg = <0x50>;
+		read-only; /* This holds our MAC & Meraki board-data */
+	};
+};
+
+&i2c_1 {
+	pinctrl-0 = <&i2c_1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	lp5562@30 {
+		enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+		compatible = "ti,lp5562";
+		clock-mode = /bits/8 <2>;
+		reg = <0x30>;
+
+		/* RGB led */
+		status_red: chan0 {
+			chan-name = "mr33:red:status";
+			led-cur = /bits/ 8 <0x20>;
+			max-cur = /bits/ 8 <0x60>;
+		};
+
+		status_green: chan1 {
+			chan-name = "mr33:green:status";
+			led-cur = /bits/ 8 <0x20>;
+			max-cur = /bits/ 8 <0x60>;
+		};
+
+		chan2 {
+			chan-name = "mr33:blue:status";
+			led-cur = /bits/ 8 <0x20>;
+			max-cur = /bits/ 8 <0x60>;
+		};
+
+		chan3 {
+			chan-name = "mr33:white:status";
+			led-cur = /bits/ 8 <0x20>;
+			max-cur = /bits/ 8 <0x60>;
+		};
+	};
+};
+
+&nand {
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	nand@0 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "sbl1";
+				reg = <0x000000000000 0x000000100000>;
+				read-only;
+			};
+			partition@1 {
+				label = "mibib";
+				reg = <0x000000100000 0x000000100000>;
+				read-only;
+			};
+			partition@2 {
+				label = "bootconfig";
+				reg = <0x000000200000 0x000000100000>;
+				read-only;
+			};
+			partition@3 {
+				label = "qsee";
+				reg = <0x000000300000 0x000000100000>;
+				read-only;
+			};
+			partition@4 {
+				label = "qsee_alt";
+				reg = <0x000000400000 0x000000100000>;
+				read-only;
+			};
+			partition@5 {
+				label = "cdt";
+				reg = <0x000000500000 0x000000080000>;
+				read-only;
+			};
+			partition@6 {
+				label = "cdt_alt";
+				reg = <0x000000580000 0x000000080000>;
+				read-only;
+			};
+			partition@7 {
+				label = "ddrparams";
+				reg = <0x000000600000 0x000000080000>;
+				read-only;
+			};
+			partition@8 {
+				label = "u-boot";
+				reg = <0x000000700000 0x000000200000>;
+				read-only;
+			};
+			partition@9 {
+				label = "u-boot-backup";
+				reg = <0x000000900000 0x000000200000>;
+				read-only;
+			};
+			partition@10 {
+				label = "ART";
+				reg = <0x000000b00000 0x000000080000>;
+				read-only;
+			};
+			partition@11 {
+				label = "ubi";
+				reg = <0x000000c00000 0x000007000000>;
+			};
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&tlmm {
+	/*
+	 * GPIO43 should be 0/1 whenever the unit is
+	 * powered through PoE or AC-Adapter.
+	 * That said, playing with this seems to
+	 * reset the AP.
+	 */
+
+	mdio_pins: mdio_pinmux {
+		mux_1 {
+			pins = "gpio6";
+			function = "mdio";
+			bias-pull-up;
+		};
+		mux_2 {
+			pins = "gpio7";
+			function = "mdc";
+			bias-pull-up;
+		};
+	};
+
+	serial_0_pins: serial_pinmux {
+		mux {
+			pins = "gpio16", "gpio17";
+			function = "blsp_uart0";
+			bias-disable;
+		};
+	};
+
+	serial_1_pins: serial1_pinmux {
+		mux {
+			/* We use the i2c-0 pins for serial_1 */
+			pins = "gpio8", "gpio9";
+			function = "blsp_uart1";
+			bias-disable;
+		};
+	};
+
+	i2c_0_pins: i2c_0_pinmux {
+		pinmux {
+			function = "blsp_i2c0";
+			pins = "gpio20", "gpio21";
+		};
+		pinconf {
+			pins = "gpio20", "gpio21";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c_1_pins: i2c_1_pinmux {
+		pinmux {
+			function = "blsp_i2c1";
+			pins = "gpio34", "gpio35";
+		};
+		pinconf {
+			pins = "gpio34", "gpio35";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	nand_pins: nand_pins {
+		/*
+		 * There are 18 pins. 15 pins are common between LCD and NAND.
+		 * The QPIC controller arbitrates between LCD and NAND. Of the
+		 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
+		 *
+		 * The meraki source hints that the bluetooth module claims
+		 * pin 52 as well. But sadly, there's no data whenever this
+		 * is a NAND or LCD exclusive pin or not.
+		 */
+
+		pullups {
+			pins = "gpio52", "gpio53", "gpio58",
+				"gpio59";
+			function = "qpic";
+			bias-pull-up;
+		};
+
+		pulldowns {
+			pins = "gpio54", "gpio55", "gpio56",
+				"gpio57", "gpio60", "gpio61",
+				"gpio62", "gpio63", "gpio64",
+				"gpio65", "gpio66", "gpio67",
+				"gpio68", "gpio69";
+			function = "qpic";
+			bias-pull-down;
+		};
+	};
+};
+
+&wifi0 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "Meraki-MR33";
+};
+
+&wifi1 {
+	status = "okay";
+	qcom,ath10k-calibration-variant = "Meraki-MR33";
+};

target/linux/ipq40xx/image/Makefile

@@ -0,0 +1,219 @@
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+define Device/Default
+	PROFILES := Default
+	KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
+	KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs
+	KERNEL_PREFIX := $$(IMAGE_PREFIX)
+	KERNEL_LOADADDR := 0x80208000
+	SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
+	IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
+	IMAGE/sysupgrade.bin/squashfs :=
+endef
+
+define Device/FitImage
+	KERNEL_SUFFIX := -fit-uImage.itb
+	KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/FitImageLzma
+	KERNEL_SUFFIX := -fit-uImage.itb
+	KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+endef
+
+define Device/UbiFit
+	KERNEL_IN_UBI := 1
+	IMAGES := nand-factory.ubi nand-sysupgrade.bin
+	IMAGE/nand-factory.ubi := append-ubi
+	IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+
+define Device/DniImage
+	KERNEL_SUFFIX := -fit-uImage.itb
+	KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+	KERNEL_NAME := Image
+	NETGEAR_BOARD_ID :=
+	NETGEAR_HW_ID :=
+	IMAGES := factory.img sysupgrade.bin
+	IMAGE/factory.img := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | netgear-dni
+	IMAGE/sysupgrade.bin := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata
+endef
+DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
+
+
+define Device/8dev_jalapeno
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_DTS := qcom-ipq4018-jalapeno
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_TITLE := 8devices Jalapeno
+endef
+TARGET_DEVICES += 8dev_jalapeno
+
+define Device/asus_rt-ac58u
+	$(call Device/FitImageLzma)
+	DEVICE_DTS := qcom-ipq4018-rt-ac58u
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DTB_SIZE := 65536
+	DEVICE_TITLE := Asus RT-AC58U
+	IMAGE_SIZE := 20439364
+	FILESYSTEMS := squashfs
+#	Someone - in their infinite wisdom - decided to put the firmware
+#	version in front of the image name \03\00\00\04 => Version 3.0.0.4
+#	Since u-boot works with strings we either need another fixup step
+#	to add a version... or we are very careful not to add '\0' into that
+#	string and call it a day.... Yeah, we do the latter!
+	UIMAGE_NAME:=$(shell echo -e '\03\01\01\01RT-AC58U')
+	IMAGES := sysupgrade.bin
+	DEVICE_PACKAGES := kmod-usb-ledtrig-usbport
+endef
+TARGET_DEVICES += asus_rt-ac58u
+
+define Device/avm_fritzbox-4040
+	$(call Device/FitImageLzma)
+	DEVICE_DTS := qcom-ipq4018-fritz4040
+	BOARD_NAME := fritz4040
+	DEVICE_TITLE := AVM Fritz!Box 4040
+	IMAGE_SIZE := 29753344
+	UBOOT_PATH := $(STAGING_DIR_IMAGE)/uboot-fritz4040.bin
+	UBOOT_PARTITION_SIZE := 524288
+	IMAGES = eva.bin sysupgrade.bin
+	IMAGE/eva.bin := append-uboot | pad-to $$$$(UBOOT_PARTITION_SIZE) | append-kernel | append-rootfs | pad-rootfs
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+	DEVICE_PACKAGES := fritz-tffs fritz-caldata
+endef
+TARGET_DEVICES += avm_fritzbox-4040
+
+define Device/compex_wpj428
+	$(call Device/FitImage)
+	DEVICE_DTS := qcom-ipq4028-wpj428
+	DEVICE_DTS_CONFIG := config@4
+	BLOCKSIZE := 64k
+	DEVICE_TITLE := Compex WPJ428
+	IMAGE_SIZE := 31232k
+	KERNEL_SIZE := 4096k
+	IMAGES = sysupgrade.bin
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+	DEVICE_PACKAGES := kmod-gpio-beeper
+endef
+TARGET_DEVICES += compex_wpj428
+
+define Device/glinet_gl-b1300
+	$(call Device/FitImage)
+	DEVICE_TITLE := GL.iNet GL-B1300
+	BOARD_NAME := gl-b1300
+	DEVICE_DTS := qcom-ipq4029-gl-b1300
+	KERNEL_SIZE := 4096k
+	IMAGE_SIZE := 26624k
+	IMAGES := sysupgrade.bin
+	IMAGE/sysupgrade.bin := append-kernel |append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += glinet_gl-b1300
+
+define Device/meraki_mr33
+	$(call Device/FitImage)
+	DEVICE_DTS := qcom-ipq4029-mr33
+	BLOCKSIZE := 131072
+	PAGESIZE := 2048
+	DEVICE_TITLE := Cisco Meraki MR33
+	IMAGES = sysupgrade.bin
+	DEVICE_PACKAGES := -swconfig ath10k-firmware-qca9887
+endef
+TARGET_DEVICES += meraki_mr33
+
+define Device/netgear_ex61x0v2
+	$(call Device/DniImage)
+	KERNEL_SIZE := 3080192
+	DEVICE_DTS_CONFIG := config@4
+	NETGEAR_BOARD_ID := EX6150v2series
+	NETGEAR_HW_ID := 29765285+16+0+128+2x2
+endef
+
+define Device/netgear_ex6100v2
+	$(call Device/netgear_ex61x0v2)
+	DEVICE_DTS := qcom-ipq4018-ex6100v2
+	DEVICE_TITLE := Netgear EX6100v2
+endef
+TARGET_DEVICES += netgear_ex6100v2
+
+define Device/netgear_ex6150v2
+	$(call Device/netgear_ex61x0v2)
+	DEVICE_DTS := qcom-ipq4018-ex6150v2
+	DEVICE_TITLE := Netgear EX6150v2
+endef
+TARGET_DEVICES += netgear_ex6150v2
+
+define Device/openmesh_a42
+	$(call Device/FitImageLzma)
+	DEVICE_DTS := qcom-ipq4018-a42
+	DEVICE_DTS_CONFIG := config@om.a42
+	BLOCKSIZE := 64k
+	DEVICE_TITLE := OpenMesh A42
+	KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
+	IMAGE_SIZE := 15616k
+	IMAGES = factory.bin sysupgrade.bin
+	IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
+	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
+	DEVICE_PACKAGES := uboot-envtools
+endef
+TARGET_DEVICES += openmesh_a42
+
+define Device/openmesh_a62
+	$(call Device/FitImageLzma)
+	DEVICE_DTS := qcom-ipq4019-a62
+	DEVICE_DTS_CONFIG := config@om.a62
+	BLOCKSIZE := 64k
+	DEVICE_TITLE := OpenMesh A62
+	KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
+	IMAGE_SIZE := 15552k
+	IMAGES = factory.bin sysupgrade.bin
+	IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A62
+	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
+	DEVICE_PACKAGES := ath10k-firmware-qca9888 uboot-envtools
+endef
+
+TARGET_DEVICES += openmesh_a62
+
+define Device/qcom_ap-dk01.1-c1
+	DEVICE_TITLE := QCA AP-DK01.1-C1
+	BOARD_NAME := ap-dk01.1-c1
+	DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
+	KERNEL_INSTALL := 1
+	KERNEL_SIZE := 4096k
+	IMAGE_SIZE := 26624k
+	$(call Device/FitImage)
+	IMAGES := sysupgrade.bin
+	IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += qcom_ap-dk01.1-c1
+
+define Device/qcom_ap-dk04.1-c1
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
+	KERNEL_INSTALL := 1
+	KERNEL_SIZE := 4048k
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := ap-dk04.1-c1
+	DEVICE_TITLE := QCA AP-DK04.1-C1
+endef
+TARGET_DEVICES += qcom_ap-dk04.1-c1
+
+define Device/zyxel_wre6606
+	$(call Device/FitImage)
+	DEVICE_TITLE := ZyXEL WRE6606
+	DEVICE_DTS_CONFIG := config@4
+	DEVICE_DTS := qcom-ipq4018-wre6606
+	DEVICE_PACKAGES := ipq-wifi-zyxel_wre6606
+	IMAGES := sysupgrade.bin
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += zyxel_wre6606
+
+$(eval $(call BuildImage))

target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch

@@ -0,0 +1,77 @@
+From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Thu, 17 Mar 2016 15:01:09 -0500
+Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
+ support
+
+This adds some operating points for cpu frequeny scaling
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -40,14 +40,7 @@
+ 			reg = <0x0>;
+ 			clocks = <&gcc GCC_APPS_CLK_SRC>;
+ 			clock-frequency = <0>;
+-			operating-points = <
+-				/* kHz	uV (fixed) */
+-				48000	1100000
+-				200000	1100000
+-				500000	1100000
+-				666000	1100000
+-			>;
+-			clock-latency = <256000>;
++			operating-points-v2 = <&cpu0_opp_table>;
+ 		};
+ 
+ 		cpu@1 {
+@@ -59,6 +52,7 @@
+ 			reg = <0x1>;
+ 			clocks = <&gcc GCC_APPS_CLK_SRC>;
+ 			clock-frequency = <0>;
++			operating-points-v2 = <&cpu0_opp_table>;
+ 		};
+ 
+ 		cpu@2 {
+@@ -70,6 +64,7 @@
+ 			reg = <0x2>;
+ 			clocks = <&gcc GCC_APPS_CLK_SRC>;
+ 			clock-frequency = <0>;
++			operating-points-v2 = <&cpu0_opp_table>;
+ 		};
+ 
+ 		cpu@3 {
+@@ -81,6 +76,29 @@
+ 			reg = <0x3>;
+ 			clocks = <&gcc GCC_APPS_CLK_SRC>;
+ 			clock-frequency = <0>;
++			operating-points-v2 = <&cpu0_opp_table>;
++		};
++	};
++
++	cpu0_opp_table: opp_table0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-48000000 {
++			opp-hz = /bits/ 64 <48000000>;
++			clock-latency-ns = <256000>;
++		};
++		opp-200000000 {
++			opp-hz = /bits/ 64 <200000000>;
++			clock-latency-ns = <256000>;
++		};
++		opp-500000000 {
++			opp-hz = /bits/ 64 <500000000>;
++			clock-latency-ns = <256000>;
++		};
++		opp-716000000 {
++			opp-hz = /bits/ 64 <716000000>;
++			clock-latency-ns = <256000>;
+ 		};
+ 	};
+ 

target/linux/ipq40xx/patches-4.14/030-mtd-nand-Use-standard-large-page-OOB-layout-when-usi.patch

@@ -0,0 +1,47 @@
+From 882fd1577cbe7812ae3a48988180c5f0fda475ca Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Sat, 26 Aug 2017 17:19:15 +0200
+Subject: [PATCH] mtd: nand: Use standard large page OOB layout when using
+ NAND_ECC_NONE
+
+Use the core's large page OOB layout functions when not reserving any
+space for ECC bytes in the OOB layout. Fix ->nand_ooblayout_ecc_lp()
+to return -ERANGE instead of a zero length in this case.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/nand_base.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -115,7 +115,7 @@ static int nand_ooblayout_ecc_lp(struct
+ 	struct nand_chip *chip = mtd_to_nand(mtd);
+ 	struct nand_ecc_ctrl *ecc = &chip->ecc;
+ 
+-	if (section)
++	if (section || !ecc->total)
+ 		return -ERANGE;
+ 
+ 	oobregion->length = ecc->total;
+@@ -4712,6 +4712,19 @@ int nand_scan_tail(struct mtd_info *mtd)
+ 			mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
+ 			break;
+ 		default:
++			/*
++			 * Expose the whole OOB area to users if ECC_NONE
++			 * is passed. We could do that for all kind of
++			 * ->oobsize, but we must keep the old large/small
++			 * page with ECC layout when ->oobsize <= 128 for
++			 * compatibility reasons.
++			 */
++			if (ecc->mode == NAND_ECC_NONE) {
++				mtd_set_ooblayout(mtd,
++						&nand_ooblayout_lp_ops);
++				break;
++			}
++
+ 			WARN(1, "No oob scheme defined for oobsize %d\n",
+ 				mtd->oobsize);
+ 			ret = -EINVAL;

target/linux/ipq40xx/patches-4.14/031-mtd-nand-use-usual-return-values-for-the-erase-hook.patch

@@ -0,0 +1,48 @@
+From eb94555e9e97c9983461214046b4d72c4ab4ba70 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@free-electrons.com>
+Date: Thu, 30 Nov 2017 18:01:28 +0100
+Subject: [PATCH] mtd: nand: use usual return values for the ->erase() hook
+
+Avoid using specific defined values for checking returned status of the
+->erase() hook. Instead, use usual negative error values on failure,
+zero otherwise.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/denali.c    |  2 +-
+ drivers/mtd/nand/docg4.c     |  7 ++++++-
+ drivers/mtd/nand/nand_base.c | 10 ++++++++--
+ 3 files changed, 15 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -2994,11 +2994,17 @@ out:
+ static int single_erase(struct mtd_info *mtd, int page)
+ {
+ 	struct nand_chip *chip = mtd_to_nand(mtd);
++	int status;
++
+ 	/* Send commands to erase a block */
+ 	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ 	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+ 
+-	return chip->waitfunc(mtd, chip);
++	status = chip->waitfunc(mtd, chip);
++	if (status < 0)
++		return status;
++
++	return status & NAND_STATUS_FAIL ? -EIO : 0;
+ }
+ 
+ /**
+@@ -3082,7 +3088,7 @@ int nand_erase_nand(struct mtd_info *mtd
+ 		status = chip->erase(mtd, page & chip->pagemask);
+ 
+ 		/* See if block erase succeeded */
+-		if (status & NAND_STATUS_FAIL) {
++		if (status) {
+ 			pr_debug("%s: failed erase, page 0x%08x\n",
+ 					__func__, page);
+ 			instr->state = MTD_ERASE_FAILED;

target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch

@@ -0,0 +1,409 @@
+From 6b4faeac05bc0b91616b921191cb054d1376f3b4 Mon Sep 17 00:00:00 2001
+From: Sricharan R <sricharan@codeaurora.org>
+Date: Mon, 28 Aug 2017 20:30:24 +0530
+Subject: [PATCH] dmaengine: qcom-bam: Process multiple pending descriptors
+
+The bam dmaengine has a circular FIFO to which we
+add hw descriptors that describes the transaction.
+The FIFO has space for about 4096 hw descriptors.
+
+Currently we add one descriptor and wait for it to
+complete with interrupt and then add the next pending
+descriptor. In this way, the FIFO is underutilized
+since only one descriptor is processed at a time, although
+there is space in FIFO for the BAM to process more.
+
+Instead keep adding descriptors to FIFO till its full,
+that allows BAM to continue to work on the next descriptor
+immediately after signalling completion interrupt for the
+previous descriptor.
+
+Also when the client has not set the DMA_PREP_INTERRUPT for
+a descriptor, then do not configure BAM to trigger a interrupt
+upon completion of that descriptor. This way we get a interrupt
+only for the descriptor for which DMA_PREP_INTERRUPT was
+requested and there signal completion of all the previous completed
+descriptors. So we still do callbacks for all requested descriptors,
+but just that the number of interrupts are reduced.
+
+CURRENT:
+
+            ------      -------   ---------------
+            |DES 0|     |DESC 1|  |DESC 2 + INT |
+            ------      -------   ---------------
+               |           |            |
+               |           |            |
+INTERRUPT:   (INT)       (INT)	      (INT)
+CALLBACK:     (CB)        (CB)         (CB)
+
+		MTD_SPEEDTEST READ PAGE: 3560 KiB/s
+		MTD_SPEEDTEST WRITE PAGE: 2664 KiB/s
+		IOZONE READ: 2456 KB/s
+		IOZONE WRITE: 1230 KB/s
+
+	bam dma interrupts (after tests): 96508
+
+CHANGE:
+
+        ------  -------    -------------
+        |DES 0| |DESC 1   |DESC 2 + INT |
+        ------  -------   --------------
+				|
+				|
+          		      (INT)
+			      (CB for 0, 1, 2)
+
+		MTD_SPEEDTEST READ PAGE: 3860 KiB/s
+		MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s
+		IOZONE READ: 2677 KB/s
+		IOZONE WRITE: 1308 KB/s
+
+	bam dma interrupts (after tests): 58806
+
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Reviewed-by: Andy Gross <andy.gross@linaro.org>
+Tested-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+---
+ drivers/dma/qcom/bam_dma.c | 169 +++++++++++++++++++++++++++++----------------
+ 1 file changed, 109 insertions(+), 60 deletions(-)
+
+--- a/drivers/dma/qcom/bam_dma.c
++++ b/drivers/dma/qcom/bam_dma.c
+@@ -46,6 +46,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_dma.h>
++#include <linux/circ_buf.h>
+ #include <linux/clk.h>
+ #include <linux/dmaengine.h>
+ #include <linux/pm_runtime.h>
+@@ -78,6 +79,8 @@ struct bam_async_desc {
+ 
+ 	struct bam_desc_hw *curr_desc;
+ 
++	/* list node for the desc in the bam_chan list of descriptors */
++	struct list_head desc_node;
+ 	enum dma_transfer_direction dir;
+ 	size_t length;
+ 	struct bam_desc_hw desc[0];
+@@ -347,6 +350,8 @@ static const struct reg_offset_data bam_
+ #define BAM_DESC_FIFO_SIZE	SZ_32K
+ #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
+ #define BAM_FIFO_SIZE	(SZ_32K - 8)
++#define IS_BUSY(chan)	(CIRC_SPACE(bchan->tail, bchan->head,\
++			 MAX_DESCRIPTORS + 1) == 0)
+ 
+ struct bam_chan {
+ 	struct virt_dma_chan vc;
+@@ -356,8 +361,6 @@ struct bam_chan {
+ 	/* configuration from device tree */
+ 	u32 id;
+ 
+-	struct bam_async_desc *curr_txd;	/* current running dma */
+-
+ 	/* runtime configuration */
+ 	struct dma_slave_config slave;
+ 
+@@ -372,6 +375,8 @@ struct bam_chan {
+ 	unsigned int initialized;	/* is the channel hw initialized? */
+ 	unsigned int paused;		/* is the channel paused? */
+ 	unsigned int reconfigure;	/* new slave config? */
++	/* list of descriptors currently processed */
++	struct list_head desc_list;
+ 
+ 	struct list_head node;
+ };
+@@ -540,7 +545,7 @@ static void bam_free_chan(struct dma_cha
+ 
+ 	vchan_free_chan_resources(to_virt_chan(chan));
+ 
+-	if (bchan->curr_txd) {
++	if (!list_empty(&bchan->desc_list)) {
+ 		dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
+ 		goto err;
+ 	}
+@@ -633,8 +638,6 @@ static struct dma_async_tx_descriptor *b
+ 
+ 	if (flags & DMA_PREP_INTERRUPT)
+ 		async_desc->flags |= DESC_FLAG_EOT;
+-	else
+-		async_desc->flags |= DESC_FLAG_INT;
+ 
+ 	async_desc->num_desc = num_alloc;
+ 	async_desc->curr_desc = async_desc->desc;
+@@ -685,28 +688,16 @@ err_out:
+ static int bam_dma_terminate_all(struct dma_chan *chan)
+ {
+ 	struct bam_chan *bchan = to_bam_chan(chan);
++	struct bam_async_desc *async_desc, *tmp;
+ 	unsigned long flag;
+ 	LIST_HEAD(head);
+ 
+ 	/* remove all transactions, including active transaction */
+ 	spin_lock_irqsave(&bchan->vc.lock, flag);
+-	/*
+-	 * If we have transactions queued, then some might be committed to the
+-	 * hardware in the desc fifo.  The only way to reset the desc fifo is
+-	 * to do a hardware reset (either by pipe or the entire block).
+-	 * bam_chan_init_hw() will trigger a pipe reset, and also reinit the
+-	 * pipe.  If the pipe is left disabled (default state after pipe reset)
+-	 * and is accessed by a connected hardware engine, a fatal error in
+-	 * the BAM will occur.  There is a small window where this could happen
+-	 * with bam_chan_init_hw(), but it is assumed that the caller has
+-	 * stopped activity on any attached hardware engine.  Make sure to do
+-	 * this first so that the BAM hardware doesn't cause memory corruption
+-	 * by accessing freed resources.
+-	 */
+-	if (bchan->curr_txd) {
+-		bam_chan_init_hw(bchan, bchan->curr_txd->dir);
+-		list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued);
+-		bchan->curr_txd = NULL;
++	list_for_each_entry_safe(async_desc, tmp,
++				&bchan->desc_list, desc_node) {
++		list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
++		list_del(&async_desc->desc_node);
+ 	}
+ 
+ 	vchan_get_all_descriptors(&bchan->vc, &head);
+@@ -778,9 +769,9 @@ static int bam_resume(struct dma_chan *c
+  */
+ static u32 process_channel_irqs(struct bam_device *bdev)
+ {
+-	u32 i, srcs, pipe_stts;
++	u32 i, srcs, pipe_stts, offset, avail;
+ 	unsigned long flags;
+-	struct bam_async_desc *async_desc;
++	struct bam_async_desc *async_desc, *tmp;
+ 
+ 	srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
+ 
+@@ -800,27 +791,40 @@ static u32 process_channel_irqs(struct b
+ 		writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
+ 
+ 		spin_lock_irqsave(&bchan->vc.lock, flags);
+-		async_desc = bchan->curr_txd;
+ 
+-		if (async_desc) {
+-			async_desc->num_desc -= async_desc->xfer_len;
+-			async_desc->curr_desc += async_desc->xfer_len;
+-			bchan->curr_txd = NULL;
++		offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
++				       P_SW_OFSTS_MASK;
++		offset /= sizeof(struct bam_desc_hw);
++
++		/* Number of bytes available to read */
++		avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
++
++		list_for_each_entry_safe(async_desc, tmp,
++					 &bchan->desc_list, desc_node) {
++			/* Not enough data to read */
++			if (avail < async_desc->xfer_len)
++				break;
+ 
+ 			/* manage FIFO */
+ 			bchan->head += async_desc->xfer_len;
+ 			bchan->head %= MAX_DESCRIPTORS;
+ 
++			async_desc->num_desc -= async_desc->xfer_len;
++			async_desc->curr_desc += async_desc->xfer_len;
++			avail -= async_desc->xfer_len;
++
+ 			/*
+-			 * if complete, process cookie.  Otherwise
++			 * if complete, process cookie. Otherwise
+ 			 * push back to front of desc_issued so that
+ 			 * it gets restarted by the tasklet
+ 			 */
+-			if (!async_desc->num_desc)
++			if (!async_desc->num_desc) {
+ 				vchan_cookie_complete(&async_desc->vd);
+-			else
++			} else {
+ 				list_add(&async_desc->vd.node,
+-					&bchan->vc.desc_issued);
++					 &bchan->vc.desc_issued);
++			}
++			list_del(&async_desc->desc_node);
+ 		}
+ 
+ 		spin_unlock_irqrestore(&bchan->vc.lock, flags);
+@@ -882,6 +886,7 @@ static enum dma_status bam_tx_status(str
+ 		struct dma_tx_state *txstate)
+ {
+ 	struct bam_chan *bchan = to_bam_chan(chan);
++	struct bam_async_desc *async_desc;
+ 	struct virt_dma_desc *vd;
+ 	int ret;
+ 	size_t residue = 0;
+@@ -897,11 +902,17 @@ static enum dma_status bam_tx_status(str
+ 
+ 	spin_lock_irqsave(&bchan->vc.lock, flags);
+ 	vd = vchan_find_desc(&bchan->vc, cookie);
+-	if (vd)
++	if (vd) {
+ 		residue = container_of(vd, struct bam_async_desc, vd)->length;
+-	else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie)
+-		for (i = 0; i < bchan->curr_txd->num_desc; i++)
+-			residue += bchan->curr_txd->curr_desc[i].size;
++	} else {
++		list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
++			if (async_desc->vd.tx.cookie != cookie)
++				continue;
++
++			for (i = 0; i < async_desc->num_desc; i++)
++				residue += async_desc->curr_desc[i].size;
++		}
++	}
+ 
+ 	spin_unlock_irqrestore(&bchan->vc.lock, flags);
+ 
+@@ -942,63 +953,86 @@ static void bam_start_dma(struct bam_cha
+ {
+ 	struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
+ 	struct bam_device *bdev = bchan->bdev;
+-	struct bam_async_desc *async_desc;
++	struct bam_async_desc *async_desc = NULL;
+ 	struct bam_desc_hw *desc;
+ 	struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
+ 					sizeof(struct bam_desc_hw));
+ 	int ret;
++	unsigned int avail;
++	struct dmaengine_desc_callback cb;
+ 
+ 	lockdep_assert_held(&bchan->vc.lock);
+ 
+ 	if (!vd)
+ 		return;
+ 
+-	list_del(&vd->node);
+-
+-	async_desc = container_of(vd, struct bam_async_desc, vd);
+-	bchan->curr_txd = async_desc;
+-
+ 	ret = pm_runtime_get_sync(bdev->dev);
+ 	if (ret < 0)
+ 		return;
+ 
+-	/* on first use, initialize the channel hardware */
+-	if (!bchan->initialized)
+-		bam_chan_init_hw(bchan, async_desc->dir);
+-
+-	/* apply new slave config changes, if necessary */
+-	if (bchan->reconfigure)
+-		bam_apply_new_config(bchan, async_desc->dir);
++	while (vd && !IS_BUSY(bchan)) {
++		list_del(&vd->node);
+ 
+-	desc = bchan->curr_txd->curr_desc;
++		async_desc = container_of(vd, struct bam_async_desc, vd);
+ 
+-	if (async_desc->num_desc > MAX_DESCRIPTORS)
+-		async_desc->xfer_len = MAX_DESCRIPTORS;
+-	else
+-		async_desc->xfer_len = async_desc->num_desc;
++		/* on first use, initialize the channel hardware */
++		if (!bchan->initialized)
++			bam_chan_init_hw(bchan, async_desc->dir);
+ 
+-	/* set any special flags on the last descriptor */
+-	if (async_desc->num_desc == async_desc->xfer_len)
+-		desc[async_desc->xfer_len - 1].flags |=
+-					cpu_to_le16(async_desc->flags);
+-	else
+-		desc[async_desc->xfer_len - 1].flags |=
+-					cpu_to_le16(DESC_FLAG_INT);
++		/* apply new slave config changes, if necessary */
++		if (bchan->reconfigure)
++			bam_apply_new_config(bchan, async_desc->dir);
++
++		desc = async_desc->curr_desc;
++		avail = CIRC_SPACE(bchan->tail, bchan->head,
++				   MAX_DESCRIPTORS + 1);
++
++		if (async_desc->num_desc > avail)
++			async_desc->xfer_len = avail;
++		else
++			async_desc->xfer_len = async_desc->num_desc;
+ 
+-	if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
+-		u32 partial = MAX_DESCRIPTORS - bchan->tail;
++		/* set any special flags on the last descriptor */
++		if (async_desc->num_desc == async_desc->xfer_len)
++			desc[async_desc->xfer_len - 1].flags |=
++						cpu_to_le16(async_desc->flags);
+ 
+-		memcpy(&fifo[bchan->tail], desc,
+-				partial * sizeof(struct bam_desc_hw));
+-		memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) *
++		vd = vchan_next_desc(&bchan->vc);
++
++		dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
++
++		/*
++		 * An interrupt is generated at this desc, if
++		 *  - FIFO is FULL.
++		 *  - No more descriptors to add.
++		 *  - If a callback completion was requested for this DESC,
++		 *     In this case, BAM will deliver the completion callback
++		 *     for this desc and continue processing the next desc.
++		 */
++		if (((avail <= async_desc->xfer_len) || !vd ||
++		     dmaengine_desc_callback_valid(&cb)) &&
++		    !(async_desc->flags & DESC_FLAG_EOT))
++			desc[async_desc->xfer_len - 1].flags |=
++				cpu_to_le16(DESC_FLAG_INT);
++
++		if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
++			u32 partial = MAX_DESCRIPTORS - bchan->tail;
++
++			memcpy(&fifo[bchan->tail], desc,
++			       partial * sizeof(struct bam_desc_hw));
++			memcpy(fifo, &desc[partial],
++			       (async_desc->xfer_len - partial) *
+ 				sizeof(struct bam_desc_hw));
+-	} else {
+-		memcpy(&fifo[bchan->tail], desc,
+-			async_desc->xfer_len * sizeof(struct bam_desc_hw));
+-	}
++		} else {
++			memcpy(&fifo[bchan->tail], desc,
++			       async_desc->xfer_len *
++			       sizeof(struct bam_desc_hw));
++		}
+ 
+-	bchan->tail += async_desc->xfer_len;
+-	bchan->tail %= MAX_DESCRIPTORS;
++		bchan->tail += async_desc->xfer_len;
++		bchan->tail %= MAX_DESCRIPTORS;
++		list_add_tail(&async_desc->desc_node, &bchan->desc_list);
++	}
+ 
+ 	/* ensure descriptor writes and dma start not reordered */
+ 	wmb();
+@@ -1027,7 +1061,7 @@ static void dma_tasklet(unsigned long da
+ 		bchan = &bdev->channels[i];
+ 		spin_lock_irqsave(&bchan->vc.lock, flags);
+ 
+-		if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd)
++		if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
+ 			bam_start_dma(bchan);
+ 		spin_unlock_irqrestore(&bchan->vc.lock, flags);
+ 	}
+@@ -1048,7 +1082,7 @@ static void bam_issue_pending(struct dma
+ 	spin_lock_irqsave(&bchan->vc.lock, flags);
+ 
+ 	/* if work pending and idle, start a transaction */
+-	if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd)
++	if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
+ 		bam_start_dma(bchan);
+ 
+ 	spin_unlock_irqrestore(&bchan->vc.lock, flags);
+@@ -1152,6 +1186,7 @@ static void bam_channel_init(struct bam_
+ 
+ 	vchan_init(&bchan->vc, &bdev->common);
+ 	bchan->vc.desc_free = bam_dma_free_desc;
++	INIT_LIST_HEAD(&bchan->desc_list);
+ }
+ 
+ static const struct of_device_id bam_of_match[] = {

target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch

@@ -0,0 +1,89 @@
+From 8c4cdce8b1ab044a2ee1d86d5a086f67e32b3c10 Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Mon, 25 Sep 2017 13:21:25 +0530
+Subject: [PATCH 2/7] mtd: nand: qcom: add command elements in BAM transaction
+
+All the QPIC register read/write through BAM DMA requires
+command descriptor which contains the array of command elements.
+
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 19 ++++++++++++++++++-
+ 1 file changed, 18 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -22,6 +22,7 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/delay.h>
++#include <linux/dma/qcom_bam_dma.h>
+ 
+ /* NANDc reg offsets */
+ #define	NAND_FLASH_CMD			0x00
+@@ -199,6 +200,7 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  */
+ #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
+ 
++#define QPIC_PER_CW_CMD_ELEMENTS	32
+ #define QPIC_PER_CW_CMD_SGL		32
+ #define QPIC_PER_CW_DATA_SGL		8
+ 
+@@ -221,8 +223,13 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+ /*
+  * This data type corresponds to the BAM transaction which will be used for all
+  * NAND transfers.
++ * @bam_ce - the array of BAM command elements
+  * @cmd_sgl - sgl for NAND BAM command pipe
+  * @data_sgl - sgl for NAND BAM consumer/producer pipe
++ * @bam_ce_pos - the index in bam_ce which is available for next sgl
++ * @bam_ce_start - the index in bam_ce which marks the start position ce
++ *		   for current sgl. It will be used for size calculation
++ *		   for current sgl
+  * @cmd_sgl_pos - current index in command sgl.
+  * @cmd_sgl_start - start index in command sgl.
+  * @tx_sgl_pos - current index in data sgl for tx.
+@@ -231,8 +238,11 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  * @rx_sgl_start - start index in data sgl for rx.
+  */
+ struct bam_transaction {
++	struct bam_cmd_element *bam_ce;
+ 	struct scatterlist *cmd_sgl;
+ 	struct scatterlist *data_sgl;
++	u32 bam_ce_pos;
++	u32 bam_ce_start;
+ 	u32 cmd_sgl_pos;
+ 	u32 cmd_sgl_start;
+ 	u32 tx_sgl_pos;
+@@ -464,7 +474,8 @@ alloc_bam_transaction(struct qcom_nand_c
+ 
+ 	bam_txn_size =
+ 		sizeof(*bam_txn) + num_cw *
+-		((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
++		((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
++		(sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+ 		(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+ 
+ 	bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+@@ -474,6 +485,10 @@ alloc_bam_transaction(struct qcom_nand_c
+ 	bam_txn = bam_txn_buf;
+ 	bam_txn_buf += sizeof(*bam_txn);
+ 
++	bam_txn->bam_ce = bam_txn_buf;
++	bam_txn_buf +=
++		sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
++
+ 	bam_txn->cmd_sgl = bam_txn_buf;
+ 	bam_txn_buf +=
+ 		sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
+@@ -491,6 +506,8 @@ static void clear_bam_transaction(struct
+ 	if (!nandc->props->is_bam)
+ 		return;
+ 
++	bam_txn->bam_ce_pos = 0;
++	bam_txn->bam_ce_start = 0;
+ 	bam_txn->cmd_sgl_pos = 0;
+ 	bam_txn->cmd_sgl_start = 0;
+ 	bam_txn->tx_sgl_pos = 0;

target/linux/ipq40xx/patches-4.14/050-0003-mtd-nand-qcom-support-for-command-descriptor-formati.patch

@@ -0,0 +1,201 @@
+From 8d6b6d7e135e9bbfc923d34a45cb0e72695e63ed Mon Sep 17 00:00:00 2001
+From: Abhishek Sahu <absahu@codeaurora.org>
+Date: Mon, 25 Sep 2017 13:21:26 +0530
+Subject: [PATCH 3/7] mtd: nand: qcom: support for command descriptor formation
+
+1. Add the function for command descriptor preparation which will
+   be used only by BAM DMA and it will form the DMA descriptors
+   containing command elements
+2. DMA_PREP_CMD flag should be used for forming command DMA
+   descriptors
+
+Reviewed-by: Archit Taneja <architt@codeaurora.org>
+Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 108 +++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 92 insertions(+), 16 deletions(-)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -200,6 +200,14 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
+  */
+ #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
+ 
++/* Returns the NAND register physical address */
++#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
++
++/* Returns the dma address for reg read buffer */
++#define reg_buf_dma_addr(chip, vaddr) \
++	((chip)->reg_read_dma + \
++	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
++
+ #define QPIC_PER_CW_CMD_ELEMENTS	32
+ #define QPIC_PER_CW_CMD_SGL		32
+ #define QPIC_PER_CW_DATA_SGL		8
+@@ -317,7 +325,8 @@ struct nandc_regs {
+  *				controller
+  * @dev:			parent device
+  * @base:			MMIO base
+- * @base_dma:			physical base address of controller registers
++ * @base_phys:			physical base address of controller registers
++ * @base_dma:			dma base address of controller registers
+  * @core_clk:			controller clock
+  * @aon_clk:			another controller clock
+  *
+@@ -350,6 +359,7 @@ struct qcom_nand_controller {
+ 	struct device *dev;
+ 
+ 	void __iomem *base;
++	phys_addr_t base_phys;
+ 	dma_addr_t base_dma;
+ 
+ 	struct clk *core_clk;
+@@ -753,6 +763,66 @@ static int prepare_bam_async_desc(struct
+ }
+ 
+ /*
++ * Prepares the command descriptor for BAM DMA which will be used for NAND
++ * register reads and writes. The command descriptor requires the command
++ * to be formed in command element type so this function uses the command
++ * element from bam transaction ce array and fills the same with required
++ * data. A single SGL can contain multiple command elements so
++ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
++ * after the current command element.
++ */
++static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
++				 int reg_off, const void *vaddr,
++				 int size, unsigned int flags)
++{
++	int bam_ce_size;
++	int i, ret;
++	struct bam_cmd_element *bam_ce_buffer;
++	struct bam_transaction *bam_txn = nandc->bam_txn;
++
++	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
++
++	/* fill the command desc */
++	for (i = 0; i < size; i++) {
++		if (read)
++			bam_prep_ce(&bam_ce_buffer[i],
++				    nandc_reg_phys(nandc, reg_off + 4 * i),
++				    BAM_READ_COMMAND,
++				    reg_buf_dma_addr(nandc,
++						     (__le32 *)vaddr + i));
++		else
++			bam_prep_ce_le32(&bam_ce_buffer[i],
++					 nandc_reg_phys(nandc, reg_off + 4 * i),
++					 BAM_WRITE_COMMAND,
++					 *((__le32 *)vaddr + i));
++	}
++
++	bam_txn->bam_ce_pos += size;
++
++	/* use the separate sgl after this command */
++	if (flags & NAND_BAM_NEXT_SGL) {
++		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
++		bam_ce_size = (bam_txn->bam_ce_pos -
++				bam_txn->bam_ce_start) *
++				sizeof(struct bam_cmd_element);
++		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
++			   bam_ce_buffer, bam_ce_size);
++		bam_txn->cmd_sgl_pos++;
++		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
++
++		if (flags & NAND_BAM_NWD) {
++			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
++						     DMA_PREP_FENCE |
++						     DMA_PREP_CMD);
++			if (ret)
++				return ret;
++		}
++	}
++
++	return 0;
++}
++
++/*
+  * Prepares the data descriptor for BAM DMA which will be used for NAND
+  * data reads and writes.
+  */
+@@ -870,19 +940,22 @@ static int read_reg_dma(struct qcom_nand
+ {
+ 	bool flow_control = false;
+ 	void *vaddr;
+-	int size;
+ 
+-	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+-		flow_control = true;
++	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
++	nandc->reg_read_pos += num_regs;
+ 
+ 	if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
+ 		first = dev_cmd_reg_addr(nandc, first);
+ 
+-	size = num_regs * sizeof(u32);
+-	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
+-	nandc->reg_read_pos += num_regs;
++	if (nandc->props->is_bam)
++		return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
++					     num_regs, flags);
++
++	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
++		flow_control = true;
+ 
+-	return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
++	return prep_adm_dma_desc(nandc, true, first, vaddr,
++				 num_regs * sizeof(u32), flow_control);
+ }
+ 
+ /*
+@@ -899,13 +972,9 @@ static int write_reg_dma(struct qcom_nan
+ 	bool flow_control = false;
+ 	struct nandc_regs *regs = nandc->regs;
+ 	void *vaddr;
+-	int size;
+ 
+ 	vaddr = offset_to_nandc_reg(regs, first);
+ 
+-	if (first == NAND_FLASH_CMD)
+-		flow_control = true;
+-
+ 	if (first == NAND_ERASED_CW_DETECT_CFG) {
+ 		if (flags & NAND_ERASED_CW_SET)
+ 			vaddr = &regs->erased_cw_detect_cfg_set;
+@@ -922,10 +991,15 @@ static int write_reg_dma(struct qcom_nan
+ 	if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
+ 		first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
+ 
+-	size = num_regs * sizeof(u32);
++	if (nandc->props->is_bam)
++		return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
++					     num_regs, flags);
++
++	if (first == NAND_FLASH_CMD)
++		flow_control = true;
+ 
+-	return prep_adm_dma_desc(nandc, false, first, vaddr, size,
+-				 flow_control);
++	return prep_adm_dma_desc(nandc, false, first, vaddr,
++				 num_regs * sizeof(u32), flow_control);
+ }
+ 
+ /*
+@@ -1189,7 +1263,8 @@ static int submit_descs(struct qcom_nand
+ 		}
+ 
+ 		if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
+-			r = prepare_bam_async_desc(nandc, nandc->cmd_chan, 0);
++			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
++						   DMA_PREP_CMD);
+ 			if (r)
+ 				return r;
+ 		}
+@@ -2728,6 +2803,7 @@ static int qcom_nandc_probe(struct platf
+ 	if (IS_ERR(nandc->base))
+ 		return PTR_ERR(nandc->base);
+ 
++	nandc->base_phys = res->start;
+ 	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
+ 
+ 	nandc->core_clk = devm_clk_get(dev, "core");

target/linux/ipq40xx/patches-4.14/050-0005-mtd-nand-force-drivers-to-explicitly-send-READ-PROG-.patch

@@ -0,0 +1,94 @@
+From 25f815f66a141436df8a4c45e5d2765272aea2ac Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@free-electrons.com>
+Date: Thu, 30 Nov 2017 18:01:30 +0100
+Subject: [PATCH 5/7] mtd: nand: force drivers to explicitly send READ/PROG
+ commands
+
+The core currently send the READ0 and SEQIN+PAGEPROG commands in
+nand_do_read/write_ops(). This is inconsistent with
+->read/write_oob[_raw]() hooks behavior which are expected to send
+these commands.
+
+There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core
+that a specific controller wants to send the READ/SEQIN+PAGEPROG
+commands on its own, but it's an opt-in flag, and existing drivers are
+unlikely to be updated to pass it.
+
+Moreover, some controllers cannot dissociate the READ/PAGEPROG commands
+from the associated data transfer and ECC engine activation, and
+developers have to hack things in their ->cmdfunc() implementation to
+handle such complex cases, or have to accept the perf penalty of sending
+twice the same command.
+To address this problem we are planning on adding a new interface which
+is passed all information about a NAND operation (including the amount
+of data to transfer) and replacing all calls to ->cmdfunc() to calls to
+this new ->exec_op() hook. But, in order to do that, we need to have all
+->cmdfunc() calls placed near their associated ->read/write_buf/byte()
+calls.
+
+Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS
+the default case, and remove this flag.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+[miquel.raynal@free-electrons.com: tested, fixed and rebased on nand/next]
+Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
+Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+---
+ drivers/mtd/nand/qcom_nandc.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/drivers/mtd/nand/qcom_nandc.c
++++ b/drivers/mtd/nand/qcom_nandc.c
+@@ -1727,6 +1727,7 @@ static int qcom_nandc_read_page(struct m
+ 	u8 *data_buf, *oob_buf = NULL;
+ 	int ret;
+ 
++	nand_read_page_op(chip, page, 0, NULL, 0);
+ 	data_buf = buf;
+ 	oob_buf = oob_required ? chip->oob_poi : NULL;
+ 
+@@ -1752,6 +1753,7 @@ static int qcom_nandc_read_page_raw(stru
+ 	int i, ret;
+ 	int read_loc;
+ 
++	nand_read_page_op(chip, page, 0, NULL, 0);
+ 	data_buf = buf;
+ 	oob_buf = chip->oob_poi;
+ 
+@@ -1852,6 +1854,8 @@ static int qcom_nandc_write_page(struct
+ 	u8 *data_buf, *oob_buf;
+ 	int i, ret;
+ 
++	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
++
+ 	clear_read_regs(nandc);
+ 	clear_bam_transaction(nandc);
+ 
+@@ -1904,6 +1908,9 @@ static int qcom_nandc_write_page(struct
+ 
+ 	free_descs(nandc);
+ 
++	if (!ret)
++		ret = nand_prog_page_end_op(chip);
++
+ 	return ret;
+ }
+ 
+@@ -1918,6 +1925,7 @@ static int qcom_nandc_write_page_raw(str
+ 	u8 *data_buf, *oob_buf;
+ 	int i, ret;
+ 
++	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+ 	clear_read_regs(nandc);
+ 	clear_bam_transaction(nandc);
+ 
+@@ -1972,6 +1980,9 @@ static int qcom_nandc_write_page_raw(str
+ 
+ 	free_descs(nandc);
+ 
++	if (!ret)
++		ret = nand_prog_page_end_op(chip);
++
+ 	return ret;
+ }
+ 

target/linux/ipq40xx/patches-4.14/059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch

@@ -0,0 +1,29 @@
+From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
+From: Lina Iyer <lina.iyer@linaro.org>
+Date: Wed, 25 Mar 2015 14:25:29 -0600
+Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
+
+Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
+
+Cc: Stephen Boyd <sboyd@codeaurora.org>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Kevin Hilman <khilman@linaro.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
+---
+ drivers/cpuidle/Kconfig.arm | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/cpuidle/Kconfig.arm
++++ b/drivers/cpuidle/Kconfig.arm
+@@ -75,3 +75,10 @@ config ARM_MVEBU_V7_CPUIDLE
+ 	depends on ARCH_MVEBU && !ARM64
+ 	help
+ 	  Select this to enable cpuidle on Armada 370, 38x and XP processors.
++
++config ARM_QCOM_CPUIDLE
++	bool "CPU Idle Driver for QCOM processors"
++	depends on ARCH_QCOM
++	select ARM_CPUIDLE
++	help
++	  Select this to enable cpuidle on QCOM processors.

target/linux/ipq40xx/patches-4.14/069-arm-boot-add-dts-files.patch

@@ -0,0 +1,32 @@
+From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 11:03:18 +0100
+Subject: [PATCH 69/69] arm: boot: add dts files
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/Makefile | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -697,7 +697,19 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+ 	qcom-apq8074-dragonboard.dtb \
+ 	qcom-apq8084-ifc6540.dtb \
+ 	qcom-apq8084-mtp.dtb \
++	qcom-ipq4018-a42.dtb \
++	qcom-ipq4018-ex6100v2.dtb \
++	qcom-ipq4018-ex6150v2.dtb \
++	qcom-ipq4018-fritz4040.dtb \
++	qcom-ipq4018-jalapeno.dtb \
++	qcom-ipq4018-rt-ac58u.dtb \
++	qcom-ipq4018-wre6606.dtb \
+ 	qcom-ipq4019-ap.dk01.1-c1.dtb \
++	qcom-ipq4019-a62.dtb \
++	qcom-ipq4019-ap.dk04.1-c1.dtb \
++	qcom-ipq4028-wpj428.dtb \
++	qcom-ipq4029-gl-b1300.dtb \
++	qcom-ipq4029-mr33.dtb \
+ 	qcom-ipq8064-ap148.dtb \
+ 	qcom-msm8660-surf.dtb \
+ 	qcom-msm8960-cdp.dtb \

target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch

@@ -0,0 +1,16 @@
+Check for SCM availability before attempting to use SPM
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/drivers/soc/qcom/spm.c
++++ b/drivers/soc/qcom/spm.c
+@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru
+ 	cpumask_t mask;
+ 	bool use_scm_power_down = false;
+ 
++	if (!qcom_scm_is_available())
++		return -EPROBE_DEFER;
++
+ 	for (i = 0; ; i++) {
+ 		state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+ 		if (!state_node)

target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch

@@ -0,0 +1,188 @@
+From patchwork Mon Jan 29 05:11:16 2018
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
+From: Sricharan R <sricharan@codeaurora.org>
+X-Patchwork-Id: 10189263
+Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
+To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
+ linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org, 
+ catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
+ bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
+ linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
+Cc: sricharan@codeaurora.org
+Date: Mon, 29 Jan 2018 10:41:16 +0530
+
+Now with the driver updates for some peripherals being there,
+add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
+peripheral support.
+
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 134 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -25,7 +25,9 @@
+ 
+ 	aliases {
+ 		spi0 = &spi_0;
++		spi1 = &spi_1;
+ 		i2c0 = &i2c_0;
++		i2c1 = &i2c_1;
+ 	};
+ 
+ 	cpus {
+@@ -190,6 +192,22 @@
+ 			clock-names = "core", "iface";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		spi_1: spi@78b6000 { /* BLSP1 QUP2 */
++			compatible = "qcom,spi-qup-v2.2.1";
++			reg = <0x78b6000 0x600>;
++			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
++				<&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
++			dma-names = "rx", "tx";
+ 			status = "disabled";
+ 		};
+ 
+@@ -202,9 +220,24 @@
+ 			clock-names = "iface", "core";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
++			dma-names = "rx", "tx";
+ 			status = "disabled";
+ 		};
+ 
++		i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
++			compatible = "qcom,i2c-qup-v2.2.1";
++			reg = <0x78b8000 0x600>;
++			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
++				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
++			clock-names = "iface", "core";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
+ 
+ 		cryptobam: dma@8e04000 {
+ 			compatible = "qcom,bam-v1.7.0";
+@@ -311,6 +344,101 @@
+ 			reg = <0x4ab000 0x4>;
+ 		};
+ 
++		pcie0: pci@40000000 {
++			compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
++			reg =  <0x40000000 0xf1d
++				0x40000f20 0xa8
++				0x80000 0x2000
++				0x40100000 0x1000>;
++			reg-names = "dbi", "elbi", "parf", "config";
++			device_type = "pci";
++			linux,pci-domain = <0>;
++			bus-range = <0x00 0xff>;
++			num-lanes = <1>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++
++			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
++				  0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++
++			interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
++			interrupt-names = "msi";
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0x7>;
++			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++					<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++					<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++					<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++			clocks = <&gcc GCC_PCIE_AHB_CLK>,
++				 <&gcc GCC_PCIE_AXI_M_CLK>,
++				 <&gcc GCC_PCIE_AXI_S_CLK>;
++			clock-names = "aux",
++				      "master_bus",
++				      "slave_bus";
++
++			resets = <&gcc PCIE_AXI_M_ARES>,
++				 <&gcc PCIE_AXI_S_ARES>,
++				 <&gcc PCIE_PIPE_ARES>,
++				 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
++				 <&gcc PCIE_AXI_S_XPU_ARES>,
++				 <&gcc PCIE_PARF_XPU_ARES>,
++				 <&gcc PCIE_PHY_ARES>,
++				 <&gcc PCIE_AXI_M_STICKY_ARES>,
++				 <&gcc PCIE_PIPE_STICKY_ARES>,
++				 <&gcc PCIE_PWR_ARES>,
++				 <&gcc PCIE_AHB_ARES>,
++				 <&gcc PCIE_PHY_AHB_ARES>;
++			reset-names = "axi_m",
++				      "axi_s",
++				      "pipe",
++				      "axi_m_vmid",
++				      "axi_s_xpu",
++				      "parf",
++				      "phy",
++				      "axi_m_sticky",
++				      "pipe_sticky",
++				      "pwr",
++				      "ahb",
++				      "phy_ahb";
++
++			status = "disabled";
++		};
++
++		qpic_bam: dma@7984000 {
++			compatible = "qcom,bam-v1.7.0";
++			reg = <0x7984000 0x1a000>;
++			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_QPIC_CLK>;
++			clock-names = "bam_clk";
++			#dma-cells = <1>;
++			qcom,ee = <0>;
++			status = "disabled";
++		};
++
++		nand: qpic-nand@79b0000 {
++			compatible = "qcom,ipq4019-nand";
++			reg = <0x79b0000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			clocks = <&gcc GCC_QPIC_CLK>,
++				 <&gcc GCC_QPIC_AHB_CLK>;
++			clock-names = "core", "aon";
++
++			dmas = <&qpic_bam 0>,
++			       <&qpic_bam 1>,
++			       <&qpic_bam 2>;
++			dma-names = "tx", "rx", "cmd";
++			status = "disabled";
++
++			nand@0 {
++				reg = <0>;
++
++				nand-ecc-strength = <4>;
++				nand-ecc-step-size = <512>;
++				nand-bus-width = <8>;
++			};
++		};
++
+ 		wifi0: wifi@a000000 {
+ 			compatible = "qcom,ipq4019-wifi";
+ 			reg = <0xa000000 0x200000>;

target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch

@@ -0,0 +1,23 @@
+From 561a7e69d2811f236266ff9222a1e683ebf8b9e0 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Thu, 1 Mar 2018 20:50:29 +0100
+Subject: [PATCH] ARM: dts: ipq4019: fix PCI range
+
+The PCI range is invalid and PCI attached devices doen't work.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -359,7 +359,7 @@
+ 			#size-cells = <2>;
+ 
+ 			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+-				  0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++				  0x82000000 0 0x40300000 0x40300000 0 0x400000>;
+ 
+ 			interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
+ 			interrupt-names = "msi";

target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch

@@ -0,0 +1,38 @@
+From 07b6d0cdbbda8c917480eceaec668f09e4cf24a5 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Mon, 14 Nov 2016 23:49:22 +0100
+Subject: [PATCH] mtd: nand: add Winbond manufacturer and chip
+
+This patch adds the W25N01GV NAND to the table of
+known devices. Without this patch the device gets detected:
+
+nand: device found, Manufacturer ID: 0xef, Chip ID: 0xaa
+nand: Unknown NAND 256MiB 1,8V 8-bit
+nand: 256 MiB, SLC, erase size: 64 KiB, page size: 1024, OOB size : 16
+
+Whereas the u-boot identifies it as:
+spi_nand: spi_nand_flash_probe SF NAND ID 00:ef:aa:21
+SF: Detected W25N01GV with page size 2 KiB, total 128 MiB
+
+Due to the page size discrepancy, it's impossible to attach
+ubi volumes on the device.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/nand/nand_ids.c | 4 ++++
+ include/linux/mtd/nand.h    | 1 +
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/mtd/nand/nand_ids.c
++++ b/drivers/mtd/nand/nand_ids.c
+@@ -54,6 +54,10 @@ struct nand_flash_dev nand_flash_ids[] =
+ 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+ 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+ 		  NAND_ECC_INFO(40, SZ_1K), 4 },
++	{"W25N01GV 1G 3.3V 8-bit",
++		{ .id = {0xef, 0xaa} },
++		  SZ_2K, SZ_128, SZ_128K, NAND_NO_SUBPAGE_WRITE,
++		  2, 64, NAND_ECC_INFO(1, SZ_512) },
+ 
+ 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
+ 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),

target/linux/ipq40xx/patches-4.14/105-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch

@@ -0,0 +1,71 @@
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 12 Apr 2018 21:01:38 +0200
+Subject: [PATCH] pinctrl: msm: fix gpio-hog related boot issues
+
+Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
+Setting up any gpio-hog in the device-tree for his device would
+"kill the bootup completely":
+
+| [    0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
+| [    0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
+| [    1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
+| [    1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
+| [    1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
+| [    1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
+| [    1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
+
+This was also verified on a RT-AC58U (IPQ4018) which would
+no longer boot, if a gpio-hog was specified. (Tried forcing
+the USB LED PIN (GPIO0) to high.).
+
+The problem is that Pinctrl+GPIO registration is currently
+peformed in the following order in pinctrl-msm.c:
+	1. pinctrl_register()
+	2. gpiochip_add()
+	3. gpiochip_add_pin_range()
+
+The actual error code -517 == -EPROBE_DEFER is coming from
+pinctrl_get_device_gpio_range(), which is called through:
+        gpiochip_add
+            of_gpiochip_add
+                of_gpiochip_scan_gpios
+                    gpiod_hog
+                        gpiochip_request_own_desc
+                            __gpiod_request
+                                chip->request
+                                    gpiochip_generic_request
+                                       pinctrl_gpio_request
+                                          pinctrl_get_device_gpio_range
+
+pinctrl_get_device_gpio_range() is unable to find any valid
+pin ranges, since nothing has been added to the pinctrldev_list yet.
+so the range can't be found, and the operation fails with -EPROBE_DEFER.
+
+This patch fixes the issue by adding the "gpio-ranges" property to
+the pinctrl device node of all upstream Qcom SoC. The pin ranges are
+then added by the gpio core.
+
+In order to remain compatible with older, existing DTs (and ACPI)
+a check for the "gpio-ranges" property has been added to
+msm_gpio_init(). This prevents the driver of adding the same entry
+to the pinctrldev_list twice.
+
+Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+Origin: other, https://patchwork.kernel.org/patch/10339127/
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi   |  1 +
+ drivers/pinctrl/qcom/pinctrl-msm.c    | 23 ++++++++++++++++++-----
+ 14 files changed, 32 insertions(+), 6 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -166,6 +166,7 @@
+ 			compatible = "qcom,ipq4019-pinctrl";
+ 			reg = <0x01000000 0x300000>;
+ 			gpio-controller;
++			gpio-ranges = <&tlmm 0 0 100>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;

target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

@@ -0,0 +1,109 @@
+From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Fri, 8 Apr 2016 15:26:10 -0500
+Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
+
+v1 was the incorrect choice here and sometimes the board
+would not come up properly.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+	- moved L2-Cache to be a subnode of cpu0
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -36,19 +36,27 @@
+ 		cpu@0 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a7";
+-			enable-method = "qcom,kpss-acc-v1";
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
+ 			qcom,acc = <&acc0>;
+ 			qcom,saw = <&saw0>;
+ 			reg = <0x0>;
+ 			clocks = <&gcc GCC_APPS_CLK_SRC>;
+ 			clock-frequency = <0>;
+ 			operating-points-v2 = <&cpu0_opp_table>;
++
++			L2: l2-cache {
++				compatible = "qcom,arch-cache";
++				cache-level = <2>;
++				qcom,saw = <&saw_l2>;
++			};
+ 		};
+ 
+ 		cpu@1 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a7";
+-			enable-method = "qcom,kpss-acc-v1";
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
+ 			qcom,acc = <&acc1>;
+ 			qcom,saw = <&saw1>;
+ 			reg = <0x1>;
+@@ -60,7 +68,8 @@
+ 		cpu@2 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a7";
+-			enable-method = "qcom,kpss-acc-v1";
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
+ 			qcom,acc = <&acc2>;
+ 			qcom,saw = <&saw2>;
+ 			reg = <0x2>;
+@@ -72,7 +81,8 @@
+ 		cpu@3 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a7";
+-			enable-method = "qcom,kpss-acc-v1";
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
+ 			qcom,acc = <&acc3>;
+ 			qcom,saw = <&saw3>;
+ 			reg = <0x3>;
+@@ -265,22 +275,22 @@
+ 		};
+ 
+                 acc0: clock-controller@b088000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+                 };
+ 
+                 acc1: clock-controller@b098000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+                 };
+ 
+                 acc2: clock-controller@b0a8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+                 };
+ 
+                 acc3: clock-controller@b0b8000 {
+-                        compatible = "qcom,kpss-acc-v1";
++                        compatible = "qcom,kpss-acc-v2";
+                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+                 };
+ 
+@@ -308,6 +318,12 @@
+                         regulator;
+                 };
+ 
++		saw_l2: regulator@b012000 {
++			compatible = "qcom,saw2";
++			reg = <0xb012000 0x1000>;
++			regulator;
++		};
++
+ 		serial@78af000 {
+ 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ 			reg = <0x78af000 0x200>;

target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch

@@ -0,0 +1,130 @@
+From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Thu, 17 Mar 2016 16:22:28 -0500
+Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
+
+This adds the SoC nodes to the ipq4019 device tree and
+enable it for the DK01.1 board.
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+Changes:
+	- replaced space with tab
+	- added sleep and mock_utmi clocks
+	- added registers for usb2 and usb3 parent node
+	- changed compatible to qca,ipa4019-dwc3
+	- updated usb2 and usb3 names
+	  (included the reg - in case they become necessary later)
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
+ arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -101,5 +101,25 @@
+ 		wifi@a800000 {
+ 			status = "ok";
+ 		};
++
++		usb3_ss_phy: ssphy@9a000 {
++			status = "ok";
++		};
++
++		usb3_hs_phy: hsphy@a6000 {
++			status = "ok";
++		};
++
++		usb3: usb3@8af8800 {
++			status = "ok";
++		};
++
++		usb2_hs_phy: hsphy@a8000 {
++			status = "ok";
++		};
++
++		usb2: usb2@60f8800 {
++			status = "ok";
++		};
+ 	};
+ };
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -539,5 +539,76 @@
+ 					  "legacy";
+ 			status = "disabled";
+ 		};
++
++		usb3_ss_phy: ssphy@9a000 {
++			compatible = "qca,uni-ssphy";
++			reg = <0x9a000 0x800>;
++			reg-names = "phy_base";
++			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++			reset-names = "por_rst";
++			status = "disabled";
++		};
++
++		usb3_hs_phy: hsphy@a6000 {
++			compatible = "qca,baldur-usb3-hsphy";
++			reg = <0xa6000 0x40>;
++			reg-names = "phy_base";
++			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++			reset-names = "por_rst", "srif_rst";
++			status = "disabled";
++		};
++
++		usb3@8af8800 {
++			compatible = "qca,ipq4019-dwc3";
++			reg = <0x8af8800 0x100>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			clocks = <&gcc GCC_USB3_MASTER_CLK>,
++				 <&gcc GCC_USB3_SLEEP_CLK>,
++				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++			clock-names = "master", "sleep", "mock_utmi";
++			ranges;
++			status = "disabled";
++
++			dwc3@8a00000 {
++				compatible = "snps,dwc3";
++				reg = <0x8a00000 0xf8000>;
++				interrupts = <0 132 0>;
++				usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
++				phy-names = "usb2-phy", "usb3-phy";
++				dr_mode = "host";
++			};
++		};
++
++		usb2_hs_phy: hsphy@a8000 {
++			compatible = "qca,baldur-usb2-hsphy";
++			reg = <0xa8000 0x40>;
++			reg-names = "phy_base";
++			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++			reset-names = "por_rst", "srif_rst";
++			status = "disabled";
++		};
++
++		usb2@60f8800 {
++			compatible = "qca,ipq4019-dwc3";
++			reg = <0x60f8800 0x100>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			clocks = <&gcc GCC_USB2_MASTER_CLK>,
++				 <&gcc GCC_USB2_SLEEP_CLK>,
++				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++			clock-names = "master", "sleep", "mock_utmi";
++			ranges;
++			status = "disabled";
++
++			dwc3@6000000 {
++				compatible = "snps,dwc3";
++				reg = <0x6000000 0xf8000>;
++				interrupts = <0 136 0>;
++				usb-phy = <&usb2_hs_phy>;
++				phy-names = "usb2-phy";
++				dr_mode = "host";
++			};
++		};
+ 	};
+ };

target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch

@@ -0,0 +1,35 @@
+From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 00:58:18 +0100
+Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
+
+Add support for the Qualcomm Atheros IPQ4019 SoC.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/Makefile          | 1 +
+ arch/arm/mach-qcom/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -151,6 +151,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
+ endif
+ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
+ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
+ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+ 
+ # Machine directory name.  This list is sorted alphanumerically
+--- a/arch/arm/mach-qcom/Kconfig
++++ b/arch/arm/mach-qcom/Kconfig
+@@ -27,4 +27,9 @@ config ARCH_MDM9615
+ 	bool "Enable support for MDM9615"
+ 	select CLKSRC_QCOM
+ 
++config ARCH_IPQ40XX
++	bool "Enable support for IPQ40XX"
++	select CLKSRC_QCOM
++	select HAVE_ARM_ARCH_TIMER
++
+ endif

target/linux/ipq40xx/patches-4.14/400-mtd-ubi-add-quirk-to-autoload-ubi-on-rt-ac58u.patch

@@ -0,0 +1,29 @@
+From b8f3a7ccbeca5bdbd1b6210b94b38d3fef2dd0bd Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Thu, 19 Jan 2017 01:57:22 +0100
+Subject: [PATCH 16/38] mtd: ubi: add auto_attach HACK for the ASUS RT-AC58U
+
+This patch adds a hack that allows UBI's autoattach feature
+to work with the custom ASUS UBI_DEV partition name.
+
+This is necessary because the vendor's u-boot doesn't leave
+the bootargs / cmdline alone, so the it can't be overwritten
+easily otherwise.
+
+Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
+---
+ drivers/mtd/ubi/build.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -1187,6 +1187,9 @@ static void __init ubi_auto_attach(void)
+ 	mtd = open_mtd_device("ubi");
+ 	if (IS_ERR(mtd))
+ 		mtd = open_mtd_device("data");
++	/* Hack for the Asus RT-AC58U */
++	if (IS_ERR(mtd))
++		mtd = open_mtd_device("UBI_DEV");
+ 
+ 	if (IS_ERR(mtd))
+ 		return;

target/linux/ipq40xx/patches-4.14/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch

@@ -0,0 +1,53 @@
+From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
+From: Rakesh Nair <ranair@codeaurora.org>
+Date: Wed, 20 Jul 2016 15:02:01 +0530
+Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
+ netdev_ops
+
+Add callback support to get default vlan tag and register
+receive flow steering filter.
+
+Used by IPQ4019 ess-edma driver.
+
+BUG=chrome-os-partner:33096
+TEST=none
+
+Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
+Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
+Reviewed-on: https://chromium-review.googlesource.com/362203
+Commit-Ready: Grant Grundler <grundler@chromium.org>
+Tested-by: Grant Grundler <grundler@chromium.org>
+Reviewed-by: Grant Grundler <grundler@chromium.org>
+---
+ include/linux/netdevice.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -713,6 +713,16 @@ struct xps_map {
+ #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
+        - sizeof(struct xps_map)) / sizeof(u16))
+ 
++#ifdef CONFIG_RFS_ACCEL
++typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
++                                     __be32 src,
++                                     __be32 dst,
++                                     __be16 sport,
++                                     __be16 dport,
++                                     u8 proto,
++                                     u16 rxq_index,
++                                     u32 action);
++#endif
+ /*
+  * This structure holds all XPS maps for device.  Maps are indexed by CPU.
+  */
+@@ -1258,6 +1268,9 @@ struct net_device_ops {
+ 						     const struct sk_buff *skb,
+ 						     u16 rxq_index,
+ 						     u32 flow_id);
++        int                     (*ndo_register_rfs_filter)(struct net_device *dev,
++                                                              set_rfs_filter_callback_t set_filter);
++        int                     (*ndo_get_default_vlan_tag)(struct net_device *net);
+ #endif
+ 	int			(*ndo_add_slave)(struct net_device *dev,
+ 						 struct net_device *slave_dev);

target/linux/ipq40xx/patches-4.14/701-dts-ipq4019-add-mdio-node.patch

@@ -0,0 +1,52 @@
+From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 20 Nov 2016 01:10:33 +0100
+Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
+
+This patch adds the mdio device-tree node.
+This is where the switch is connected to, so it's needed
+for the ethernet interfaces.
+
+Note: The driver isn't anywhere close to be upstream,
+so the info might change.
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -540,6 +540,34 @@
+ 			status = "disabled";
+ 		};
+ 
++		mdio@90000 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "qcom,ipq4019-mdio";
++			reg = <0x90000 0x64>;
++			status = "disabled";
++
++			ethernet-phy@0 {
++				reg = <0>;
++			};
++
++			ethernet-phy@1 {
++				reg = <1>;
++			};
++
++			ethernet-phy@2 {
++				reg = <2>;
++			};
++
++			ethernet-phy@3 {
++				reg = <3>;
++			};
++
++			ethernet-phy@4 {
++				reg = <4>;
++			};
++		};
++
+ 		usb3_ss_phy: ssphy@9a000 {
+ 			compatible = "qca,uni-ssphy";
+ 			reg = <0x9a000 0x800>;

target/linux/ipq40xx/patches-4.14/702-dts-ipq4019-add-PHY-switch-nodes.patch

@@ -0,0 +1,46 @@
+From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 20 Nov 2016 02:20:54 +0100
+Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
+
+This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
+nodes which are needed for the ar40xx.c driver to initialize the
+switch.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -568,6 +568,29 @@
+ 			};
+ 		};
+ 
++		ess-switch@c000000 {
++			compatible = "qcom,ess-switch";
++			reg = <0xc000000 0x80000>;
++			switch_access_mode = "local bus";
++			resets = <&gcc ESS_RESET>;
++			reset-names = "ess_rst";
++			clocks = <&gcc GCC_ESS_CLK>;
++			clock-names = "ess_clk";
++			switch_cpu_bmp = <0x1>;
++			switch_lan_bmp = <0x1e>;
++			switch_wan_bmp = <0x20>;
++			switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
++			switch_initvlas = <0x7c 0x54>;
++			status = "disabled";
++		};
++
++		ess-psgmii@98000 {
++			compatible = "qcom,ess-psgmii";
++			reg = <0x98000 0x800>;
++			psgmii_access_mode = "local bus";
++			status = "disabled";
++		};
++
+ 		usb3_ss_phy: ssphy@9a000 {
+ 			compatible = "qca,uni-ssphy";
+ 			reg = <0x9a000 0x800>;

target/linux/ipq40xx/patches-4.14/711-dts-ipq4019-add-ethernet-essedma-node.patch

@@ -0,0 +1,92 @@
+From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 20 Nov 2016 01:01:10 +0100
+Subject: [PATCH] dts: ipq4019: add ethernet essedma node
+
+This patch adds the device-tree node for the ethernet
+interfaces.
+
+Note: The driver isn't anywhere close to be upstream,
+so the info might change.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -28,6 +28,8 @@
+ 		spi1 = &spi_1;
+ 		i2c0 = &i2c_0;
+ 		i2c1 = &i2c_1;
++		ethernet0 = &gmac0;
++		ethernet1 = &gmac1;
+ 	};
+ 
+ 	cpus {
+@@ -591,6 +593,64 @@
+ 			status = "disabled";
+ 		};
+ 
++		edma@c080000 {
++			compatible = "qcom,ess-edma";
++			reg = <0xc080000 0x8000>;
++			qcom,page-mode = <0>;
++			qcom,rx_head_buf_size = <1540>;
++			qcom,mdio_supported;
++			qcom,poll_required = <1>;
++			qcom,num_gmac = <2>;
++			interrupts = <0  65 IRQ_TYPE_EDGE_RISING
++				      0  66 IRQ_TYPE_EDGE_RISING
++				      0  67 IRQ_TYPE_EDGE_RISING
++				      0  68 IRQ_TYPE_EDGE_RISING
++				      0  69 IRQ_TYPE_EDGE_RISING
++				      0  70 IRQ_TYPE_EDGE_RISING
++				      0  71 IRQ_TYPE_EDGE_RISING
++				      0  72 IRQ_TYPE_EDGE_RISING
++				      0  73 IRQ_TYPE_EDGE_RISING
++				      0  74 IRQ_TYPE_EDGE_RISING
++				      0  75 IRQ_TYPE_EDGE_RISING
++				      0  76 IRQ_TYPE_EDGE_RISING
++				      0  77 IRQ_TYPE_EDGE_RISING
++				      0  78 IRQ_TYPE_EDGE_RISING
++				      0  79 IRQ_TYPE_EDGE_RISING
++				      0  80 IRQ_TYPE_EDGE_RISING
++				      0 240 IRQ_TYPE_EDGE_RISING
++				      0 241 IRQ_TYPE_EDGE_RISING
++				      0 242 IRQ_TYPE_EDGE_RISING
++				      0 243 IRQ_TYPE_EDGE_RISING
++				      0 244 IRQ_TYPE_EDGE_RISING
++				      0 245 IRQ_TYPE_EDGE_RISING
++				      0 246 IRQ_TYPE_EDGE_RISING
++				      0 247 IRQ_TYPE_EDGE_RISING
++				      0 248 IRQ_TYPE_EDGE_RISING
++				      0 249 IRQ_TYPE_EDGE_RISING
++				      0 250 IRQ_TYPE_EDGE_RISING
++				      0 251 IRQ_TYPE_EDGE_RISING
++				      0 252 IRQ_TYPE_EDGE_RISING
++				      0 253 IRQ_TYPE_EDGE_RISING
++				      0 254 IRQ_TYPE_EDGE_RISING
++				      0 255 IRQ_TYPE_EDGE_RISING>;
++
++			status = "disabled";
++
++			gmac0: gmac0 {
++				local-mac-address = [00 00 00 00 00 00];
++				vlan_tag = <1 0x1f>;
++			};
++
++			gmac1: gmac1 {
++				local-mac-address = [00 00 00 00 00 00];
++				qcom,phy_mdio_addr = <4>;
++				qcom,poll_required = <1>;
++				qcom,forced_speed = <1000>;
++				qcom,forced_duplex = <1>;
++				vlan_tag = <2 0x20>;
++			};
++		};
++
+ 		usb3_ss_phy: ssphy@9a000 {
+ 			compatible = "qca,uni-ssphy";
+ 			reg = <0x9a000 0x800>;

target/linux/ipq40xx/patches-4.14/712-mr33-essedma.patch

@@ -0,0 +1,340 @@
+--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
++++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
+@@ -17,6 +17,11 @@
+ #include <linux/of.h>
+ #include <linux/of_net.h>
+ #include <linux/timer.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/clk.h>
++#include <linux/string.h>
++#include <linux/reset.h>
+ #include "edma.h"
+ #include "ess_edma.h"
+ 
+@@ -83,7 +88,103 @@ void edma_read_reg(u16 reg_addr, volatil
+ 	*reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr));
+ }
+ 
+-/* edma_change_tx_coalesce()
++static void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value)
++{
++	writel(reg_value, ((void __iomem *)
++		((unsigned long)edma->ess_hw_addr + reg_addr)));
++}
++
++static void ess_read_reg(struct edma_common_info *edma, u16 reg_addr,
++		  volatile u32 *reg_value)
++{
++	*reg_value = readl((void __iomem *)
++		((unsigned long)edma->ess_hw_addr + reg_addr));
++}
++
++static int ess_reset(struct edma_common_info *edma)
++{
++	struct device_node *switch_node = NULL;
++	struct reset_control *ess_rst;
++	u32 regval;
++
++	switch_node = of_find_node_by_name(NULL, "ess-switch");
++	if (!switch_node) {
++		pr_err("switch-node not found\n");
++		return -EINVAL;
++	}
++
++	ess_rst = of_reset_control_get(switch_node, "ess_rst");
++	of_node_put(switch_node);
++
++	if (IS_ERR(ess_rst)) {
++		pr_err("failed to find ess_rst!\n");
++		return -ENOENT;
++	}
++
++	reset_control_assert(ess_rst);
++	msleep(10);
++	reset_control_deassert(ess_rst);
++	msleep(100);
++	reset_control_put(ess_rst);
++
++	/* Enable only port 5 <--> port 0
++	 * bits 0:6 bitmap of ports it can fwd to */
++#define SET_PORT_BMP(r,v) \
++		ess_read_reg(edma, r, &regval); \
++		ess_write_reg(edma, r, ((regval & ~0x3F) | v));
++
++	SET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20);
++	SET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00);
++	SET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00);
++	SET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00);
++	SET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00);
++	SET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01);
++	ess_write_reg(edma, ESS_RGMII_CTRL, 0x400);
++	ess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX);
++	ess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX);
++	ess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0);
++#undef SET_PORT_BMP
++
++	/* forward multicast and broadcast frames to CPU */
++	ess_write_reg(edma, ESS_FWD_CTRL1,
++		(ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) |
++		(ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) |
++		(ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S));
++
++	return 0;
++}
++
++void ess_set_port_status_speed(struct edma_common_info *edma,
++			       struct phy_device *phydev, uint8_t port_id)
++{
++	uint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id);
++	uint32_t reg_val = 0;
++
++	ess_read_reg(edma, reg_off, &reg_val);
++
++	/* reset the speed bits [0:1] */
++	reg_val &= ~ESS_PORT_STATUS_SPEED_INV;
++
++	/* set the new speed */
++	switch(phydev->speed) {
++		case SPEED_1000:  reg_val |= ESS_PORT_STATUS_SPEED_1000; break;
++		case SPEED_100:   reg_val |= ESS_PORT_STATUS_SPEED_100;  break;
++		case SPEED_10:    reg_val |= ESS_PORT_STATUS_SPEED_10;   break;
++		default:          reg_val |= ESS_PORT_STATUS_SPEED_INV;  break;
++	}
++
++	/* check full/half duplex */
++	if (phydev->duplex) {
++		reg_val |= ESS_PORT_STATUS_DUPLEX_MODE;
++	} else {
++		reg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE;
++	}
++
++	ess_write_reg(edma, reg_off, reg_val);
++}
++
++/*
++ * edma_change_tx_coalesce()
+  *	change tx interrupt moderation timer
+  */
+ void edma_change_tx_coalesce(int usecs)
+@@ -551,6 +652,31 @@ static struct ctl_table edma_table[] = {
+ 	{}
+ };
+ 
++static int ess_parse(struct edma_common_info *edma)
++{
++	struct device_node *switch_node;
++	int ret = -EINVAL;
++
++	switch_node = of_find_node_by_name(NULL, "ess-switch");
++	if (!switch_node) {
++		pr_err("cannot find ess-switch node\n");
++		goto out;
++	}
++
++	edma->ess_hw_addr = of_io_request_and_map(switch_node,
++						  0, KBUILD_MODNAME);
++	if (!edma->ess_hw_addr) {
++		pr_err("%s ioremap fail.", __func__);
++		goto out;
++	}
++
++	edma->ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
++	ret = clk_prepare_enable(edma->ess_clk);
++out:
++	of_node_put(switch_node);
++	return ret;
++}
++
+ /* edma_axi_netdev_ops
+  *	Describe the operations supported by registered netdevices
+  *
+@@ -786,6 +912,17 @@ static int edma_axi_probe(struct platfor
+ 		miibus = mdio_data->mii_bus;
+ 	}
+ 
++	if (of_property_read_bool(np, "qcom,single-phy") &&
++	    edma_cinfo->num_gmac == 1) {
++		err = ess_parse(edma_cinfo);
++		if (!err)
++			err = ess_reset(edma_cinfo);
++		if (err)
++			goto err_single_phy_init;
++		else
++			edma_cinfo->is_single_phy = true;
++	}
++
+ 	for_each_available_child_of_node(np, pnp) {
+ 		const char *mac_addr;
+ 
+@@ -1074,11 +1211,15 @@ static int edma_axi_probe(struct platfor
+ 
+ 	for (i = 0; i < edma_cinfo->num_gmac; i++) {
+ 		if (adapter[i]->poll_required) {
++			int phy_mode = of_get_phy_mode(np);
++
++			if (phy_mode < 0)
++				phy_mode = PHY_INTERFACE_MODE_SGMII;
+ 			adapter[i]->phydev =
+ 				phy_connect(edma_netdev[i],
+ 					    (const char *)adapter[i]->phy_id,
+ 					    &edma_adjust_link,
+-					    PHY_INTERFACE_MODE_SGMII);
++					    phy_mode);
+ 			if (IS_ERR(adapter[i]->phydev)) {
+ 				dev_dbg(&pdev->dev, "PHY attach FAIL");
+ 				err = -EIO;
+@@ -1125,6 +1266,9 @@ err_rmap_alloc_fail:
+ 	for (i = 0; i < edma_cinfo->num_gmac; i++)
+ 		unregister_netdev(edma_netdev[i]);
+ err_register:
++err_single_phy_init:
++	iounmap(edma_cinfo->ess_hw_addr);
++	clk_disable_unprepare(edma_cinfo->ess_clk);
+ err_mdiobus_init_fail:
+ 	edma_free_rx_rings(edma_cinfo);
+ err_rx_rinit:
+@@ -1185,6 +1329,8 @@ static int edma_axi_remove(struct platfo
+ 	del_timer_sync(&edma_stats_timer);
+ 	edma_free_irqs(adapter);
+ 	unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr);
++	iounmap(edma_cinfo->ess_hw_addr);
++	clk_disable_unprepare(edma_cinfo->ess_clk);
+ 	edma_free_tx_resources(edma_cinfo);
+ 	edma_free_rx_resources(edma_cinfo);
+ 	edma_free_tx_rings(edma_cinfo);
+--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
++++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
+@@ -161,8 +161,10 @@ static void edma_configure_rx(struct edm
+ 	/* Set Rx FIFO threshold to start to DMA data to host */
+ 	rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;
+ 
+-	/* Set RX remove vlan bit */
+-	rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
++	if (!edma_cinfo->is_single_phy) {
++		/* Set RX remove vlan bit */
++		rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
++	}
+ 
+ 	edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);
+ }
+@@ -1295,6 +1297,10 @@ void edma_adjust_link(struct net_device
+ 	if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) {
+ 		dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed);
+ 		adapter->link_state = __EDMA_LINKUP;
++		if (adapter->edma_cinfo->is_single_phy) {
++			ess_set_port_status_speed(adapter->edma_cinfo, phydev,
++						  ffs(adapter->dp_bitmap) - 1);
++		}
+ 		netif_carrier_on(netdev);
+ 		if (netif_running(netdev))
+ 			netif_tx_wake_all_queues(netdev);
+@@ -1388,10 +1394,12 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
+ 	}
+ 
+ 	/* Check and mark VLAN tag offload */
+-	if (skb_vlan_tag_present(skb))
+-		flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
+-	else if (adapter->default_vlan_tag)
+-		flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
++	if (!adapter->edma_cinfo->is_single_phy) {
++		if (unlikely(skb_vlan_tag_present(skb)))
++			flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
++		else if (adapter->default_vlan_tag)
++			flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
++	}
+ 
+ 	/* Check and mark checksum offload */
+ 	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
+--- a/drivers/net/ethernet/qualcomm/essedma/edma.h
++++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
+@@ -31,6 +31,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/clk.h>
+ #include <linux/kernel.h>
+ #include <linux/device.h>
+ #include <linux/sysctl.h>
+@@ -331,6 +332,10 @@ struct edma_common_info {
+ 	struct edma_hw hw; /* edma hw specific structure */
+ 	struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
+ 	spinlock_t stats_lock; /* protect edma stats area for updation */
++
++	bool is_single_phy;
++	void __iomem *ess_hw_addr;
++	struct clk *ess_clk;
+ };
+ 
+ /* transimit packet descriptor (tpd) ring */
+@@ -443,4 +448,6 @@ void edma_change_tx_coalesce(int usecs);
+ void edma_change_rx_coalesce(int usecs);
+ void edma_get_tx_rx_coalesce(u32 *reg_val);
+ void edma_clear_irq_status(void);
++void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
++                               struct phy_device *phydev, uint8_t port_id);
+ #endif /* _EDMA_H_ */
+--- a/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
++++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
+@@ -329,4 +329,61 @@ struct edma_hw;
+ #define EDMA_RRD_PRIORITY_MASK 0x7
+ #define EDMA_RRD_PORT_TYPE_SHIFT 7
+ #define EDMA_RRD_PORT_TYPE_MASK 0x1F
++
++#define ESS_RGMII_CTRL		0x0004
++
++/* Port status registers */
++#define ESS_PORT0_STATUS	0x007C
++#define ESS_PORT1_STATUS	0x0080
++#define ESS_PORT2_STATUS	0x0084
++#define ESS_PORT3_STATUS	0x0088
++#define ESS_PORT4_STATUS	0x008C
++#define ESS_PORT5_STATUS	0x0090
++
++#define ESS_PORT_STATUS_HDX_FLOW_CTL	0x80
++#define ESS_PORT_STATUS_DUPLEX_MODE	0x40
++#define ESS_PORT_STATUS_RX_FLOW_EN	0x20
++#define ESS_PORT_STATUS_TX_FLOW_EN	0x10
++#define ESS_PORT_STATUS_RX_MAC_EN	0x08
++#define ESS_PORT_STATUS_TX_MAC_EN	0x04
++#define ESS_PORT_STATUS_SPEED_INV	0x03
++#define ESS_PORT_STATUS_SPEED_1000	0x02
++#define ESS_PORT_STATUS_SPEED_100	0x01
++#define ESS_PORT_STATUS_SPEED_10	0x00
++
++#define ESS_PORT_1G_FDX      (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
++			       ESS_PORT_STATUS_TX_FLOW_EN  | ESS_PORT_STATUS_RX_MAC_EN  | \
++			       ESS_PORT_STATUS_TX_MAC_EN   | ESS_PORT_STATUS_SPEED_1000)
++
++#define PHY_STATUS_REG			0x11
++#define PHY_STATUS_SPEED		0xC000
++#define PHY_STATUS_SPEED_SHIFT		14
++#define PHY_STATUS_DUPLEX		0x2000
++#define PHY_STATUS_DUPLEX_SHIFT	13
++#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
++#define PHY_STATUS_CARRIER		0x0400
++#define PHY_STATUS_CARRIER_SHIFT	10
++
++/* Port lookup control registers */
++#define ESS_PORT0_LOOKUP_CTRL	0x0660
++#define ESS_PORT1_LOOKUP_CTRL	0x066C
++#define ESS_PORT2_LOOKUP_CTRL	0x0678
++#define ESS_PORT3_LOOKUP_CTRL	0x0684
++#define ESS_PORT4_LOOKUP_CTRL	0x0690
++#define ESS_PORT5_LOOKUP_CTRL	0x069C
++
++#define ESS_PORT0_HEADER_CTRL	0x009C
++
++#define ESS_PORTS_ALL		0x3f
++
++#define ESS_FWD_CTRL1		0x0624
++#define   ESS_FWD_CTRL1_UC_FLOOD		BITS(0, 7)
++#define   ESS_FWD_CTRL1_UC_FLOOD_S		0
++#define   ESS_FWD_CTRL1_MC_FLOOD		BITS(8, 7)
++#define   ESS_FWD_CTRL1_MC_FLOOD_S		8
++#define   ESS_FWD_CTRL1_BC_FLOOD		BITS(16, 7)
++#define   ESS_FWD_CTRL1_BC_FLOOD_S		16
++#define   ESS_FWD_CTRL1_IGMP			BITS(24, 7)
++#define   ESS_FWD_CTRL1_IGMP_S			24
++
+ #endif /* _ESS_EDMA_H_ */

target/linux/ipq40xx/patches-4.14/713-essedma-Disable-TCP-segmentation-offload-for-IPv6.patch

@@ -0,0 +1,46 @@
+From: Sven Eckelmann <sven@narfation.org>
+Date: Tue, 9 Jun 2020 14:08:44 +0200
+Subject: essedma: Disable TCP segmentation offload for IPv6
+
+It was noticed that the the whole MAC can hang when transferring data from
+one ar40xx port (WAN ports) to the CPU and from the CPU back to another
+ar40xx port (LAN ports). The CPU was doing only NATing in that process.
+
+Usually, the problem first starts with a simple data corruption:
+
+  $ wget https://cdimage.debian.org/debian-cd/current/amd64/iso-cd/debian-10.4.0-amd64-netinst.iso -O /dev/null
+  ...
+  Connecting to saimei.ftp.acc.umu.se (saimei.ftp.acc.umu.se)|2001:6b0:19::138|:443... connected.
+  ...
+  Read  error at byte 48807936/352321536 (Decryption has failed.). Retrying.
+
+But after a short while, the whole MAC will stop to react. No traffic can
+be transported anymore from the CPU port from/to the AR40xx PHY/switch and
+the MAC has to be resetted.
+
+Signed-off-by: Sven Eckelmann <sven@narfation.org>
+
+--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
++++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
+@@ -972,17 +972,14 @@ static int edma_axi_probe(struct platfor
+ 		edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
+ 				      | NETIF_F_HW_VLAN_CTAG_TX
+ 				      | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
+-				      NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO;
++				      NETIF_F_TSO | NETIF_F_GRO;
+ 		edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
+ 				NETIF_F_HW_VLAN_CTAG_RX
+-				| NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+-				NETIF_F_GRO;
++				| NETIF_F_SG | NETIF_F_TSO | NETIF_F_GRO;
+ 		edma_netdev[i]->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG |
+-					   NETIF_F_TSO | NETIF_F_TSO6 |
+-					   NETIF_F_GRO;
++					   NETIF_F_TSO | NETIF_F_GRO;
+ 		edma_netdev[i]->wanted_features = NETIF_F_HW_CSUM | NETIF_F_SG |
+-					     NETIF_F_TSO | NETIF_F_TSO6 |
+-					     NETIF_F_GRO;
++					     NETIF_F_TSO | NETIF_F_GRO;
+ 
+ #ifdef CONFIG_RFS_ACCEL
+ 		edma_netdev[i]->features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;

target/linux/ipq40xx/patches-4.14/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch

@@ -0,0 +1,429 @@
+From e73682ec4455c34f3f3edc7f40d90ed297521012 Mon Sep 17 00:00:00 2001
+From: Senthilkumar N L <snlakshm@codeaurora.org>
+Date: Tue, 6 Jan 2015 12:52:23 +0530
+Subject: [PATCH] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
+
+These drivers handles control and configuration of the HS
+and SS USB PHY transceivers.
+
+Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+---
+Changed:
+	- replaced spaces with tabs
+	- remove emulation and host variables
+---
+ drivers/usb/phy/Kconfig          |  11 ++
+ drivers/usb/phy/Makefile         |   2 +
+ drivers/usb/phy/phy-qca-baldur.c | 233 +++++++++++++++++++++++++++++++++++++++
+ drivers/usb/phy/phy-qca-uniphy.c | 141 +++++++++++++++++++++++
+ 4 files changed, 387 insertions(+)
+ create mode 100644 drivers/usb/phy/phy-qca-baldur.c
+ create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
+
+--- a/drivers/usb/phy/Kconfig
++++ b/drivers/usb/phy/Kconfig
+@@ -188,6 +188,17 @@ config USB_MXS_PHY
+ 
+ 	  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
+ 
++config USB_IPQ4019_PHY
++	tristate "IPQ4019 PHY wrappers support"
++	depends on (USB || USB_GADGET) && ARCH_QCOM
++	select USB_PHY
++	help
++	  Enable this to support the USB PHY transceivers on QCA961x chips.
++	  It handles PHY initialization, clock management required after
++	  resetting the hardware and power management.
++	  This driver is required even for peripheral only or host only
++	  mode configurations.
++
+ config USB_ULPI
+ 	bool "Generic ULPI Transceiver Driver"
+ 	depends on ARM || ARM64
+--- a/drivers/usb/phy/Makefile
++++ b/drivers/usb/phy/Makefile
+@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS)		+= phy-gpio
+ obj-$(CONFIG_USB_ISP1301)		+= phy-isp1301.o
+ obj-$(CONFIG_USB_MSM_OTG)		+= phy-msm-usb.o
+ obj-$(CONFIG_USB_QCOM_8X16_PHY)	+= phy-qcom-8x16-usb.o
++obj-$(CONFIG_USB_IPQ4019_PHY)		+= phy-qca-baldur.o
++obj-$(CONFIG_USB_IPQ4019_PHY)		+= phy-qca-uniphy.o
+ obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o
+ obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
+ obj-$(CONFIG_USB_ULPI)			+= phy-ulpi.o
+--- /dev/null
++++ b/drivers/usb/phy/phy-qca-baldur.c
+@@ -0,0 +1,233 @@
++/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/usb/phy.h>
++#include <linux/reset.h>
++#include <linux/of_device.h>
++
++/**
++ *  USB Hardware registers
++ */
++#define PHY_CTRL0_ADDR	0x000
++#define PHY_CTRL1_ADDR	0x004
++#define PHY_CTRL2_ADDR	0x008
++#define PHY_CTRL3_ADDR	0x00C
++#define PHY_CTRL4_ADDR	0x010
++#define PHY_MISC_ADDR	0x024
++#define PHY_IPG_ADDR	0x030
++
++#define PHY_CTRL0_VAL	0xA4600015
++#define PHY_CTRL1_VAL	0x09500000
++#define PHY_CTRL2_VAL	0x00058180
++#define PHY_CTRL3_VAL	0x6DB6DCD6
++#define PHY_CTRL4_VAL	0x836DB6DB
++#define PHY_MISC_VAL	0x3803FB0C
++#define PHY_IPG_VAL	0x47323232
++
++#define USB30_HS_PHY_HOST_MODE	(0x01 << 21)
++#define USB20_HS_PHY_HOST_MODE	(0x01 << 5)
++
++/* used to differentiate between USB3 HS and USB2 HS PHY */
++struct qca_baldur_hs_data {
++	unsigned int usb3_hs_phy;
++	unsigned int phy_config_offset;
++};
++
++struct qca_baldur_hs_phy {
++	struct device *dev;
++	struct usb_phy phy;
++
++	void __iomem *base;
++	void __iomem *qscratch_base;
++
++	struct reset_control *por_rst;
++	struct reset_control *srif_rst;
++
++	const struct qca_baldur_hs_data *data;
++};
++
++#define phy_to_dw_phy(x) container_of((x), struct qca_baldur_hs_phy, phy)
++
++static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
++{
++	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
++
++	return readl(phy->base + reg);
++}
++
++static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
++{
++	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
++
++	writel(val, phy->base + reg);
++	return 0;
++}
++
++static int qca_baldur_hs_phy_init(struct usb_phy *x)
++{
++	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
++
++	/* assert HS PHY POR reset */
++	reset_control_assert(phy->por_rst);
++	msleep(10);
++
++	/* assert HS PHY SRIF reset */
++	reset_control_assert(phy->srif_rst);
++	msleep(10);
++
++	/* deassert HS PHY SRIF reset and program HS PHY registers */
++	reset_control_deassert(phy->srif_rst);
++	msleep(10);
++
++	/* perform PHY register writes */
++	writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
++	writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
++	writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
++	writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
++	writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
++	writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
++	writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
++
++	msleep(10);
++
++	/* de-assert USB3 HS PHY POR reset */
++	reset_control_deassert(phy->por_rst);
++
++	return 0;
++}
++
++static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
++{
++	struct platform_device *pdev = to_platform_device(phy->dev);
++	struct resource *res;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	phy->base = devm_ioremap_resource(phy->dev, res);
++	if (IS_ERR(phy->base))
++		return PTR_ERR(phy->base);
++
++	phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
++	if (IS_ERR(phy->por_rst))
++		return PTR_ERR(phy->por_rst);
++
++	phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
++	if (IS_ERR(phy->srif_rst))
++		return PTR_ERR(phy->srif_rst);
++
++	return 0;
++}
++
++static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
++{
++	reset_control_assert(phy->srif_rst);
++	reset_control_assert(phy->por_rst);
++}
++
++static int qca_baldur_hs_remove(struct platform_device *pdev)
++{
++	struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
++
++	usb_remove_phy(&phy->phy);
++	return 0;
++}
++
++static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
++{
++	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
++
++	qca_baldur_hs_put_resources(phy);
++}
++
++static struct usb_phy_io_ops qca_baldur_io_ops = {
++	.read = qca_baldur_phy_read,
++	.write = qca_baldur_phy_write,
++};
++
++static const struct qca_baldur_hs_data usb3_hs_data = {
++	.usb3_hs_phy = 1,
++	.phy_config_offset = USB30_HS_PHY_HOST_MODE,
++};
++
++static const struct qca_baldur_hs_data usb2_hs_data = {
++	.usb3_hs_phy = 0,
++	.phy_config_offset = USB20_HS_PHY_HOST_MODE,
++};
++
++static const struct of_device_id qca_baldur_hs_id_table[] = {
++	{ .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
++	{ .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
++	{ /* Sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
++
++static int qca_baldur_hs_probe(struct platform_device *pdev)
++{
++	const struct of_device_id *match;
++	struct qca_baldur_hs_phy *phy;
++	int err;
++
++	match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
++	if (!match)
++		return -ENODEV;
++
++	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
++	if (!phy)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, phy);
++	phy->dev = &pdev->dev;
++
++	phy->data = match->data;
++
++	err = qca_baldur_hs_get_resources(phy);
++	if (err < 0) {
++		dev_err(&pdev->dev, "failed to request resources: %d\n", err);
++		return err;
++	}
++
++	phy->phy.dev = phy->dev;
++	phy->phy.label = "qca-baldur-hsphy";
++	phy->phy.init = qca_baldur_hs_phy_init;
++	phy->phy.shutdown = qca_baldur_hs_phy_shutdown;
++	phy->phy.type = USB_PHY_TYPE_USB2;
++	phy->phy.io_ops = &qca_baldur_io_ops;
++
++	err = usb_add_phy_dev(&phy->phy);
++	return err;
++}
++
++static struct platform_driver qca_baldur_hs_driver = {
++	.probe		= qca_baldur_hs_probe,
++	.remove		= qca_baldur_hs_remove,
++	.driver		= {
++		.name	= "qca-baldur-hsphy",
++		.owner	= THIS_MODULE,
++		.of_match_table = qca_baldur_hs_id_table,
++	},
++};
++
++module_platform_driver(qca_baldur_hs_driver);
++
++MODULE_ALIAS("platform:qca-baldur-hsphy");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
+--- /dev/null
++++ b/drivers/usb/phy/phy-qca-uniphy.c
+@@ -0,0 +1,135 @@
++/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/usb/phy.h>
++#include <linux/reset.h>
++#include <linux/of_device.h>
++
++struct qca_uni_ss_phy {
++	struct usb_phy phy;
++	struct device *dev;
++
++	void __iomem *base;
++
++	struct reset_control *por_rst;
++};
++
++#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
++
++static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
++{
++	struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
++
++	/* assert SS PHY POR reset */
++	reset_control_assert(phy->por_rst);
++}
++
++static int qca_uni_ss_phy_init(struct usb_phy *x)
++{
++	struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
++
++	/* assert SS PHY POR reset */
++	reset_control_assert(phy->por_rst);
++
++	msleep(20);
++
++	/* deassert SS PHY POR reset */
++	reset_control_deassert(phy->por_rst);
++
++	return 0;
++}
++
++static int qca_uni_ss_get_resources(struct platform_device *pdev,
++		struct qca_uni_ss_phy *phy)
++{
++	struct resource *res;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	phy->base = devm_ioremap_resource(phy->dev, res);
++	if (IS_ERR(phy->base))
++		return PTR_ERR(phy->base);
++
++	phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
++	if (IS_ERR(phy->por_rst))
++		return PTR_ERR(phy->por_rst);
++
++	return 0;
++}
++
++static int qca_uni_ss_remove(struct platform_device *pdev)
++{
++	struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
++
++	usb_remove_phy(&phy->phy);
++	return 0;
++}
++
++static const struct of_device_id qca_uni_ss_id_table[] = {
++	{ .compatible = "qca,uni-ssphy" },
++	{ /* Sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
++
++static int qca_uni_ss_probe(struct platform_device *pdev)
++{
++	struct qca_uni_ss_phy *phy;
++	int ret;
++
++	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
++	if (!phy)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, phy);
++	phy->dev = &pdev->dev;
++
++	ret = qca_uni_ss_get_resources(pdev, phy);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
++		return ret;
++	}
++
++	phy->phy.dev = phy->dev;
++	phy->phy.label = "qca-uni-ssphy";
++	phy->phy.init = qca_uni_ss_phy_init;
++	phy->phy.shutdown = qca_uni_ss_phy_shutdown;
++	phy->phy.type = USB_PHY_TYPE_USB3;
++
++	ret = usb_add_phy_dev(&phy->phy);
++	return ret;
++}
++
++static struct platform_driver qca_uni_ss_driver = {
++	.probe = qca_uni_ss_probe,
++	.remove	= qca_uni_ss_remove,
++	.driver = {
++		.name = "qca-uni-ssphy",
++		.owner = THIS_MODULE,
++		.of_match_table = qca_uni_ss_id_table,
++	},
++};
++
++module_platform_driver(qca_uni_ss_driver);
++
++MODULE_ALIAS("platform:qca-uni-ssphy");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");

target/linux/ipq40xx/patches-4.14/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch

@@ -0,0 +1,25 @@
+From 08c18ab774368feb610d1eb952957bb1bb35129f Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 19 Nov 2016 00:52:35 +0100
+Subject: [PATCH 37/38] usb: dwc3: register qca,ipq4019-dwc3 in dwc3-of-simple
+
+For host mode, the dwc3 found in the IPQ4019 can be driven
+by the dwc3-of-simple module. It will get more tricky for
+OTG since they'll need to enable VBUS and reconfigure the
+registers.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/usb/dwc3/dwc3-of-simple.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/usb/dwc3/dwc3-of-simple.c
++++ b/drivers/usb/dwc3/dwc3-of-simple.c
+@@ -177,6 +177,7 @@ static const struct dev_pm_ops dwc3_of_s
+ 
+ static const struct of_device_id of_dwc3_simple_match[] = {
+ 	{ .compatible = "qcom,dwc3" },
++	{ .compatible = "qca,ipq4019-dwc3" },
+ 	{ .compatible = "rockchip,rk3399-dwc3" },
+ 	{ .compatible = "xlnx,zynqmp-dwc3" },
+ 	{ .compatible = "cavium,octeon-7130-usb-uctl" },

target/linux/ipq40xx/patches-4.14/850-soc-add-qualcomm-syscon.patch

@@ -0,0 +1,177 @@
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st
+ obj-$(CONFIG_QCOM_SMP2P)	+= smp2p.o
+ obj-$(CONFIG_QCOM_SMSM)	+= smsm.o
+ obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
++obj-$(CONFIG_QCOM_TCSR)	 += qcom_tcsr.o
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -78,6 +78,13 @@ config QCOM_SMSM
+ 	  Say yes here to support the Qualcomm Shared Memory State Machine.
+ 	  The state machine is represented by bits in shared memory.
+ 
++config QCOM_TCSR
++	tristate "QCOM Top Control and Status Registers"
++	depends on ARCH_QCOM
++	help
++	  Say y here to enable TCSR support.  The TCSR provides control
++	  functions for various peripherals.
++
+ config QCOM_WCNSS_CTRL
+ 	tristate "Qualcomm WCNSS control driver"
+ 	depends on ARCH_QCOM
+--- /dev/null
++++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,98 @@
++/*
++ * Copyright (c) 2014, The Linux foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License rev 2 and
++ * only rev 2 as published by the free Software foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define TCSR_USB_PORT_SEL	0xb0
++#define TCSR_USB_HSPHY_CONFIG	0xC
++
++#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0
++#define TCSR_ESS_INTERFACE_SEL_MASK     0xf
++
++#define TCSR_WIFI0_GLB_CFG_OFFSET	0x0
++#define TCSR_WIFI1_GLB_CFG_OFFSET	0x4
++#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2	0x4
++
++static int tcsr_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	const struct device_node *node = pdev->dev.of_node;
++	void __iomem *base;
++	u32 val;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
++		dev_err(&pdev->dev, "setting usb port select = %d\n", val);
++		writel(val, base + TCSR_USB_PORT_SEL);
++	}
++
++	if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
++		dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
++		writel(val, base + TCSR_USB_HSPHY_CONFIG);
++	}
++
++	if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
++		u32 tmp = 0;
++		dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
++		tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++		tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
++		tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
++		writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++        }
++
++	if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
++		dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
++		writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
++		writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
++	}
++
++	if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
++		dev_info(&pdev->dev,
++			"setting wifi_noc_memtype_m0_m2 = %x\n", val);
++		writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
++	}
++
++	return 0;
++}
++
++static const struct of_device_id tcsr_dt_match[] = {
++	{ .compatible = "qcom,tcsr", },
++	{ },
++};
++
++MODULE_DEVICE_TABLE(of, tcsr_dt_match);
++
++static struct platform_driver tcsr_driver = {
++	.driver = {
++		.name		= "tcsr",
++		.owner		= THIS_MODULE,
++		.of_match_table	= tcsr_dt_match,
++	},
++	.probe = tcsr_probe,
++};
++
++module_platform_driver(tcsr_driver);
++
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_DESCRIPTION("QCOM TCSR driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,48 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_TCSR_H
++#define __DT_BINDINGS_QCOM_TCSR_H
++
++#define TCSR_USB_SELECT_USB3_P0		0x1
++#define TCSR_USB_SELECT_USB3_P1		0x2
++#define TCSR_USB_SELECT_USB3_DUAL	0x3
++
++/* IPQ40xx HS PHY Mode Select */
++#define TCSR_USB_HSPHY_HOST_MODE	0x00E700E7
++#define TCSR_USB_HSPHY_DEVICE_MODE	0x00C700E7
++
++/* IPQ40xx ess interface mode select */
++#define TCSR_ESS_PSGMII              0
++#define TCSR_ESS_PSGMII_RGMII5       1
++#define TCSR_ESS_PSGMII_RMII0        2
++#define TCSR_ESS_PSGMII_RMII1        4
++#define TCSR_ESS_PSGMII_RMII0_RMII1  6
++#define TCSR_ESS_PSGMII_RGMII4       9
++
++/*
++ * IPQ40xx WiFi Global Config
++ * Bit 30:AXID_EN
++ * Enable AXI master bus Axid translating to confirm all txn submitted by order
++ * Bit 24: Use locally generated socslv_wxi_bvalid
++ * 1:  use locally generate socslv_wxi_bvalid for performance.
++ * 0:  use SNOC socslv_wxi_bvalid.
++ */
++#define TCSR_WIFI_GLB_CFG		0x41000000
++
++/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
++#define TCSR_WIFI_NOC_MEMTYPE_M0_M2	0x02222222
++
++/* TCSR A/B REG */
++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
++
++#endif

target/linux/ipq40xx/patches-4.14/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch

@@ -0,0 +1,42 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -15,12 +15,39 @@
+  */
+ 
+ #include "qcom-ipq4019.dtsi"
++#include <dt-bindings/soc/qcom,tcsr.h>
+ 
+ / {
+ 	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+ 	compatible = "qcom,ipq4019";
+ 
+ 	soc {
++		tcsr@194b000 {
++			/* select hostmode */
++			compatible = "qcom,tcsr";
++			reg = <0x194b000 0x100>;
++			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
++			status = "ok";
++		};
++
++		ess_tcsr@1953000 {
++			compatible = "qcom,tcsr";
++			reg = <0x1953000 0x1000>;
++			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
++		};
++
++		tcsr@1949000 {
++			compatible = "qcom,tcsr";
++			reg = <0x1949000 0x100>;
++			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
++		};
++
++		tcsr@1957000 {
++			compatible = "qcom,tcsr";
++			reg = <0x1957000 0x100>;
++			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
++		};
++
+ 		rng@22000 {
+ 			status = "ok";
+ 		};

target/linux/ipq40xx/patches-4.14/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch

@@ -0,0 +1,17 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -93,14 +93,6 @@
+ 			pinctrl-names = "default";
+ 			status = "ok";
+ 			cs-gpios = <&tlmm 54 0>;
+-
+-			mx25l25635e@0 {
+-				#address-cells = <1>;
+-				#size-cells = <1>;
+-				reg = <0>;
+-				compatible = "mx25l25635e";
+-				spi-max-frequency = <24000000>;
+-			};
+ 		};
+ 
+ 		serial@78af000 {

target/linux/ipq40xx/patches-4.14/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch

@@ -0,0 +1,74 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -19,4 +19,71 @@
+ / {
+ 	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ 
++	memory {
++		device_type = "memory";
++		reg = <0x80000000 0x10000000>;
++	};
++};
++
++&spi_0 {
++	mx25l25635f@0 {
++		compatible = "mx25l25635f", "jedec,spi-nor";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		reg = <0>;
++		spi-max-frequency = <24000000>;
++
++		SBL1@0 {
++			label = "SBL1";
++			reg = <0x0 0x40000>;
++			read-only;
++		};
++		MIBIB@40000 {
++			label = "MIBIB";
++			reg = <0x40000 0x20000>;
++			read-only;
++		};
++		QSEE@60000 {
++			label = "QSEE";
++			reg = <0x60000 0x60000>;
++			read-only;
++		};
++		CDT@c0000 {
++			label = "CDT";
++			reg = <0xc0000 0x10000>;
++			read-only;
++		};
++		DDRPARAMS@d0000 {
++			label = "DDRPARAMS";
++			reg = <0xd0000 0x10000>;
++			read-only;
++		};
++		APPSBLENV@e0000 {
++			label = "APPSBLENV";
++			reg = <0xe0000 0x10000>;
++			read-only;
++		};
++		APPSBL@f0000 {
++			label = "APPSBL";
++			reg = <0xf0000 0x80000>;
++			read-only;
++		};
++		ART@170000 {
++			label = "ART";
++			reg = <0x170000 0x10000>;
++			read-only;
++		};
++		kernel@180000 {
++			label = "kernel";
++			reg = <0x180000 0x400000>;
++		};
++		rootfs@580000 {
++			label = "rootfs";
++			reg = <0x580000 0x1600000>;
++		};
++		firmware@180000 {
++			label = "firmware";
++			reg = <0x180000 0x1a00000>;
++		};
++	};
+ };

target/linux/ipq40xx/patches-4.14/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch

@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -18,6 +18,7 @@
+ 
+ / {
+ 	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
++	compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
+ 
+ 	memory {
+ 		device_type = "memory";

target/linux/ipq40xx/patches-4.14/864-09-dts-ipq4019-ap-dk01.1-enable-ethernet.patch

@@ -0,0 +1,25 @@
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -121,6 +121,22 @@
+ 			status = "ok";
+ 		};
+ 
++		mdio@90000 {
++			status = "okay";
++		};
++
++		ess-switch@c000000 {
++			status = "okay";
++		};
++
++		ess-psgmii@98000 {
++			status = "okay";
++		};
++
++		edma@c080000 {
++			status = "okay";
++		};
++
+ 		usb3_ss_phy: ssphy@9a000 {
+ 			status = "ok";
+ 		};

target/linux/ipq40xx/patches-4.14/865-ARM-dts-ipq4019-Add-TZ-and-SMEM-reserved-regions.patch

@@ -0,0 +1,88 @@
+From fc566294610fa49e9d8c31c4ecc9c82f49b11f59 Mon Sep 17 00:00:00 2001
+From: Sven Eckelmann <sven.eckelmann@openmesh.com>
+Date: Wed, 18 Apr 2018 09:10:44 +0200
+Subject: [PATCH] ARM: dts: ipq4019: Add TZ and SMEM reserved regions
+
+The QSEE (trustzone) is started on IPQ4019 before Linux is started.
+According to QCA, it is placed in in the the memory region
+0x87e80000-0x88000000 and must not be accessed directly. There is an
+additional memory region 0x87e00000-0x87E80000 smem which which can be used
+for communication with the TZ. The driver for the latter is not yet ready
+but it is still not allowed to use this memory region like any other
+memory region.
+
+Not reserving this memory region either leads to kernel crashes, kernel
+hangs (often during the boot) or bus errors for userspace programs. The
+latter happens when a program is using a memory region which is mapped to
+these physical memory regions.
+
+  [  571.758058] Unhandled fault: imprecise external abort (0xc06) at 0x01715ff8
+  [  571.758099] pgd = cebec000
+  [  571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f
+  Bus error
+
+Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
+
+Forwarded: https://patchwork.kernel.org/patch/10347459/
+---
+Cc: Sricharan Ramabadhran <srichara@qti.qualcomm.com>
+Cc: Senthilkumar N L <snlakshm@qti.qualcomm.com>
+
+There are additional memory regions which have to be initialized first by
+Linux. So they are currently not used. We were told by QCA that the
+features QSDK uses them for are:
+
+* crash dump feature
+  - a couple of regions used when 'qca,scm_restart_reason' dt node has the
+    value 'dload_status' not set to 1
+    + apps_bl <0x87000000 0x400000>
+    + sbl <0x87400000 0x100000>
+    + cnss_debug <0x87400000 0x100000>
+    + cpu_context_dump <0x87b00000 0x080000>
+  - required driver not available in Linux
+  - safe to remove
+* QSEE app execution
+  - region tz_apps <0x87b80000 0x280000>
+  - required driver not available in Linux
+  - safe to remove
+* communication with TZ/QSEE
+  - region smem <0x87b80000 0x280000>
+  - driver changes not yet upstreamed
+  - must not be removed because any access can crash kernel/program
+* trustzone (QSEE) private memory
+  - region tz <0x87e80000 0x180000>
+  - must not be removed because any access can crash kernel/program
+
+The problem with the missing regions was reported in 2016 [1]. So maybe
+this change qualifies for a stable@vger.kernel.org submission.
+
+[1] https://www.spinics.net/lists/linux-arm-msm/msg21536.html
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -23,6 +23,22 @@
+ 	compatible = "qcom,ipq4019";
+ 	interrupt-parent = <&intc>;
+ 
++	reserved-memory {
++		#address-cells = <0x1>;
++		#size-cells = <0x1>;
++		ranges;
++
++		smem_region: smem@87e00000 {
++			reg = <0x87e00000 0x080000>;
++			no-map;
++		};
++
++		tz@87e80000 {
++			reg = <0x87e80000 0x180000>;
++			no-map;
++		};
++	};
++
+ 	aliases {
+ 		spi0 = &spi_0;
+ 		spi1 = &spi_1;

target/linux/ipq40xx/patches-4.14/900-clk-fix.patch

@@ -0,0 +1,111 @@
+From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Thu, 11 Mar 2018 14:41:31 +0100
+Subject: [PATCH] clk: fix apss cpu overclocking
+
+There's an interaction issue between the clk changes:"
+clk: qcom: ipq4019: Add the apss cpu pll divider clock node
+clk: qcom: ipq4019: remove fixed clocks and add pll clocks
+" and the cpufreq-dt.
+
+cpufreq-dt is now spamming the kernel-log with the following:
+
+[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
+for freq 761142857 (-34)
+
+This only happens on certain devices like the Compex WPJ428
+and AVM FritzBox!4040. However, other devices like the Asus
+RT-AC58U and Meraki MR33 work just fine.
+
+The issue stem from the fact that all higher CPU-Clocks
+are achieved by switching the clock-parent to the P_DDRPLLAPSS
+(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
+as part of the DDR calibration.
+
+For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
+at round 533 MHz (ddrpllsdcc = 190285714 Hz).
+
+whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
+clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
+
+This patch attempts to fix the issue by modifying
+clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
+to use a new qcom_find_freq_close() function, which returns the closest
+matching frequency, instead of the next higher. This way, the SoC in
+the FB4040 (with its max clock speed of 710.4 MHz) will no longer
+try to overclock to 761 MHz.
+
+Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fe
+ 	.reg = 0x2f020,
+ };
+ 
++
++const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
++					     unsigned long rate)
++{
++	const struct freq_tbl *last = NULL;
++
++	for ( ; f->freq; f++) {
++		if (rate == f->freq)
++			return f;
++
++		if (f->freq > rate) {
++			if (!last ||
++			   (f->freq - rate) < (rate - last->freq))
++				return f;
++			else
++				return last;
++		}
++		last = f;
++	}
++
++	return last;
++}
++
+ /*
+  * Round rate function for APSS CPU PLL Clock divider.
+  * It looks up the frequency table and returns the next higher frequency
+@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struc
+ 	struct clk_hw *p_hw;
+ 	const struct freq_tbl *f;
+ 
+-	f = qcom_find_freq(pll->freq_tbl, rate);
++	f = qcom_find_freq_close(pll->freq_tbl, rate);
+ 	if (!f)
+ 		return -EINVAL;
+ 
+@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct c
+ 	u32 mask;
+ 	int ret;
+ 
+-	f = qcom_find_freq(pll->freq_tbl, rate);
++	f = qcom_find_freq_close(pll->freq_tbl, rate);
+ 	if (!f)
+ 		return -EINVAL;
+ 
+@@ -1315,6 +1338,7 @@ static unsigned long
+ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ 			unsigned long parent_rate)
+ {
++	const struct freq_tbl *f;
+ 	struct clk_fepll *pll = to_clk_fepll(hw);
+ 	u32 cdiv, pre_div;
+ 	u64 rate;
+@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+ 	rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
+ 	do_div(rate, pre_div);
+ 
+-	return rate;
++	f = qcom_find_freq_close(pll->freq_tbl, rate);
++	if (!f)
++		return rate;
++
++	return f->freq;
+ };
+ 
+ static const struct clk_ops clk_regmap_cpu_div_ops = {

target/linux/ipq40xx/patches-4.14/902-essedma-alloc-skb-ip-align.patch

@@ -0,0 +1,21 @@
+From 17681f0bb474d0d227f07369144149d1555d8bce Mon Sep 17 00:00:00 2001
+From: Chen Minqiang <ptpt52@gmail.com>
+Date: Sun, 17 Jun 2018 04:14:13 +0800
+Subject: [PATCH] essedma: alloc skb ip align
+
+Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
+---
+ drivers/net/ethernet/qualcomm/essedma/edma.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
++++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
+@@ -201,7 +201,7 @@ static int edma_alloc_rx_buf(struct edma
+ 			skb = sw_desc->skb;
+ 		} else {
+ 			/* alloc skb */
+-			skb = netdev_alloc_skb(edma_netdev[0], length);
++			skb = netdev_alloc_skb_ip_align(edma_netdev[0], length);
+ 			if (!skb) {
+ 				/* Better luck next round */
+ 				break;

target/linux/ipq40xx/patches-4.14/997-device_tree_cmdline.patch

@@ -0,0 +1,12 @@
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1130,6 +1130,9 @@ int __init early_init_dt_scan_chosen(uns
+ 	p = of_get_flat_dt_prop(node, "bootargs", &l);
+ 	if (p != NULL && l > 0)
+ 		strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
++	p = of_get_flat_dt_prop(node, "bootargs-append", &l);
++	if (p != NULL && l > 0)
++		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+ 
+ 	/*
+ 	 * CONFIG_CMDLINE is meant to be a default in case nothing else

target/linux/ipq40xx/profiles/00-default.mk

@@ -0,0 +1,9 @@
+define Profile/Default
+  NAME:=Default Profile
+  PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most boards.
+endef
+$(eval $(call Profile,Default))