domenico/openwrt-18.06
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domenico
2025-06-24 15:51:28 +02:00
commit 22031d9dab
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67
target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch Normal file
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@@ -0,0 +1,67 @@
From 788d269aee4c612d5cd97b896ea5d22f19137097 Mon Sep 17 00:00:00 2001
From: Chaotian Jing <chaotian.jing@mediatek.com>
Date: Mon, 16 Oct 2017 09:46:34 +0800
Subject: [PATCH 155/224] mmc: mediatek: add busy_check support
bit7 of PATCH_BIT1 has different meaning in new design, to
compatible with previous platform, clear this bit in new
platform.
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
drivers/mmc/host/mtk-sd.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -318,6 +318,7 @@ struct mtk_mmc_compatible {
u32 pad_tune_reg;
bool async_fifo;
bool data_tune;
+ bool busy_check;
};
struct msdc_tune_para {
@@ -382,6 +383,7 @@ static const struct mtk_mmc_compatible m
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
.data_tune = false,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt8173_compat = {
@@ -390,6 +392,7 @@ static const struct mtk_mmc_compatible m
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
.data_tune = false,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt2701_compat = {
@@ -398,6 +401,7 @@ static const struct mtk_mmc_compatible m
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
.data_tune = true,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt2712_compat = {
@@ -406,6 +410,7 @@ static const struct mtk_mmc_compatible m
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
.data_tune = true,
+ .busy_check = true,
};
static const struct of_device_id msdc_of_ids[] = {
@@ -1277,6 +1282,8 @@ static void msdc_init_hw(struct msdc_hos
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
+ if (host->dev_comp->busy_check)
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
if (host->dev_comp->async_fifo) {
sdr_set_field(host->base + MSDC_PATCH_BIT2,
MSDC_PB2_RESPWAIT, 3);