Initial commit
This commit is contained in:
domenico
228
target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
Normal file
228
target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
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@@ -0,0 +1,228 @@
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/*
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* Aerohive HiveAP-330 Device Tree Source
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*
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "Aerohive HiveAP-330";
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compatible = "aerohive,hiveap-330";
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chosen {
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bootargs-override = "console=ttyS0,9600";
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};
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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reg = <0x0 0x40000>;
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label = "dtb";
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};
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partition@40000 {
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reg = <0x40000 0x40000>;
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label = "initrd";
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};
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partition@80000 {
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reg = <0x80000 0x27c0000>;
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label = "rootfs";
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};
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partition@2840000 {
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reg = <0x2840000 0x800000>;
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label = "kernel";
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};
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partition@3040000 {
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reg = <0x3040000 0xec0000>;
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label = "stock-jffs2";
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read-only;
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};
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hwinfo: partition@3f00000 {
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reg = <0x3f00000 0x20000>;
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label = "hw-info";
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read-only;
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};
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partition@3f20000 {
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reg = <0x3f20000 0x20000>;
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label = "boot-info";
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read-only;
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};
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partition@3f40000 {
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reg = <0x3f40000 0x20000>;
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label = "boot-info-backup";
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read-only;
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};
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partition@3f60000 {
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reg = <0x3f60000 0x20000>;
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label = "u-boot-env";
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};
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partition@3f80000 {
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reg = <0x3f80000 0x80000>;
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label = "u-boot";
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read-only;
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};
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firmware@0 {
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reg = <0x0 0x3040000>;
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label = "firmware";
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};
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};
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3100 {
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tpm@29 {
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compatible = "atmel,at97sc3204t";
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reg = <0x29>;
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};
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lp5521@32 {
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compatible = "national,lp5521";
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reg = <0x32>;
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clock-mode = /bits/ 8 <2>;
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chan0 {
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chan-name = "hiveap-330:red:tricolor0";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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};
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chan1 {
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chan-name = "hiveap-330:green:tricolor0";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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};
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chan2 {
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chan-name = "hiveap-330:blue:tricolor0";
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led-cur = /bits/ 8 <0x2f>;
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max-cur = /bits/ 8 <0x5f>;
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};
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};
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/* Most likely SoC boot config */
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eeprom@51 {
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compatible = "eeprom";
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reg = <0x51>;
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};
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <2 1 0 0>;
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reg = <0x2>;
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};
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};
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mdio@25000 {
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status = "disabled";
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};
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mdio@26000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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mtd-mac-address = <&hwinfo 0>;
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "okay";
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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mtd-mac-address = <&hwinfo 0>;
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mtd-mac-address-increment = <1>;
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};
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gpio0: gpio-controller@fc00 {
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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usb@23000 {
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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buttons {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 8 1>; /* active low */
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linux,code = <0x198>; /* KEY_RESTART */
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};
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};
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};
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/include/ "fsl/p1020si-post.dtsi"
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@@ -0,0 +1,262 @@
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/*
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* TP-Link TL-WDR4900 v1 Device Tree Source
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*
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* Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/p1010si-pre.dtsi"
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/ {
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model = "TP-Link TL-WDR4900 v1";
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compatible = "tplink,tl-wdr4900-v1";
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chosen {
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bootargs = "console=ttyS0,115200";
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/*
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linux,stdout-path = "/soc@ffe00000/serial@4500";
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*/
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};
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aliases {
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spi0 = &spi0;
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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spi0: spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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u-boot@0 {
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reg = <0x0 0x0050000>;
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label = "u-boot";
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read-only;
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};
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dtb@50000 {
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reg = <0x00050000 0x00010000>;
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label = "dtb";
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read-only;
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};
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kernel@60000 {
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reg = <0x00060000 0x002a0000>;
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label = "kernel";
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};
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rootfs@300000 {
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reg = <0x00300000 0x00ce0000>;
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label = "rootfs";
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};
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config: config@fe0000 {
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reg = <0x00fe0000 0x00010000>;
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label = "config";
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read-only;
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};
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caldata@ff0000 {
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reg = <0x00ff0000 0x00010000>;
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label = "caldata";
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read-only;
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};
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firmware@60000 {
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reg = <0x00060000 0x00f80000>;
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label = "firmware";
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};
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};
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};
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gpio0: gpio-controller@fc00 {
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};
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usb@22000 {
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phy_type = "utmi";
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dr_mode = "host";
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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qca,ar8327-initvals = <
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0x00004 0x07600000 /* PAD0_MODE */
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0x00008 0x00000000 /* PAD5_MODE */
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0x0000c 0x01000000 /* PAD6_MODE */
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0x00010 0x40000000 /* POWER_ON_STRIP */
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0x00050 0xcf35cf35 /* LED_CTRL0 */
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0x00054 0xcf35cf35 /* LED_CTRL1 */
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0x00058 0xcf35cf35 /* LED_CTRL2 */
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0x0005c 0x03ffff00 /* LED_CTRL3 */
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0x0007c 0x0000007e /* PORT0_STATUS */
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0x00094 0x00000200 /* PORT6_STATUS */
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>;
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};
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};
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mdio@25000 {
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status = "disabled";
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};
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mdio@26000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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mtd-mac-address = <&config 0x144>;
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "disabled";
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};
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sdhc@2e000 {
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status = "disabled";
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};
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serial1: serial@4600 {
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status = "disabled";
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};
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can0: can@1c000 {
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status = "disabled";
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};
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can1: can@1d000 {
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status = "disabled";
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};
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ptp_clock@b0e00 {
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compatible = "fsl,etsec-ptp";
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reg = <0xb0e00 0xb0>;
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interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
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fsl,cksel = <1>;
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <2>;
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fsl,tmr-add = <0xcccccccd>;
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fsl,tmr-fiper1 = <0x3b9ac9fb>; /* 1PPS */
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <249999999>;
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};
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};
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pci0: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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ifc: ifc@ffe1e000 {
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status = "disabled";
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};
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leds {
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compatible = "gpio-leds";
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system {
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gpios = <&gpio0 2 1>; /* active low */
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label = "tp-link:blue:system";
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};
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usb1 {
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gpios = <&gpio0 3 1>; /* active low */
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label = "tp-link:green:usb1";
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};
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usb2 {
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gpios = <&gpio0 4 1>; /* active low */
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label = "tp-link:green:usb2";
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};
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usbpower {
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gpios = <&gpio0 10 1>; /* active low */
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label = "tp-link:usb:power";
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};
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};
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buttons {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 5 1>; /* active low */
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linux,code = <0x198>; /* KEY_RESTART */
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};
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rfkill {
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label = "RFKILL switch";
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gpios = <&gpio0 11 1>; /* active low */
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linux,code = <0xf7>; /* RFKill */
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};
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};
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};
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/include/ "fsl/p1010si-post.dtsi"
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/*
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* The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
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* related to the P1010.
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*
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* NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
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* datasheet states that the P1014 does not include the accelerated crypto
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* module (CAAM/SEC4) which is present in the P1010.
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*
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* NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
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* SEC4 module, but states that SoCs with System Version Register values
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* 0x80F10110 or 0x80F10120 do not have the security feature.
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*
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* All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
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* as: core rev 1.0, "P1014 (without security)".
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*
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* The SVR value is reported by uboot on the serial console.
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*/
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/ {
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soc: soc@ffe00000 {
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/delete-node/ crypto@30000; /* Pulled in by p1010si-post */
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||||
};
|
||||
};
|
||||
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