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domenico
2025-06-24 16:03:39 +02:00
commit f3256cdaf2
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126
package/boot/uboot-kirkwood/Makefile Normal file
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#
# Copyright (C) 2010-2014 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=2019.01
PKG_RELEASE:=2
PKG_HASH:=50bd7e5a466ab828914d080d5f6a432345b500e8fba1ad3b7b61e95e60d51c22
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=kirkwood
endef
define U-Boot/dockstar
NAME:=Seagate DockStar
BUILD_DEVICES:=seagate_dockstar
endef
define U-Boot/dockstar_second_stage
NAME:=Seagate DockStar (second stage)
BUILD_DEVICES:=seagate_dockstar
endef
define U-Boot/goflexhome
NAME:=the Seagate GoFlexHome/GoFlexNet
BUILD_DEVICES:=seagate_goflexhome seagate_goflexnet
endef
define U-Boot/ib62x0
NAME:=RaidSonic ICY BOX NAS6210 and NAS6220
BUILD_DEVICES:=raidsonic_ib-nas62x0
endef
define U-Boot/ib62x0_second_stage
NAME:=RaidSonic ICY BOX NAS6210 and NAS6220 (second stage)
BUILD_DEVICES:=raidsonic_ib-nas62x0
endef
define U-Boot/iconnect
NAME:=Iomega iConnect Wireless
BUILD_DEVICES:=iom_iconnect-1.1
endef
define U-Boot/iconnect_second_stage
NAME:=Iomega iConnect Wireless (second stage)
BUILD_DEVICES:=iom_iconnect-1.1
endef
define U-Boot/nsa310
NAME:=Zyxel NSA310
BUILD_DEVICES:=zyxel_nsa310b
endef
define U-Boot/nsa325
NAME:=Zyxel NSA325v1 and v2
BUILD_DEVICES:=zyxel_nsa325
endef
define U-Boot/pogo_e02
NAME:=Cloud Engines Pogoplug E02
BUILD_DEVICES:=cloudengines_pogoe02
endef
define U-Boot/pogo_e02_second_stage
NAME:=Cloud Engines Pogoplug E02 (second stage)
BUILD_DEVICES:=cloudengines_pogoe02
endef
define U-Boot/pogoplugv4
NAME:=Cloud Engines Pogoplug V4
BUILD_DEVICES:=cloudengines_pogoplugv4
endef
UBOOT_TARGETS := \
dockstar dockstar_second_stage \
goflexhome \
ib62x0 ib62x0_second_stage \
iconnect iconnect_second_stage \
nsa310 \
nsa325 \
pogo_e02 pogo_e02_second_stage \
pogoplugv4
define Build/Configure
$(if $(findstring _second_stage,$(BUILD_VARIANT)),
$(CP) \
$(PKG_BUILD_DIR)/configs/$(subst _second_stage,,$(BUILD_VARIANT))_defconfig \
$(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig
echo CONFIG_SECOND_STAGE=y >> $(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig
)
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
$(BUILD_VARIANT)_config V=1
endef
define Build/Compile
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
u-boot.kwb \
CROSS_COMPILE=$(TARGET_CROSS)
mkimage -A $(ARCH) -O linux -T kernel -C none \
-a 0x600000 -e 0x600000 \
-n 'U-Boot uImage' \
-d $(PKG_BUILD_DIR)/u-boot.bin $(PKG_BUILD_DIR)/u-boot.img
endef
define Package/u-boot/install
$(CP) \
$(PKG_BUILD_DIR)/u-boot.bin \
$(PKG_BUILD_DIR)/u-boot.kwb \
$(PKG_BUILD_DIR)/u-boot.img \
$(1)/
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/kwboot $(STAGING_DIR_HOST)/bin/
endef
$(eval $(call BuildPackage/U-Boot))

38
package/boot/uboot-kirkwood/patches/001-ARM-kirkwood-disable-dcache-for-Kirkwood-boards.patch Normal file
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From 599f7aa541bb5a658cbfd2af73bd9d2f6e828d43 Mon Sep 17 00:00:00 2001
From: Chris Packham <judge.packham@gmail.com>
Date: Mon, 18 Mar 2019 20:51:58 +1300
Subject: [PATCH] ARM: kirkwood: disable dcache for Kirkwood boards
Prior to commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.
Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/arm/mach-kirkwood/include/mach/config.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index fcd903887b..aea60688c2 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -26,6 +26,12 @@
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+/*
+ * Disable the dcache. Currently the network driver (mvgbe.c) and USB
+ * EHCI driver (ehci-marvell.c) and possibly others rely on the data
+ * cache being disabled.
+ */
+#define CONFIG_SYS_DCACHE_OFF
/*
* By default kwbimage.cfg from board specific folder is used
--
2.20.1

668
package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch Normal file
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arm: kirkwood: add ZyXEL NSA310 device
This patch add ZyXEL NSA310 1-Bay Media Server
The ZyXEL NSA310 device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1200Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Realtek
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 5 Status LED (green/red)
- 1 Copy/Sync button
- 1 Reset button
- 2 SATA II port (1 internal and 1 external eSata)
- 2 USB 2.0 ports (1 front and 1 back)
- Smart fan
Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
NOTE: this patch is ready for upstream, LEDE-specific parts are in
another patch
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -56,6 +56,9 @@ config TARGET_GOFLEXHOME
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310
+ bool "Zyxel NSA310 Board"
+
config TARGET_NSA310S
bool "Zyxel NSA310S"
@@ -86,6 +89,7 @@ source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
--- /dev/null
+++ b/board/zyxel/nsa310/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NSA310
+
+config SYS_BOARD
+ default "nsa310"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310"
+
+endif
--- /dev/null
+++ b/board/zyxel/nsa310/MAINTAINERS
@@ -0,0 +1,6 @@
+NSA310 BOARD
+M: Alberto Bursi <alberto.bursi@outlook.it>
+S: Maintained
+F: board/zyxel/nsa310/
+F: include/configs/nsa310.h
+F: configs/nsa310_defconfig
--- /dev/null
+++ b/board/zyxel/nsa310/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310.o
--- /dev/null
+++ b/board/zyxel/nsa310/kwbimage.cfg
@@ -0,0 +1,166 @@
+#
+# Copyright (C) 2013 Rafal Kazmierowski
+#
+# Based on guruplug.c originally written by
+# Siddarth Gore <gores@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+#BOOT_FROM uart
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43010c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000c # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db
+DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low)
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI
+DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+++ b/board/zyxel/nsa310/nsa310.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2013 Rafal Kazmierowski
+ *
+ * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
+ * originally written by
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
+ NSA310_OE_LOW, NSA310_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ /* (all LEDs & power off active high) */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA, /* PCF8563 RTC chip */
+ MPP9_TW_SCK, /* connected to TWSI */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* SATA2 LED (green) */
+ MPP13_GPIO, /* SATA2 LED (red) */
+ MPP14_GPIO, /* MCU DATA pin (in) */
+ MPP15_GPIO, /* USB LED (green) */
+ MPP16_GPIO, /* MCU CLK pin (out) */
+ MPP17_GPIO, /* MCU ACT pin (out) */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO, /* USB LED (red)-Power*/
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO, /* SYS LED (green) */
+ MPP29_GPIO, /* SYS LED (red) */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* Reset button */
+ MPP37_GPIO, /* Copy button */
+ MPP38_GPIO, /* VID B0 */
+ MPP39_GPIO, /* COPY LED (green) */
+ MPP40_GPIO, /* COPY LED (red) */
+ MPP41_GPIO, /* SATA1 LED (green) */
+ MPP42_GPIO, /* SATA1 LED (red) */
+ MPP43_GPIO, /* HTP pin */
+ MPP44_GPIO, /* Buzzer */
+ MPP45_GPIO, /* VID B1 */
+ MPP46_GPIO, /* Power button */
+ MPP47_GPIO, /* Power resume data */
+ MPP48_GPIO, /* Power off */
+ MPP49_GPIO, /* Power resume clock */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config,NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1318 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /* Set RGMII delay */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int val)
+{
+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ u32 dout0 = readl(&gpio0->dout);
+ u32 blen0 = readl(&gpio0->blink_en);
+
+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 dout1 = readl(&gpio1->dout);
+ u32 blen1 = readl(&gpio1->blink_en);
+
+ switch (val) {
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
+ writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_START:
+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_LOADED:
+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
+ break;
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
+ case -BOOTSTAGE_ID_NET_LOADED:
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
+ break;
+ default:
+ if (val < 0) {
+ /* error */
+ printf("Error occured, error code = %d\n", -val);
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
+ writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
+ }
+ break;
+ }
+}
+#endif
--- /dev/null
+++ b/board/zyxel/nsa310/nsa310.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2013 Rafal Kazmierowski
+ *
+ * Based on Peter Schildmann <linux@schildmann.info>
+ * and guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __NSA310_H
+#define __NSA310_H
+
+/* GPIO's */
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_RED_LED (1 << 29)
+#define SATA1_GREEN_LED (1ULL << 41)
+#define SATA1_RED_LED (1ULL << 42)
+#define SATA2_GREEN_LED (1 << 12)
+#define SATA2_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_RED_LED (1 << 21)
+#define COPY_GREEN_LED (1ULL << 39)
+#define COPY_RED_LED (1ULL << 40)
+
+#define NSA310_OE_LOW (0)
+#define NSA310_VAL_LOW (SYS_GREEN_LED)
+#define NSA310_OE_HIGH (((COPY_GREEN_LED | COPY_RED_LED | \
+ SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL)
+#define NSA310_VAL_HIGH (0)
+
+/* PHY related */
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __NSA310_H */
--- /dev/null
+++ b/configs/nsa310_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_NSA310=y
+CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="NSA310> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_FDT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_ENV=y
+CONFIG_CMD_NAND=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_SYS_LONGHELP=y
--- /dev/null
+++ b/include/configs/nsa310.h
@@ -0,0 +1,117 @@
+/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_NSA310_H
+#define _CONFIG_NSA310_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KW88F6281 /* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Misc Configuration Options
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_PREBOOT
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#endif
+
+/* max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0xc0000
+#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x1
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+
+/*
+ * Date Time
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310_H */

655
package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch Normal file
View File

@@ -0,0 +1,655 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -68,6 +68,9 @@ config TARGET_SBx81LIFKW
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
+config TARGET_NSA325
+ bool "Zyxel NSA325 board"
+
endchoice
config SYS_SOC
@@ -91,6 +94,7 @@ source "board/Seagate/goflexhome/Kconfig
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
+source "board/zyxel/nsa325/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
--- /dev/null
+++ b/board/zyxel/nsa325/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NSA325
+
+config SYS_BOARD
+ default "nsa325"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa325"
+
+endif
--- /dev/null
+++ b/board/zyxel/nsa325/MAINTAINERS
@@ -0,0 +1,6 @@
+NSA325 BOARD
+M: Alberto Bursi <alberto.bursi@outlook.it>
+S: Maintained
+F: board/zyxel/nsa325/
+F: include/configs/nsa325.h
+F: configs/nsa325_defconfig
--- /dev/null
+++ b/board/zyxel/nsa325/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa325.o
+
--- /dev/null
+++ b/board/zyxel/nsa325/kwbimage.cfg
@@ -0,0 +1,78 @@
+# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
+#
+# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+#BOOT_FROM uart
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization
+DATA 0xFFD01400 0x4301503E # DDR Configuration register
+DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low
+DATA 0xFFD01408 0x33137777 # DDR Timing (Low)
+DATA 0xFFD0140C 0x16000C55 # DDR Timing (High)
+DATA 0xFFD01410 0x04000000 # DDR Address Control
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+DATA 0xFFD01418 0x00000000 # DDR Operation
+DATA 0xFFD0141C 0x00000672 # DDR Mode
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+DATA 0xFFD01424 0x0000F14F # DDR Controller Control High
+DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing
+DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb
+DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+
+DATA 0xFFD015D0 0x00000630
+DATA 0xFFD015D4 0x00000046
+DATA 0xFFD015D8 0x00000008
+DATA 0xFFD015DC 0x00000000
+DATA 0xFFD015E0 0x00000023
+DATA 0xFFD015E4 0x00203C18
+DATA 0xFFD01620 0x00384800
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x00066666
+
+#Disable nsa325 hardware watchdog to allow successful kwbooting
+DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
+DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
+
+# End of Header extension
+DATA 0x0 0x0
+
--- /dev/null
+++ b/board/zyxel/nsa325/nsa325.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on nsa320.c originall written by
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.c originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include "nsa325.h"
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
+ NSA325_OE_LOW, NSA325_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ /* (all LEDs & power off active high) */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA, /* PCF8563 RTC chip */
+ MPP9_TW_SCK, /* connected to TWSI */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* HDD2 LED (green) */
+ MPP13_GPIO, /* HDD2 LED (red) */
+ MPP14_GPIO, /* MCU DATA pin (in) */
+ MPP15_GPIO, /* USB LED (green) */
+ MPP16_GPIO, /* MCU CLK pin (out) */
+ MPP17_GPIO, /* MCU ACT pin (out) */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO, /* USB power */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO, /* SYS LED (green) */
+ MPP29_GPIO, /* SYS LED (orange) */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* reset button */
+ MPP37_GPIO, /* copy button */
+ MPP38_GPIO, /* VID B0 */
+ MPP39_GPIO, /* COPY LED (green) */
+ MPP40_GPIO, /* COPY LED (red) */
+ MPP41_GPIO, /* HDD1 LED (green) */
+ MPP42_GPIO, /* HDD1 LED (red) */
+ MPP43_GPIO, /* HTP pin */
+ MPP44_GPIO, /* buzzer */
+ MPP45_GPIO, /* VID B1 */
+ MPP46_GPIO, /* power button */
+ MPP47_GPIO, /* HDD2 power */
+ MPP48_GPIO, /* power off */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* This disables the hardware watchdog in the mcu on this board. */
+ kw_gpio_set_valid(14, 1);
+ kw_gpio_direction_output(14, 0);
+ kw_gpio_set_value(14, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1318 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /* Set RGMII delay */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
+ /* and has an MCU attached to the LED[2] via tristate interrupt */
+ reg = 0;
+
+ /* switch to LED register page */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
+ miiphy_write(name, devadr, 0x4, 0x1e1);
+ miiphy_write(name, devadr, 0x9, 0x300);
+ /* Downshift */
+ miiphy_write(name, devadr, 0x10, 0x3860);
+ miiphy_write(name, devadr, 0x0, 0x9140);
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
+
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int val)
+{
+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ u32 dout0 = readl(&gpio0->dout);
+ u32 blen0 = readl(&gpio0->blink_en);
+
+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 dout1 = readl(&gpio1->dout);
+ u32 blen1 = readl(&gpio1->blink_en);
+
+ switch (val) {
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
+ writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_START:
+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_LOADED:
+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
+ break;
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
+ case -BOOTSTAGE_ID_NET_LOADED:
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
+ break;
+ default:
+ if (val < 0) {
+ /* error */
+ printf("Error occured, error code = %d\n", -val);
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
+ writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
+ }
+ break;
+ }
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO button status */
+/*
+un-pressed:
+ gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
+ gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear )
+ gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
+pressed
+ gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
+ gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear )
+ gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
+*/
+
+static int
+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "power") == 0) {
+ kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
+ kw_gpio_direction_input(BTN_POWER);
+ return !kw_gpio_get_value(BTN_POWER);
+ }
+ else if (strcmp(argv[1], "reset") == 0)
+ return kw_gpio_get_value(BTN_RESET);
+ else if (strcmp(argv[1], "copy") == 0)
+ return kw_gpio_get_value(BTN_COPY);
+ else
+ return -1;
+}
+
+
+U_BOOT_CMD(button, 2, 0, do_read_button,
+ "Return GPIO button status 0=off 1=on",
+ "- button power|reset|copy: test buttons states\n"
+);
+
+#endif
+
--- /dev/null
+++ b/board/zyxel/nsa325/nsa325.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on nsa320.h originall written by
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __NSA325_H
+#define __NSA325_H
+
+/* low GPIO's */
+#define HDD2_GREEN_LED (1 << 12)
+#define HDD2_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \
+ USB_GREEN_LED | USB_POWER | \
+ SYS_GREEN_LED | SYS_ORANGE_LED))
+#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define COPY_GREEN_LED (1 << 7)
+#define COPY_RED_LED (1 << 8)
+#define HDD1_GREEN_LED (1 << 9)
+#define HDD1_RED_LED (1 << 10)
+#define HDD2_POWER (1 << 15)
+#define WATCHDOG_SIGNAL (1 << 14)
+
+#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \
+ HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
+#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#define BTN_POWER 46
+#define BTN_RESET 36
+#define BTN_COPY 37
+
+#endif /* __NSA325_H */
--- /dev/null
+++ b/configs/nsa325_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_NSA325=y
+CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="NSA325> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_FDT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_ENV=y
+CONFIG_CMD_NAND=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_SYS_LONGHELP=y
--- /dev/null
+++ b/include/configs/nsa325.h
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ * Based on
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_NSA325_H
+#define _CONFIG_NSA325_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Misc Configuration Options
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_PREBOOT
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0xc0000
+#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x1
+#define CONFIG_NETCONSOLE
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+
+/*
+ * Date Time
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
+
+#endif /* _CONFIG_NSA325_H */

1526
package/boot/uboot-kirkwood/patches/010-pogoplug_v4.patch Normal file
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File diff suppressed because it is too large Load Diff

57
package/boot/uboot-kirkwood/patches/110-dockstar.patch Normal file
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@@ -0,0 +1,57 @@
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -17,6 +17,7 @@
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_MVFS
/*
* mv-common.h should be defined after CMD configs since it used them
@@ -35,27 +36,22 @@
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x80000
-#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
+#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x1100000 ${initrd}; " \
- "bootm 0x800000 0x1100000"
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=console=ttyS0,115200\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "initrd=/boot/uInitrd\0" \
- "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -18,7 +18,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

50
package/boot/uboot-kirkwood/patches/120-iconnect.patch Normal file
View File

@@ -0,0 +1,50 @@
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -42,24 +42,22 @@
#define CONFIG_ENV_SECT_SIZE 0x20000
#endif
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OFFSET 0x80000
+#define CONFIG_ENV_OFFSET 0xe0000
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part rootfs; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
"bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet driver configuration
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -11,13 +11,14 @@ CONFIG_SYS_PROMPT="iconnect => "
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

40
package/boot/uboot-kirkwood/patches/130-ib62x0.patch Normal file
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@@ -0,0 +1,40 @@
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -47,21 +47,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/zImage\0" \
- "fdt=/boot/ib62x0.dtb\0" \
- "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet driver configuration
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -21,7 +21,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

46
package/boot/uboot-kirkwood/patches/140-pogoplug_e02.patch Normal file
View File

@@ -0,0 +1,46 @@
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -42,23 +42,23 @@
#endif
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
+#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs $(bootargs_console); " \
- "run bootcmd_usb; " \
- "bootm 0x00800000 0x01100000"
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part ubi; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
- "32M(rootfs),-(data)\0"\
- "mtdids=nand0=orion_nand\0"\
- "bootargs_console=console=ttyS0,115200\0" \
- "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
- "ext2load usb 0:1 0x01100000 /uInitrd\0"
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -18,6 +18,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

35
package/boot/uboot-kirkwood/patches/150-goflexhome.patch Normal file
View File

@@ -0,0 +1,35 @@
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -66,17 +66,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
"bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -23,7 +23,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),255m(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

166
package/boot/uboot-kirkwood/patches/200-openwrt-config.patch Normal file
View File

@@ -0,0 +1,166 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -102,4 +102,7 @@ source "board/zyxel/nsa310/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
+config SECOND_STAGE
+ bool "OpenWrt second stage hack"
+
endif
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -65,4 +65,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_DOCKSTAR_H */
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -85,4 +85,6 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_IB62x0_H */
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -72,4 +72,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_ICONNECT_H */
--- /dev/null
+++ b/include/configs/openwrt-kirkwood-common.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OPENWRT_KIRKWOOD_COMMON_H
+#define __OPENWRT_KIRKWOOD_COMMON_H
+
+/* Ethernet */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_IPADDR 192.168.1.1
+#endif
+
+/* second stage loader */
+#if defined(CONFIG_SECOND_STAGE)
+#undef CONFIG_ENV_IS_IN_NAND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* Various */
+#define CONFIG_BZIP2
+
+/* Unnecessary */
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#endif /* __OPENWRT_KIRKWOOD_COMMON_H */
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -72,4 +72,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_POGO_E02_H */
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -91,4 +91,6 @@
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_GOFLEXHOME_H */
--- a/include/configs/nsa310.h
+++ b/include/configs/nsa310.h
@@ -114,4 +114,6 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_NSA310_H */
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -31,3 +31,8 @@ CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -40,3 +40,8 @@ CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -35,4 +35,7 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -31,4 +31,8 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/nsa310_defconfig
+++ b/configs/nsa310_defconfig
@@ -35,6 +35,9 @@ CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
CONFIG_LZO=y
CONFIG_SYS_LONGHELP=y
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -31,3 +31,8 @@ CONFIG_USB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y