Initial commit
This commit is contained in:
domenico
@@ -0,0 +1,185 @@
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From 0e2da1a792a21e3933e17727920ed3c35a3ba57a Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 11 Mar 2018 15:13:30 +0100
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Subject: [PATCH] arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus
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The Xunlong Orange Pi Zero Plus is single board computer.
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- H5 Quad-core 64-bit Cortex-A53
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- 512MB DDR3
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- microSD slot
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- Debug TTL UART
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- 1000M/100M/10M Ethernet RJ45
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- Realtek RTL8189FTV
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- Spi flash (2MB)
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- One USB 2.0 HOST, One USB 2.0 OTG
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This is based on a patch from armbian:
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https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/arm64/boot/dts/allwinner/Makefile | 1 +
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.../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 147 +++++++++++++++++++++
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2 files changed, 148 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
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--- a/arch/arm64/boot/dts/allwinner/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/Makefile
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@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-p
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
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+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
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@@ -0,0 +1,147 @@
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+/*
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+ * Copyright (C) 2016 ARM Ltd.
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+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
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+ *
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+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
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+ */
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+
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+/dts-v1/;
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+#include "sun50i-h5.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/pinctrl/sun4i-a10.h>
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+
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+/ {
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+ model = "Xunlong Orange Pi Zero Plus";
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+ compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
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+
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+ reg_vcc3v3: vcc3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ aliases {
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+ ethernet0 = &emac;
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+ ethernet1 = &rtl8189ftv;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ pwr {
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+ label = "orangepi:green:pwr";
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+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
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+ default-state = "on";
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+ };
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+
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+ status {
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+ label = "orangepi:red:status";
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+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
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+ };
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+ };
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+
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+ reg_gmac_3v3: gmac-3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "gmac-3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <100000>;
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+ enable-active-high;
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+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
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+ };
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+};
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+
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+&ehci0 {
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+ status = "okay";
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+};
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+
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+&ehci1 {
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+ status = "okay";
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+};
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+
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+ status = "okay";
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+};
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+
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+&external_mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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+&mmc0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc0_pins_a>;
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+ vmmc-supply = <®_vcc3v3>;
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+ bus-width = <4>;
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+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc1_pins_a>;
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+ vmmc-supply = <®_vcc3v3>;
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+ bus-width = <4>;
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+ non-removable;
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+ status = "okay";
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+
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+ /*
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+ * Explicitly define the sdio device, so that we can add an ethernet
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+ * alias for it (which e.g. makes u-boot set a mac-address).
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+ */
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+ rtl8189ftv: sdio_wifi@1 {
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+ reg = <1>;
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+ };
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+};
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+
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+&spi0 {
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+ status = "okay";
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+
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+ flash@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "mxicy,mx25l1606e", "winbond,w25q128";
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+ reg = <0>;
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+ spi-max-frequency = <40000000>;
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+ };
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+};
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+
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+&ohci0 {
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+ status = "okay";
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+};
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+
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+&ohci1 {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins_a>;
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+ status = "okay";
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+};
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+
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+&usb_otg {
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ /* USB Type-A ports' VBUS is always on */
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+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
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+ status = "okay";
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+};
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