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			60 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
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| From: John Crispin <blogic@openwrt.org>
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| Date: Sun, 28 Jul 2013 19:45:30 +0200
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| Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
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| 
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| Describe gpio-ralink binding.
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| 
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| Signed-off-by: John Crispin <blogic@openwrt.org>
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| Cc: linux-mips@linux-mips.org
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| Cc: devicetree@vger.kernel.org
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| Cc: linux-gpio@vger.kernel.org
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| ---
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|  .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++
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|  1 file changed, 40 insertions(+)
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|  create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
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| 
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| --- /dev/null
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| +++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
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| @@ -0,0 +1,40 @@
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| +Ralink SoC GPIO controller bindings
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| +
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| +Required properties:
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| +- compatible:
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| +  - "ralink,rt2880-gpio" for Ralink controllers
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| +- #gpio-cells : Should be two.
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| +  - first cell is the pin number
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| +  - second cell is used to specify optional parameters (unused)
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| +- gpio-controller : Marks the device node as a GPIO controller
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| +- reg : Physical base address and length of the controller's registers
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| +- interrupt-parent: phandle to the INTC device node
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| +- interrupts : Specify the INTC interrupt number
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| +- ralink,nr-gpio : Specify the number of GPIOs
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| +- ralink,register-map : The register layout depends on the GPIO bank and actual
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| +		SoC type. Register offsets need to be in this order.
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| +		[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
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| +
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| +Optional properties:
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| +- ralink,gpio-base : Specify the GPIO chips base number
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| +
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| +Example:
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| +
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| +	gpio0: gpio@600 {
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| +		compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
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| +
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| +		#gpio-cells = <2>;
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| +		gpio-controller;
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| +
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| +		reg = <0x600 0x34>;
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| +
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| +		interrupt-parent = <&intc>;
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| +		interrupts = <6>;
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| +
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| +		ralink,gpio-base = <0>;
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| +		ralink,nr-gpio = <24>;
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| +		ralink,register-map = [ 00 04 08 0c
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| +				20 24 28 2c
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| +				30 34 ];
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| +
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| +	};
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