mediatek: add support t-phy settings from efuse on MT7986
Import patches from mtk-openwrt-feeds (MTK SDK) to support reading t-phy settings affecting PCIe as well as USB2 and USB3 from efuse. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
@@ -341,7 +341,7 @@
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pcie_phy: t-phy@11c00000 {
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pcie_phy: t-phy@11c00000 {
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compatible = "mediatek,mt7986-tphy",
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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"mediatek,generic-tphy-v4";
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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ranges;
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ranges;
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@@ -352,6 +352,24 @@
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clocks = <&clk40m>;
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clocks = <&clk40m>;
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clock-names = "ref";
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clock-names = "ref";
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#phy-cells = <1>;
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#phy-cells = <1>;
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auto_load_valid;
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auto_load_valid_ln1;
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nvmem-cells = <&pcie_intr_ln0>,
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<&pcie_rx_imp_ln0>,
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<&pcie_tx_imp_ln0>,
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<&pcie_auto_load_valid_ln0>,
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<&pcie_intr_ln1>,
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<&pcie_rx_imp_ln1>,
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<&pcie_tx_imp_ln1>,
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<&pcie_auto_load_valid_ln1>;
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nvmem-cell-names = "intr",
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"rx_imp",
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"tx_imp",
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"auto_load_valid",
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"intr_ln1",
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"rx_imp_ln1",
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"tx_imp_ln1",
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"auto_load_valid_ln1";
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};
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};
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};
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};
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@@ -462,6 +480,9 @@
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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clock-names = "ref", "da_ref";
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clock-names = "ref", "da_ref";
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#phy-cells = <1>;
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#phy-cells = <1>;
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auto_load_valid;
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nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
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nvmem-cell-names = "intr", "auto_load_valid";
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};
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};
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u3port0: usb-phy@11e10700 {
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u3port0: usb-phy@11e10700 {
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@@ -469,6 +490,12 @@
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clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
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clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
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clock-names = "ref";
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clock-names = "ref";
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#phy-cells = <1>;
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#phy-cells = <1>;
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auto_load_valid;
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nvmem-cells = <&comb_intr_p0>,
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<&comb_rx_imp_p0>,
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<&comb_tx_imp_p0>,
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<&comb_auto_load_valid>;
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nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
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};
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};
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u2port1: usb-phy@11e11000 {
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u2port1: usb-phy@11e11000 {
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@@ -477,6 +504,9 @@
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
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clock-names = "ref", "da_ref";
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clock-names = "ref", "da_ref";
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#phy-cells = <1>;
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#phy-cells = <1>;
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auto_load_valid;
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nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
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nvmem-cell-names = "intr", "auto_load_valid";
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};
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};
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};
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};
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@@ -0,0 +1,225 @@
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From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
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From: Zhanyong Wang <zhanyong.wang@mediatek.com>
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Date: Tue, 25 Jan 2022 16:50:47 +0800
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Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
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Add PCIe 2 lane efuse support in tphy driver.
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Signed-off-by: Jie Yang <jieyy.yang@mediatek.com>
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Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
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---
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drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++
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1 file changed, 140 insertions(+)
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--- a/drivers/phy/mediatek/phy-mtk-tphy.c
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+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
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@@ -44,6 +44,15 @@
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#define SSUSB_SIFSLV_V2_U3PHYD 0x200
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#define SSUSB_SIFSLV_V2_U3PHYA 0x400
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+/* version V4 sub-banks offset base address */
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+/* pcie phy banks */
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+#define SSUSB_SIFSLV_V4_SPLLC 0x000
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+#define SSUSB_SIFSLV_V4_CHIP 0x100
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+#define SSUSB_SIFSLV_V4_U3PHYD 0x900
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+#define SSUSB_SIFSLV_V4_U3PHYA 0xb00
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+
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+#define SSUSB_LN1_OFFSET 0x10000
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+
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#define U3P_MISC_REG1 0x04
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#define MR1_EFUSE_AUTO_LOAD_DIS BIT(6)
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@@ -320,6 +329,7 @@ enum mtk_phy_version {
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MTK_PHY_V1 = 1,
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MTK_PHY_V2,
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MTK_PHY_V3,
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+ MTK_PHY_V4,
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};
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struct mtk_phy_pdata {
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@@ -369,6 +379,9 @@ struct mtk_phy_instance {
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u32 efuse_intr;
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u32 efuse_tx_imp;
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u32 efuse_rx_imp;
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+ u32 efuse_intr_ln1;
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+ u32 efuse_tx_imp_ln1;
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+ u32 efuse_rx_imp_ln1;
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int eye_src;
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int eye_vrt;
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int eye_term;
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@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk
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}
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}
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+static void phy_v4_banks_init(struct mtk_tphy *tphy,
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+ struct mtk_phy_instance *instance)
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+{
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+ struct u2phy_banks *u2_banks = &instance->u2_banks;
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+ struct u3phy_banks *u3_banks = &instance->u3_banks;
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+
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+ switch (instance->type) {
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+ case PHY_TYPE_USB2:
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+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
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+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
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+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
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+ break;
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+ case PHY_TYPE_USB3:
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+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
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+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
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+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
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+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
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+ break;
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+ case PHY_TYPE_PCIE:
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+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC;
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+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP;
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+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD;
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+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA;
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+ break;
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+ default:
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+ dev_err(tphy->dev, "incompatible PHY type\n");
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+ return;
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+ }
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+}
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+
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static void phy_parse_property(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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@@ -1143,6 +1186,40 @@ static int phy_efuse_get(struct mtk_tphy
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dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
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instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
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+
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+ if (tphy->pdata->version != MTK_PHY_V4)
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+ break;
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+
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+ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
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+ if (ret) {
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+ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
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+ break;
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+ }
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+
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+ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1);
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+ if (ret) {
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+ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret);
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+ break;
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+ }
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+
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+ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1);
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+ if (ret) {
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+ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret);
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+ break;
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+ }
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+
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+ /* no efuse, ignore it */
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+ if (!instance->efuse_intr_ln1 &&
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+ !instance->efuse_rx_imp_ln1 &&
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+ !instance->efuse_tx_imp_ln1) {
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+ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n");
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+ instance->efuse_sw_en = 0;
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+ break;
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+ }
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+
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+ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n",
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+ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1,
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+ instance->efuse_tx_imp_ln1);
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break;
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default:
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dev_err(dev, "no sw efuse for type %d\n", instance->type);
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@@ -1174,6 +1251,31 @@ static void phy_efuse_set(struct mtk_phy
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writel(tmp, u2_banks->com + U3P_USBPHYACR1);
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break;
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case PHY_TYPE_USB3:
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+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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+
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+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
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+ tmp &= ~P3D_RG_TX_IMPEL;
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+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
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+ tmp |= P3D_RG_FORCE_TX_IMPEL;
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+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
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+
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+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
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+ tmp &= ~P3D_RG_RX_IMPEL;
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+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
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+ tmp |= P3D_RG_FORCE_RX_IMPEL;
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+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
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+
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+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
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+ tmp &= ~P3A_RG_IEXT_INTR;
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+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
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+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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+ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
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+ __func__, instance->efuse_tx_imp,
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+ instance->efuse_rx_imp, instance->efuse_intr);
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+
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+ break;
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case PHY_TYPE_PCIE:
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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@@ -1195,6 +1297,34 @@ static void phy_efuse_set(struct mtk_phy
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tmp &= ~P3A_RG_IEXT_INTR;
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tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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+ if (!instance->efuse_intr_ln1 &&
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+ !instance->efuse_rx_imp_ln1 &&
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+ !instance->efuse_tx_imp_ln1)
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+ break;
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+
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+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
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+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
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+
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+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
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+ tmp &= ~P3D_RG_TX_IMPEL;
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+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1);
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+ tmp |= P3D_RG_FORCE_TX_IMPEL;
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+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
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+
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+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
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+ tmp &= ~P3D_RG_RX_IMPEL;
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+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1);
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+ tmp |= P3D_RG_FORCE_RX_IMPEL;
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+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
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+
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+ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
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+ tmp &= ~P3A_RG_IEXT_INTR;
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+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1);
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+ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
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+ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n",
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+ __func__, instance->efuse_tx_imp_ln1,
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+ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1);
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break;
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default:
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dev_warn(dev, "no sw efuse for type %d\n", instance->type);
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@@ -1334,6 +1464,9 @@ static struct phy *mtk_phy_xlate(struct
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case MTK_PHY_V3:
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phy_v2_banks_init(tphy, instance);
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break;
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+ case MTK_PHY_V4:
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+ phy_v4_banks_init(tphy, instance);
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+ break;
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default:
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dev_err(dev, "phy version is not supported\n");
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return ERR_PTR(-EINVAL);
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@@ -1374,6 +1507,12 @@ static const struct mtk_phy_pdata tphy_v
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.version = MTK_PHY_V3,
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};
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+static const struct mtk_phy_pdata tphy_v4_pdata = {
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+ .avoid_rx_sen_degradation = false,
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+ .sw_efuse_supported = true,
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+ .version = MTK_PHY_V4,
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+};
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+
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static const struct mtk_phy_pdata mt8173_pdata = {
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.avoid_rx_sen_degradation = true,
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.version = MTK_PHY_V1,
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@@ -1393,6 +1532,7 @@ static const struct of_device_id mtk_tph
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{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
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{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
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{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
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+ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata },
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{ },
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};
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MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
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@@ -0,0 +1,149 @@
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From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
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From: Zhanyong Wang <zhanyong.wang@mediatek.com>
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Date: Tue, 25 Jan 2022 19:03:34 +0800
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Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
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support
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add auto-load-valid check mechanism support
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Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
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---
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drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
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1 file changed, 64 insertions(+), 3 deletions(-)
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--- a/drivers/phy/mediatek/phy-mtk-tphy.c
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+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
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@@ -376,9 +376,13 @@ struct mtk_phy_instance {
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u32 type_sw_reg;
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u32 type_sw_index;
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u32 efuse_sw_en;
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+ bool efuse_alv_en;
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+ u32 efuse_autoloadvalid;
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u32 efuse_intr;
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u32 efuse_tx_imp;
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u32 efuse_rx_imp;
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+ bool efuse_alv_ln1_en;
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+ u32 efuse_ln1_autoloadvalid;
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u32 efuse_intr_ln1;
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u32 efuse_tx_imp_ln1;
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u32 efuse_rx_imp_ln1;
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@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy
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{
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struct device *dev = &instance->phy->dev;
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int ret = 0;
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+ bool alv = false;
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/* tphy v1 doesn't support sw efuse, skip it */
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if (!tphy->pdata->sw_efuse_supported) {
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@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy
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switch (instance->type) {
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case PHY_TYPE_USB2:
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
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+ if (alv) {
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+ instance->efuse_alv_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
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+ &instance->efuse_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "u2 auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
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@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
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+ if (alv) {
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+ instance->efuse_alv_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
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+ &instance->efuse_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "u3 auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
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@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy
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if (tphy->pdata->version != MTK_PHY_V4)
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break;
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
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+ if (alv) {
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+ instance->efuse_alv_ln1_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
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+ &instance->efuse_ln1_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "pcie auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_ln1_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
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if (ret) {
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dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
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@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy
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switch (instance->type) {
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case PHY_TYPE_USB2:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u2_banks->misc + U3P_MISC_REG1);
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tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u2_banks->misc + U3P_MISC_REG1);
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@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy
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writel(tmp, u2_banks->com + U3P_USBPHYACR1);
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break;
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case PHY_TYPE_USB3:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy
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break;
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case PHY_TYPE_PCIE:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy
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tmp &= ~P3A_RG_IEXT_INTR;
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tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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- if (!instance->efuse_intr_ln1 &&
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- !instance->efuse_rx_imp_ln1 &&
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- !instance->efuse_tx_imp_ln1)
|
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+
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+ if ((!instance->efuse_intr_ln1 &&
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+ !instance->efuse_rx_imp_ln1 &&
|
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+ !instance->efuse_tx_imp_ln1) ||
|
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+ (instance->efuse_alv_ln1_en &&
|
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+ instance->efuse_ln1_autoloadvalid == 1))
|
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break;
|
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tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
|
||||||
Reference in New Issue
Block a user