initial support for RT288x/RT305x
SVN-Revision: 17439
This commit is contained in:
Gabor Juhos
@@ -0,0 +1,56 @@
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/*
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* Ralink RT288x/RT305x specific CPU feature overrides
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This file was derived from: include/asm-mips/cpu-features.h
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_sb1_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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#define cpu_has_prefetch 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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#define cpu_has_mips16 1
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 1
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_64bit_addresses 0
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
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@@ -0,0 +1,52 @@
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/*
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* Ralink RT288x GPIO API definitions
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_MACH_RT288X_GPIO_H
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#define __ASM_MACH_RT288X_GPIO_H
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#define ARCH_NR_GPIOS 64
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#include <asm-generic/gpio.h>
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#include <asm/mach-ralink/rt288x.h>
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extern void __rt288x_gpio_set_value(unsigned gpio, int value);
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extern int __rt288x_gpio_get_value(unsigned gpio);
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static inline int gpio_to_irq(unsigned gpio)
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{
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return RT288X_GPIO_IRQ(gpio);
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return irq - RT288X_GPIO_IRQ_BASE;
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}
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static inline int gpio_get_value(unsigned gpio)
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{
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if (gpio < RT288X_GPIO_COUNT)
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return __rt288x_gpio_get_value(gpio);
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (gpio < RT288X_GPIO_COUNT)
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__rt288x_gpio_set_value(gpio, value);
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else
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__gpio_set_value(gpio, value);
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}
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#define gpio_cansleep __gpio_cansleep
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#endif /* __ASM_MACH_RT288X_GPIO_H */
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@@ -0,0 +1,17 @@
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/*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_RT288X_IRQ_H
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#define __ASM_MACH_RT288X_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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#define NR_IRQS 48
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#include_next <irq.h>
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#endif /* __ASM_MACH_RT288X_IRQ_H */
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@@ -0,0 +1,20 @@
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/*
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* Ralink RT288x SoC specific platform definitions
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_RT288X_PLATFORM_H
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#define __ASM_MACH_RT288X_PLATFORM_H
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struct physmap_flash_data;
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extern void rt288x_register_flash(unsigned int id,
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struct physmap_flash_data *pdata) __init;
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#endif /* __ASM_MACH_RT288X_PLATFORM_H */
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@@ -0,0 +1,89 @@
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/*
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* Ralink RT288x SoC specific definitions
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT288X_H_
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#define _RT288X_H_
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#include <linux/init.h>
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#include <linux/io.h>
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void rt288x_detect_sys_type(void) __init;
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#define RT288X_SYS_TYPE_LEN 64
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extern unsigned char rt288x_sys_type[RT288X_SYS_TYPE_LEN];
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void rt288x_detect_sys_freq(void) __init;
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extern unsigned long rt288x_cpu_freq;
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extern unsigned long rt288x_sys_freq;
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extern unsigned long rt288x_mach_type;
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#define RT288X_MACH_GENERIC 0
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#define RT288X_CPU_IRQ_BASE 0
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#define RT288X_INTC_IRQ_BASE 8
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#define RT288X_INTC_IRQ_COUNT 32
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#define RT288X_GPIO_IRQ_BASE 40
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#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2)
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#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4)
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#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5)
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#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6)
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#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7)
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#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0)
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#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1)
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#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2)
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#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3)
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#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4)
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#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8)
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#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23)
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#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x))
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#define RT288X_GPIO_COUNT 32
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extern void __iomem *rt288x_sysc_base;
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extern void __iomem *rt288x_intc_base;
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extern void __iomem *rt288x_memc_base;
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static inline void rt288x_sysc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt288x_sysc_base + reg);
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}
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static inline u32 rt288x_sysc_rr(unsigned reg)
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{
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return __raw_readl(rt288x_sysc_base + reg);
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}
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static inline void rt288x_intc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt288x_intc_base + reg);
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}
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static inline u32 rt288x_intc_rr(unsigned reg)
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{
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return __raw_readl(rt288x_intc_base + reg);
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}
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static inline void rt288x_memc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, rt288x_memc_base + reg);
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}
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static inline u32 rt288x_memc_rr(unsigned reg)
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{
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return __raw_readl(rt288x_memc_base + reg);
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}
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#endif /* _RT228X_H_ */
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@@ -0,0 +1,121 @@
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/*
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* Ralink RT288x SoC register definitions
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT288X_REGS_H_
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#define _RT288X_REGS_H_
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#include <linux/bitops.h>
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#define RT2880_SYSC_BASE 0x00300000
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#define RT2880_TIMER_BASE 0x00300100
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#define RT2880_INTC_BASE 0x00300200
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#define RT2880_MEMC_BASE 0x00300300
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#define RT2880_UART0_BASE 0x00300500
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#define RT2880_PIO_BASE 0x00300600
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#define RT2880_I2C_BASE 0x00300900
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#define RT2880_SPI_BASE 0x00300b00
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#define RT2880_UART1_BASE 0x00300c00
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#define RT2880_FE_BASE 0x00310000
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#define RT2880_ROM_BASE 0x00400000
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#define RT2880_PCI_BASE 0x00500000
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#define RT2880_WMAC_BASE 0x00600000
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#define RT2880_FLASH1_BASE 0x01000000
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#define RT2880_FLASH0_BASE 0x1fc00000
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#define RT2880_SDRAM_BASE 0x08000000
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#define RT2880_SYSC_SIZE 0x100
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#define RT2880_INTC_SIZE 0x100
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#define RT2880_MEMC_SIZE 0x100
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#define RT2880_UART0_SIZE 0x100
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#define RT2880_UART1_SIZE 0x100
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#define RT2880_FLASH1_SIZE (16 * 1024 * 1024)
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#define RT2880_FLASH0_SIZE (4 * 1024 * 1024)
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/* SYSC registers */
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#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
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#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
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#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
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#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
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#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
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#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
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#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
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#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
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#define CHIP_ID_ID_MASK 0xff
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
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#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
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#define SYSTEM_CONFIG_CPUCLK_250 0x0
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#define SYSTEM_CONFIG_CPUCLK_266 0x1
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#define SYSTEM_CONFIG_CPUCLK_280 0x2
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#define SYSTEM_CONFIG_CPUCLK_300 0x3
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#define RT2880_RESET_SYSTEM BIT(0)
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#define RT2880_RESET_TIMER BIT(1)
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#define RT2880_RESET_INTC BIT(2)
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#define RT2880_RESET_MEMC BIT(3)
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#define RT2880_RESET_CPU BIT(4)
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#define RT2880_RESET_UART0 BIT(5)
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#define RT2880_RESET_PIO BIT(6)
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#define RT2880_RESET_I2C BIT(9)
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#define RT2880_RESET_SPI BIT(11)
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#define RT2880_RESET_UART1 BIT(12)
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#define RT2880_RESET_PCI BIT(16)
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#define RT2880_RESET_WMAC BIT(17)
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#define RT2880_RESET_FE BIT(18)
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#define RT2880_RESET_PCM BIT(19)
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/* TIMER registers */
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/* INTC register */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define RT2880_INTC_INT_TIMER0 BIT(0)
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#define RT2880_INTC_INT_TIMER1 BIT(1)
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#define RT2880_INTC_INT_UART0 BIT(2)
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#define RT2880_INTC_INT_PIO BIT(3)
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#define RT2880_INTC_INT_PCM BIT(4)
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#define RT2880_INTC_INT_UART1 BIT(8)
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#define RT2880_INTC_INT_IA BIT(23)
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#define RT2880_INTC_INT_GLOBAL BIT(31)
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/* MEMC registers */
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#define MEMC_REG_SDRAM_CFG0 0x00
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#define MEMC_REG_SDRAM_CFG1 0x04
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#define MEMC_REG_FLASH_CFG0 0x08
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#define MEMC_REG_FLASH_CFG1 0x0c
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#define MEMC_REG_IA_ADDR 0x10
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#define MEMC_REG_IA_TYPE 0x14
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#define FLASH_CFG_WIDTH_SHIFT 26
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#define FLASH_CFG_WIDTH_MASK 0x3
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#define FLASH_CFG_WIDTH_8BIT 0x0
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#define FLASH_CFG_WIDTH_16BIT 0x1
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#define FLASH_CFG_WIDTH_32BIT 0x2
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/* UART registers */
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#define UART_REG_RX 0
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#define UART_REG_TX 1
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#define UART_REG_IER 2
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#define UART_REG_IIR 3
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#define UART_REG_FCR 4
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#define UART_REG_LCR 5
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#define UART_REG_MCR 6
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#define UART_REG_LSR 7
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#endif /* _RT288X_REGS_H_ */
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@@ -0,0 +1,91 @@
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/*
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* Ralink RT305x SoC specific definitions
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*
|
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
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#ifndef _RT305X_H_
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#define _RT305X_H_
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#include <linux/init.h>
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#include <linux/io.h>
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void rt305x_detect_sys_type(void) __init;
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#define RT305X_SYS_TYPE_LEN 64
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extern unsigned char rt305x_sys_type[RT305X_SYS_TYPE_LEN];
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void rt305x_detect_sys_freq(void) __init;
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extern unsigned long rt305x_cpu_freq;
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extern unsigned long rt305x_sys_freq;
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#define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
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#define RT305X_CPU_IRQ_BASE 0
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#define RT305X_INTC_IRQ_BASE 8
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#define RT305X_INTC_IRQ_COUNT 32
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#define RT305X_GPIO_IRQ_BASE 40
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#define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2)
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#define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5)
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#define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6)
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#define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7)
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#define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0)
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#define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1)
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#define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2)
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#define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3)
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#define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4)
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#define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5)
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#define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6)
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#define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7)
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#define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8)
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#define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9)
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#define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10)
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#define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12)
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#define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17)
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#define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
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extern void __iomem *rt305x_sysc_base;
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extern void __iomem *rt305x_intc_base;
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extern void __iomem *rt305x_memc_base;
|
||||
|
||||
static inline void rt305x_sysc_wr(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt305x_sysc_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt305x_sysc_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt305x_sysc_base + reg);
|
||||
}
|
||||
|
||||
static inline void rt305x_intc_wr(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt305x_intc_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt305x_intc_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt305x_intc_base + reg);
|
||||
}
|
||||
|
||||
static inline void rt305x_memc_wr(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt305x_memc_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt305x_memc_rr(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt305x_memc_base + reg);
|
||||
}
|
||||
|
||||
#endif /* _RT305X_H_ */
|
||||
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Ralink RT305 SoC register definitions
|
||||
*
|
||||
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _RT305X_REGS_H_
|
||||
#define _RT305X_REGS_H_
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define RT305X_SDRAM_BASE 0x00000000
|
||||
#define RT305X_SYSC_BASE 0x10000000
|
||||
#define RT305X_TIMER_BASE 0x10000100
|
||||
#define RT305X_INTC_BASE 0x10000200
|
||||
#define RT305X_MEMC_BASE 0x10000300
|
||||
#define RT305X_PCM_BASE 0x10000400
|
||||
#define RT305X_UART0_BASE 0x10000500
|
||||
#define RT305X_PIO_BASE 0x10000600
|
||||
#define RT305X_GDMA_BASE 0x10000700
|
||||
#define RT305X_NANDC_BASE 0x10000800
|
||||
#define RT305X_I2C_BASE 0x10000900
|
||||
#define RT305X_I2S_BASE 0x10000a00
|
||||
#define RT305X_SPI_BASE 0x10000b00
|
||||
#define RT305X_UART1_BASE 0x10000c00
|
||||
#define RT305X_FE_BASE 0x10010000
|
||||
#define RT305X_SWITCH_BASE 0x10110000
|
||||
#define RT305X_WMAC_BASE 0x00180000
|
||||
#define RT305X_OTG_BASE 0x101c0000
|
||||
#define RT305X_ROM_BASE 0x00400000
|
||||
#define RT305X_FLASH1_BASE 0x1b000000
|
||||
#define RT305X_FLASH0_BASE 0x1f000000
|
||||
|
||||
#define RT305X_SYSC_SIZE 0x100
|
||||
#define RT305X_INTC_SIZE 0x100
|
||||
#define RT305X_MEMC_SIZE 0x100
|
||||
#define RT305X_UART0_SIZE 0x100
|
||||
#define RT305X_UART1_SIZE 0x100
|
||||
#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
|
||||
#define RT305X_FLASH0_SIZE (4 * 1024 * 1024)
|
||||
|
||||
/* SYSC registers */
|
||||
#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
|
||||
#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
|
||||
#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
|
||||
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
|
||||
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
|
||||
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
|
||||
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
|
||||
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
|
||||
|
||||
#define CHIP_ID_ID_MASK 0xff
|
||||
#define CHIP_ID_ID_SHIFT 8
|
||||
#define CHIP_ID_REV_MASK 0xff
|
||||
|
||||
#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
|
||||
#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
|
||||
#define SYSTEM_CONFIG_CPUCLK_320 0x0
|
||||
#define SYSTEM_CONFIG_CPUCLK_384 0x1
|
||||
|
||||
#define RT305X_RESET_SYSTEM BIT(0)
|
||||
#define RT305X_RESET_TIMER BIT(8)
|
||||
#define RT305X_RESET_INTC BIT(9)
|
||||
#define RT305X_RESET_MEMC BIT(10)
|
||||
#define RT305X_RESET_PCM BIT(11)
|
||||
#define RT305X_RESET_UART0 BIT(12)
|
||||
#define RT305X_RESET_PIO BIT(13)
|
||||
#define RT305X_RESET_DMA BIT(14)
|
||||
#define RT305X_RESET_I2C BIT(16)
|
||||
#define RT305X_RESET_I2S BIT(17)
|
||||
#define RT305X_RESET_SPI BIT(18)
|
||||
#define RT305X_RESET_UART1 BIT(19)
|
||||
#define RT305X_RESET_WNIC BIT(20)
|
||||
#define RT305X_RESET_FE BIT(21)
|
||||
#define RT305X_RESET_OTG BIT(22)
|
||||
#define RT305X_RESET_ESW BIT(23)
|
||||
|
||||
/* TIMER registers */
|
||||
|
||||
/* INTC register */
|
||||
#define INTC_REG_STATUS0 0x00
|
||||
#define INTC_REG_STATUS1 0x04
|
||||
#define INTC_REG_TYPE 0x20
|
||||
#define INTC_REG_RAW_STATUS 0x30
|
||||
#define INTC_REG_ENABLE 0x34
|
||||
#define INTC_REG_DISABLE 0x38
|
||||
|
||||
#define RT305X_INTC_INT_SYSCTL BIT(0)
|
||||
#define RT305X_INTC_INT_TIMER0 BIT(1)
|
||||
#define RT305X_INTC_INT_TIMER1 BIT(2)
|
||||
#define RT305X_INTC_INT_IA BIT(3)
|
||||
#define RT305X_INTC_INT_PCM BIT(4)
|
||||
#define RT305X_INTC_INT_UART0 BIT(5)
|
||||
#define RT305X_INTC_INT_PIO BIT(6)
|
||||
#define RT305X_INTC_INT_DMA BIT(7)
|
||||
#define RT305X_INTC_INT_NAND BIT(8)
|
||||
#define RT305X_INTC_INT_PERFC BIT(9)
|
||||
#define RT305X_INTC_INT_I2S BIT(10)
|
||||
#define RT305X_INTC_INT_UART1 BIT(12)
|
||||
#define RT305X_INTC_INT_ESW BIT(17)
|
||||
#define RT305X_INTC_INT_OTG BIT(18)
|
||||
#define RT305X_INTC_INT_GLOBAL BIT(31)
|
||||
|
||||
/* MEMC registers */
|
||||
#define MEMC_REG_SDRAM_CFG0 0x00
|
||||
#define MEMC_REG_SDRAM_CFG1 0x04
|
||||
#define MEMC_REG_FLASH_CFG0 0x08
|
||||
#define MEMC_REG_FLASH_CFG1 0x0c
|
||||
#define MEMC_REG_IA_ADDR 0x10
|
||||
#define MEMC_REG_IA_TYPE 0x14
|
||||
|
||||
#define FLASH_CFG_WIDTH_SHIFT 26
|
||||
#define FLASH_CFG_WIDTH_MASK 0x3
|
||||
#define FLASH_CFG_WIDTH_8BIT 0x0
|
||||
#define FLASH_CFG_WIDTH_16BIT 0x1
|
||||
#define FLASH_CFG_WIDTH_32BIT 0x2
|
||||
|
||||
/* UART registers */
|
||||
#define UART_REG_RX 0
|
||||
#define UART_REG_TX 1
|
||||
#define UART_REG_IER 2
|
||||
#define UART_REG_IIR 3
|
||||
#define UART_REG_FCR 4
|
||||
#define UART_REG_LCR 5
|
||||
#define UART_REG_MCR 6
|
||||
#define UART_REG_LSR 7
|
||||
|
||||
#endif /* _RT305X_REGS_H_ */
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MACH_RT288X_WAR_H
|
||||
#define __ASM_MACH_RT288X_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MACH_RT288X_WAR_H */
|
||||
Reference in New Issue
Block a user