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ramips: lzma-loader: use proper register names

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Before this was reworked, in the file for mt7621 subtarget
(target/linux/ramips/image/lzma-loader/src/board-mt7621.c)
the "Transmitter shift register empty" bit TEMT was used instead of
the "Transmitter holding register empty" bit THRE,
but after the rework, this value was labeled as the THRE bit instead.

Functionally there is no difference, but this is confusing to read,
as it suggests that the subtargets have different bits for the same
register in UART when in reality they are exactly the same.

One can use either bit, or both, at user's descretion
in order to determine whether the UART TX buffer is ready.
The generic kernel early-printk uses both,
(arch/mips/kernel/early_printk_8250.c)
while the ralink-specific early-printk uses only THRE,
(arch/mips/ralink/early_printk.c).

Define both bits and rewrite macros for readability,
keep the same values, as changing which to use should be tested first.

Ref: c31319b66 ("ramips: lzma-loader: Refactor loader")
Signed-off-by: Michael Pratt <mcpratt@pm.me>

(cherry picked from commit 2e47913c64)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
This commit is contained in:
Michael Pratt
2023-12-06 14:12:03 -05:00
committed by Hauke Mehrtens
parent 76f7dd3312
commit 2216b10ebb
1 changed files with 8 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
target/linux/ramips/image/lzma-loader/src/board.c
View File

@@ -26,21 +26,24 @@
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#if defined(SOC_MT7620) || defined(SOC_RT3883) #if defined(SOC_MT7620) || defined(SOC_RT3883)
#define UART_BASE KSEG1ADDR(0x10000c00) #define UART_BASE KSEG1ADDR(0x10000c00)
#define UART_THR (UART_BASE + 0x04) #define UART_THR (UART_BASE + 0x04)
#define UART_LSR (UART_BASE + 0x1c) #define UART_LSR (UART_BASE + 0x1c)
#define UART_LSR_THRE_MASK 0x40 #define UART_LSR_MASK UART_LSR_TEMT
#elif defined(SOC_MT7621) #elif defined(SOC_MT7621)
#define UART_BASE KSEG1ADDR(0x1e000c00) #define UART_BASE KSEG1ADDR(0x1e000c00)
#define UART_THR (UART_BASE + 0x00) #define UART_THR (UART_BASE + 0x00)
#define UART_LSR (UART_BASE + 0x14) #define UART_LSR (UART_BASE + 0x14)
#define UART_LSR_THRE_MASK 0x20 #define UART_LSR_MASK UART_LSR_THRE
#elif defined(SOC_RT305X) #elif defined(SOC_RT305X)
#define UART_BASE KSEG1ADDR(0x10000500) #define UART_BASE KSEG1ADDR(0x10000500)
#define UART_THR (UART_BASE + 0x04) #define UART_THR (UART_BASE + 0x04)
#define UART_LSR (UART_BASE + 0x1c) #define UART_LSR (UART_BASE + 0x1c)
#define UART_LSR_THRE_MASK 0x20 #define UART_LSR_MASK UART_LSR_THRE
#else #else
#error "Unsupported SOC..." #error "Unsupported SOC..."
#endif #endif
@@ -56,7 +59,7 @@ void board_init(void)
void board_putc(int ch) void board_putc(int ch)
{ {
while ((READREG(UART_LSR) & UART_LSR_THRE_MASK) == 0); while ((READREG(UART_LSR) & UART_LSR_MASK) == 0);
WRITEREG(UART_THR, ch); WRITEREG(UART_THR, ch);
while ((READREG(UART_LSR) & UART_LSR_THRE_MASK) == 0); while ((READREG(UART_LSR) & UART_LSR_MASK) == 0);
} }