kernel: bump 4.19 to 4.19.88
Refreshed all patches. Remove upstreamed: - 0004-boot-sq201-from-sda1.patch - 500-v4.20-ubifs-Fix-default-compression-selection-in-ubifs.patch - 0003-usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core.patch Altered patches: - 0011-ARM-dts-Fix-up-SQ201-flash-access.patch - 400-mtd-add-rootfs-split-support.patch - 0101-pci-mediatek-backport-fix-pcie.patch Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
This commit is contained in:
Koen Vandeputte
@@ -57,83 +57,7 @@
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}
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static void mtk_pcie_port_free(struct mtk_pcie_port *port)
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@@ -394,75 +395,6 @@ static struct pci_ops mtk_pcie_ops_v2 =
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.write = mtk_pcie_config_write,
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};
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-static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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-{
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- struct mtk_pcie *pcie = port->pcie;
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- struct resource *mem = &pcie->mem;
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- const struct mtk_pcie_soc *soc = port->pcie->soc;
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- u32 val;
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- size_t size;
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- int err;
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-
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- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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- if (pcie->base) {
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- val = readl(pcie->base + PCIE_SYS_CFG_V2);
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- val |= PCIE_CSR_LTSSM_EN(port->slot) |
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- PCIE_CSR_ASPM_L1_EN(port->slot);
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- writel(val, pcie->base + PCIE_SYS_CFG_V2);
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- }
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-
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- /* Assert all reset signals */
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- writel(0, port->base + PCIE_RST_CTRL);
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-
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- /*
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- * Enable PCIe link down reset, if link status changed from link up to
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- * link down, this will reset MAC control registers and configuration
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- * space.
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- */
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- writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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-
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- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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- val = readl(port->base + PCIE_RST_CTRL);
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- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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- PCIE_MAC_SRSTB | PCIE_CRSTB;
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- writel(val, port->base + PCIE_RST_CTRL);
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-
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- /* Set up vendor ID and class code */
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- if (soc->need_fix_class_id) {
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- val = PCI_VENDOR_ID_MEDIATEK;
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- writew(val, port->base + PCIE_CONF_VEND_ID);
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-
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- val = PCI_CLASS_BRIDGE_HOST;
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- writew(val, port->base + PCIE_CONF_CLASS_ID);
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- }
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-
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- /* 100ms timeout value should be enough for Gen1/2 training */
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- err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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- !!(val & PCIE_PORT_LINKUP_V2), 20,
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- 100 * USEC_PER_MSEC);
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- if (err)
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- return -ETIMEDOUT;
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-
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- /* Set INTx mask */
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- val = readl(port->base + PCIE_INT_MASK);
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- val &= ~INTX_MASK;
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- writel(val, port->base + PCIE_INT_MASK);
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-
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- /* Set AHB to PCIe translation windows */
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- size = mem->end - mem->start;
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- val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
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- writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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-
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- val = upper_32_bits(mem->start);
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- writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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-
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- /* Set PCIe to AXI translation memory space.*/
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- val = fls(0xffffffff) | WIN_ENABLE;
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- writel(val, port->base + PCIE_AXI_WINDOW0);
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-
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- return 0;
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-}
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-
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static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
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@@ -601,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
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@@ -532,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
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writel(val, port->base + PCIE_INT_MASK);
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}
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@@ -161,7 +85,7 @@
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static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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@@ -630,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
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@@ -561,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
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port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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&intx_domain_ops, port);
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@@ -169,16 +93,7 @@
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if (!port->irq_domain) {
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dev_err(dev, "failed to get INTx IRQ domain\n");
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return -ENODEV;
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@@ -639,8 +593,6 @@ static int mtk_pcie_init_irq_domain(stru
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ret = mtk_pcie_allocate_msi_domains(port);
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if (ret)
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return ret;
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-
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- mtk_pcie_enable_msi(port);
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}
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return 0;
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@@ -693,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
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@@ -622,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
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struct mtk_pcie *pcie = port->pcie;
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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@@ -187,7 +102,7 @@
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err = mtk_pcie_init_irq_domain(port, node);
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if (err) {
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@@ -701,8 +653,81 @@ static int mtk_pcie_setup_irq(struct mtk
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@@ -630,8 +653,9 @@ static int mtk_pcie_setup_irq(struct mtk
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return err;
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}
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@@ -196,82 +111,10 @@
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+ port->irq = platform_get_irq(pdev, port->slot);
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+ irq_set_chained_handler_and_data(port->irq,
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+ mtk_pcie_intr_handler, port);
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+
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+ return 0;
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+}
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+
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+static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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+{
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+ struct mtk_pcie *pcie = port->pcie;
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+ struct resource *mem = &pcie->mem;
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+ const struct mtk_pcie_soc *soc = port->pcie->soc;
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+ u32 val;
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+ size_t size;
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+ int err;
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+
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+ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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+ if (pcie->base) {
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+ val = readl(pcie->base + PCIE_SYS_CFG_V2);
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+ val |= PCIE_CSR_LTSSM_EN(port->slot) |
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+ PCIE_CSR_ASPM_L1_EN(port->slot);
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+ writel(val, pcie->base + PCIE_SYS_CFG_V2);
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+ }
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+
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+ /* Assert all reset signals */
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+ writel(0, port->base + PCIE_RST_CTRL);
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+
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+ /*
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+ * Enable PCIe link down reset, if link status changed from link up to
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+ * link down, this will reset MAC control registers and configuration
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+ * space.
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+ */
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+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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+
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+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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+ val = readl(port->base + PCIE_RST_CTRL);
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+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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+ PCIE_MAC_SRSTB | PCIE_CRSTB;
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+ writel(val, port->base + PCIE_RST_CTRL);
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+
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+ /* Set up vendor ID and class code */
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+ if (soc->need_fix_class_id) {
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+ val = PCI_VENDOR_ID_MEDIATEK;
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+ writew(val, port->base + PCIE_CONF_VEND_ID);
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+
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+ val = PCI_CLASS_BRIDGE_PCI;
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+ writew(val, port->base + PCIE_CONF_CLASS_ID);
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+ }
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+
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+ /* 100ms timeout value should be enough for Gen1/2 training */
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+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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+ !!(val & PCIE_PORT_LINKUP_V2), 20,
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+ 100 * USEC_PER_MSEC);
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+ if (err)
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+ return -ETIMEDOUT;
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+
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+ /* Set INTx mask */
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+ val = readl(port->base + PCIE_INT_MASK);
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+ val &= ~INTX_MASK;
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+ writel(val, port->base + PCIE_INT_MASK);
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+
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+ if (IS_ENABLED(CONFIG_PCI_MSI))
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+ mtk_pcie_enable_msi(port);
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+
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+ /* Set AHB to PCIe translation windows */
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+ size = mem->end - mem->start;
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+ val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
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+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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+
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+ val = upper_32_bits(mem->start);
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+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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+
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+ /* Set PCIe to AXI translation memory space.*/
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+ val = fls(0xffffffff) | WIN_ENABLE;
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+ writel(val, port->base + PCIE_AXI_WINDOW0);
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return 0;
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}
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@@ -903,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
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@@ -904,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
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/* sys_ck might be divided into the following parts in some chips */
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snprintf(name, sizeof(name), "ahb_ck%d", slot);
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@@ -336,7 +179,7 @@
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snprintf(name, sizeof(name), "pcie-rst%d", slot);
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port->reset = devm_reset_control_get_optional_exclusive(dev, name);
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@@ -998,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
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@@ -999,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
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pcie->free_ck = NULL;
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}
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@@ -349,7 +192,7 @@
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/* enable top level clock */
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err = clk_prepare_enable(pcie->free_ck);
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@@ -1013,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
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@@ -1014,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
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return 0;
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err_free_ck:
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@@ -362,19 +205,16 @@
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return err;
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}
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@@ -1122,8 +1122,6 @@
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@@ -1122,36 +1122,6 @@ static int mtk_pcie_request_resources(st
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return err;
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err = devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
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- if (err)
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- return err;
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return 0;
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}
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@@ -1127,34 +1128,6 @@ static int mtk_pcie_request_resources(st
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return 0;
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}
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-
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- return 0;
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-}
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-
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-static int mtk_pcie_register_host(struct pci_host_bridge *host)
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-{
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- struct mtk_pcie *pcie = pci_host_bridge_priv(host);
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@@ -399,14 +239,10 @@
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- pcie_bus_configure_settings(child);
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-
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- pci_bus_add_devices(host->bus);
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-
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- return 0;
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-}
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-
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static int mtk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -1181,7 +1154,14 @@ static int mtk_pcie_probe(struct platfor
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return 0;
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}
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@@ -1182,7 +1152,14 @@ static int mtk_pcie_probe(struct platfor
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if (err)
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goto put_resources;
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@@ -422,7 +258,7 @@
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if (err)
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goto put_resources;
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@@ -1194,6 +1174,80 @@ put_resources:
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@@ -1195,6 +1172,80 @@ put_resources:
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return err;
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}
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@@ -503,7 +339,7 @@
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static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
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.ops = &mtk_pcie_ops,
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.startup = mtk_pcie_startup_port,
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@@ -1222,10 +1276,13 @@ static const struct of_device_id mtk_pci
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@@ -1223,10 +1274,13 @@ static const struct of_device_id mtk_pci
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static struct platform_driver mtk_pcie_driver = {
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.probe = mtk_pcie_probe,
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