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kernel: update kernel 4.9 to 4.9.14

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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens
2017-03-12 12:30:30 +01:00
parent f5d403488e
commit 9a065fcfec
27 changed files with 131 additions and 211 deletions
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12
target/linux/mediatek/patches-4.9/0000-pinctrl-esw.patch
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@@ -1,7 +1,5 @@
Index: linux-4.9.13/include/dt-bindings/pinctrl/mt7623-pinfunc.h
===================================================================
--- linux-4.9.13.orig/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+++ linux-4.9.13/include/dt-bindings/pinctrl/mt7623-pinfunc.h
--- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -505,6 +505,9 @@
#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
@@ -12,10 +10,8 @@ Index: linux-4.9.13/include/dt-bindings/pinctrl/mt7623-pinfunc.h
#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
Index: linux-4.9.13/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
===================================================================
--- linux-4.9.13.orig/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+++ linux-4.9.13/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
@@ -1894,8 +1894,9 @@ static const struct mtk_desc_pin mtk_pin
MTK_PIN(
PINCTRL_PIN(273, "GPIO273"),

8
target/linux/mediatek/patches-4.9/0001-NET-multi-phy-support.patch
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@@ -11,7 +11,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -890,7 +890,8 @@ void phy_state_machine(struct work_struc
@@ -996,7 +996,8 @@ void phy_state_machine(struct work_struc
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
@@ -21,7 +21,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
phydev->adjust_link(phydev->attached_dev);
break;
}
@@ -973,7 +974,8 @@ void phy_state_machine(struct work_struc
@@ -1079,7 +1080,8 @@ void phy_state_machine(struct work_struc
netif_carrier_on(phydev->attached_dev);
} else {
phydev->state = PHY_NOLINK;
@@ -31,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
}
phydev->adjust_link(phydev->attached_dev);
@@ -985,7 +987,8 @@ void phy_state_machine(struct work_struc
@@ -1091,7 +1093,8 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
@@ -43,7 +43,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
}
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -377,6 +377,7 @@ struct phy_device {
@@ -373,6 +373,7 @@ struct phy_device {
bool is_pseudo_fixed_link;
bool has_fixups;
bool suspended;

16
target/linux/mediatek/patches-4.9/0009-clk-mediatek-Add-MT2701-clock-support.patch
View File

@@ -21,7 +21,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,14 @@
@@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
---help---
Mediatek SoCs' clock support.
@@ -46,7 +46,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,26 @@
@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
}
@@ -73,7 +73,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
static int mtk_cg_enable(struct clk_hw *hw)
{
mtk_cg_clr_bit(hw);
@@ -85,6 +105,30 @@
@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct cl
mtk_cg_clr_bit(hw);
}
@@ -104,7 +104,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
const struct clk_ops mtk_clk_gate_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable,
@@ -97,6 +141,18 @@
@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_se
.disable = mtk_cg_disable_inv,
};
@@ -125,7 +125,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
const char *parent_name,
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -36,6 +36,8 @@
@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_mt
extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
@@ -1349,7 +1349,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
+ mtk_apmixedsys_init);
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -244,3 +244,28 @@
@@ -244,3 +244,28 @@ void mtk_clk_register_composites(const s
clk_data->clks[mc->id] = clk;
}
}
@@ -1380,7 +1380,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
+}
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -121,7 +121,8 @@
@@ -121,7 +121,8 @@ struct mtk_composite {
.flags = CLK_SET_RATE_PARENT, \
}
@@ -1390,7 +1390,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
.id = _id, \
.parent = _parent, \
.name = _name, \
@@ -156,8 +157,36 @@
@@ -156,8 +157,36 @@ struct mtk_gate {
const struct clk_ops *ops;
};

2
target/linux/mediatek/patches-4.9/0012-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch
View File

@@ -16,7 +16,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -14,6 +14,10 @@
@@ -14,6 +14,10 @@ config MACH_MT2701
bool "MediaTek MT2701 SoCs support"
default ARCH_MEDIATEK

2
target/linux/mediatek/patches-4.9/0017-clk-add-hifsys-reset.patch
View File

@@ -20,7 +20,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -1000,6 +1000,8 @@
@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

6
target/linux/mediatek/patches-4.9/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch
View File

@@ -19,7 +19,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -29,6 +29,7 @@
@@ -29,6 +29,7 @@ config MACH_MT6592
config MACH_MT7623
bool "MediaTek MT7623 SoCs support"
default ARCH_MEDIATEK
@@ -29,7 +29,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
bool "MediaTek MT8127 SoCs support"
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -301,4 +301,15 @@
@@ -301,4 +301,15 @@ config VMD
To compile this driver as a module, choose M here: the
module will be called vmd.
@@ -47,7 +47,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
endmenu
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -33,3 +33,4 @@
@@ -33,3 +33,4 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-arm
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
obj-$(CONFIG_VMD) += vmd.o

2
target/linux/mediatek/patches-4.9/0026-scpsys-various-fixes.patch
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@@ -11,7 +11,7 @@ Subject: [PATCH 026/102] scpsys: various fixes
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -1043,6 +1043,8 @@
@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struc
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

4
target/linux/mediatek/patches-4.9/0052-clk-dont-disable-unused-clocks.patch
View File

@@ -10,8 +10,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -233,7 +233,7 @@ unlock_out:
clk_enable_unlock(flags);
@@ -796,7 +796,7 @@ unlock_out:
clk_core_disable_unprepare(core->parent);
}
-static bool clk_ignore_unused;

8
target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch
View File

@@ -193,7 +193,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
#include <dt-bindings/clock/mt2701-clk.h>
@@ -465,6 +466,10 @@
@@ -465,6 +466,10 @@ static const char * const cpu_parents[]
"mmpll"
};
@@ -204,7 +204,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
static const struct mtk_composite top_muxes[] __initconst = {
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0040, 0, 3, INVALID_MUX_GATE_BIT),
@@ -677,6 +682,9 @@
@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
clk_data);
@@ -224,7 +224,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
#include <dt-bindings/clock/mt8173-clk.h>
@@ -525,6 +526,25 @@
@@ -525,6 +526,25 @@ static const char * const i2s3_b_ck_pare
"apll2_div5"
};
@@ -250,7 +250,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
static const struct mtk_composite top_muxes[] __initconst = {
/* CLK_CFG_0 */
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
@@ -948,6 +968,9 @@
@@ -948,6 +968,9 @@ static void __init mtk_infrasys_init(str
clk_data);
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);

6
target/linux/mediatek/patches-4.9/0055-cpufreq-mediatek-add-driver.patch
View File

@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
@@ -74,6 +74,15 @@ config ARM_KIRKWOOD_CPUFREQ
This adds the CPUFreq driver for Marvell Kirkwood
SoCs.
@@ -27,11 +27,11 @@ Signed-off-by: John Crispin <john@phrozen.org>
+ This adds the CPUFreq driver support for Mediatek MT7623 SoC.
+
config ARM_MT8173_CPUFREQ
bool "Mediatek MT8173 CPUFreq support"
tristate "Mediatek MT8173 CPUFreq support"
depends on ARCH_MEDIATEK && REGULATOR
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += h
@@ -58,6 +58,7 @@ obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += hi
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o

4
target/linux/mediatek/patches-4.9/0071-pwm-add-pwm-mediatek.patch
View File

@@ -43,7 +43,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
+};*/
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -282,6 +282,15 @@
@@ -282,6 +282,15 @@ config PWM_MTK_DISP
To compile this driver as a module, choose M here: the module
will be called pwm-mtk-disp.
@@ -61,7 +61,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
depends on ARCH_MXS && OF
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -25,6 +25,7 @@
@@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o

18
target/linux/mediatek/patches-4.9/0101-net-mediatek-add-gsw-mt7530-driver.patch
View File

@@ -2213,7 +2213,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
static int mtk_msg_level = -1;
module_param_named(msg_level, mtk_msg_level, int, 0);
MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
@@ -74,14 +77,14 @@
@@ -74,14 +77,14 @@ static int mtk_mdio_busy_wait(struct mtk
return 0;
if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
break;
@@ -2230,7 +2230,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
u32 phy_register, u32 write_data)
{
if (mtk_mdio_busy_wait(eth))
@@ -100,7 +103,7 @@
@@ -100,7 +103,7 @@ static u32 _mtk_mdio_write(struct mtk_et
return 0;
}
@@ -2239,7 +2239,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
u32 d;
@@ -155,7 +158,7 @@
@@ -155,7 +158,7 @@ static void mtk_gmac0_rgmii_adjust(struc
val = (speed == SPEED_1000) ?
RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
@@ -2248,7 +2248,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
val = (speed == SPEED_1000) ?
TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
@@ -1833,15 +1836,6 @@
@@ -1833,15 +1836,6 @@ static int mtk_hw_init(struct mtk_eth *e
}
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
@@ -2264,7 +2264,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
/* GE1, Force 1000M/FD, FC ON */
mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
@@ -1851,6 +1845,8 @@
@@ -1851,6 +1845,8 @@ static int mtk_hw_init(struct mtk_eth *e
/* Enable RX VLan Offloading */
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
@@ -2273,7 +2273,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
/* disable delay and normal interrupt */
mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
@@ -1879,6 +1875,8 @@
@@ -1879,6 +1875,8 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
}
@@ -2282,7 +2282,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return 0;
}
@@ -2379,6 +2377,9 @@
@@ -2379,6 +2377,9 @@ static int mtk_probe(struct platform_dev
if (!eth)
return -ENOMEM;
@@ -2303,7 +2303,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
@@ -554,6 +554,9 @@
@@ -554,6 +554,9 @@ struct mtk_eth {
struct mii_bus *mii_bus;
struct work_struct pending_work;
unsigned long state;
@@ -2313,7 +2313,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
};
/* struct mtk_mac - the structure that holds the info about the MACs of the
@@ -586,4 +589,6 @@
@@ -586,4 +589,6 @@ void mtk_stats_update_mac(struct mtk_mac
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);

4
target/linux/mediatek/patches-4.9/0103-nand_fixes.patch
View File

@@ -1,6 +1,6 @@
--- a/drivers/mtd/nand/mtk_nand.c
+++ b/drivers/mtd/nand/mtk_nand.c
@@ -1017,8 +1017,8 @@ static int mtk_nfc_ooblayout_free(struct
@@ -1073,8 +1073,8 @@ static int mtk_nfc_ooblayout_free(struct
if (section >= eccsteps)
return -ERANGE;
@@ -11,7 +11,7 @@
return 0;
}
@@ -1058,7 +1058,7 @@ static void mtk_nfc_set_fdm(struct mtk_n
@@ -1114,7 +1114,7 @@ static void mtk_nfc_set_fdm(struct mtk_n
fdm->reg_size = NFI_FDM_MAX_SIZE;
/* bad block mark storage */

2
target/linux/mediatek/patches-4.9/0200-devicetree.patch
View File

@@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -775,6 +775,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -950,6 +950,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt7623-evb.dtb \