arc: use patched .dts from sources
Instead of using off-the-tree .dts files for ARC boards we're switching to use in-tree ones. And for that to work properly we apply upstream patch that adds currently missing "model" property. Upstream patch and discussion could be found here: http://lists.infradead.org/pipermail/linux-snps-arc/2016-August/001394.html Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jonas Gorski <jonas.gorski@gmail.com> Cc: John Crispin <john@phrozen.org>
This commit is contained in:
Alexey Brodkin
committed by
John Crispin
John Crispin
parent
c41506625a
commit
a3cde14f5a
@@ -1,100 +0,0 @@
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/*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC001 770D/EM6/AS221 CPU card
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* Note that this file only supports the 770D CPU
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*/
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/ {
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compatible = "snps,arc";
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clock-frequency = <750000000>; /* 750 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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cpu_intc: arc700-intc@cpu {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/*
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* this GPIO block ORs all interrupts on CPU card (creg,..)
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* to uplink only 1 IRQ to ARC core intc
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*/
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dw-apb-gpio@0x2000 {
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compatible = "snps,dw-apb-gpio";
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reg = < 0x2000 0x80 >;
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#address-cells = <1>;
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#size-cells = <0>;
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ictl_intc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <15>;
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};
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33333000>;
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interrupt-parent = <&ictl_intc>;
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interrupts = <19 4>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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arcpmu0: pmu {
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compatible = "snps,arc700-pct";
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};
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};
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/*
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* This INTC is actually connected to DW APB GPIO
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* which acts as a wire between MB INTC and CPU INTC.
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* GPIO INTC is configured in platform init code
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* and here we mimic direct connection from MB INTC to
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* CPU INTC, thus we set "interrupts = <7>" instead of
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* "interrupts = <12>"
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*
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* This intc actually resides on MB, but we move it here to
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* avoid duplicating the MB dtsi file given that IRQ from
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* this intc to cpu intc are different for axs101 and axs103
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*/
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = < 7 >;
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};
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x40000000>;
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512MiB */
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};
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};
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@@ -1,22 +0,0 @@
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/*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* ARC AXS101 S/W development platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "axc001.dtsi"
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/include/ "axs10x_mb.dtsi"
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/ {
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model = "Synopsys AXS101 Development Board";
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compatible = "snps,axs101", "snps,arc-sdp";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8";
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};
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};
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@@ -1,225 +0,0 @@
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/*
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* Support for peripherals on the AXS10x mainboard
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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axs10x_mb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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clocks {
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i2cclk: i2cclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmcclk: mmcclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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};
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ethernet@0x18000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = < 0x18000 0x2000 >;
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interrupts = < 4 >;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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};
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ehci@0x40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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interrupts = < 8 >;
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};
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ohci@0x60000 {
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compatible = "generic-ohci";
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reg = < 0x60000 0x100 >;
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interrupts = < 8 >;
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};
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/*
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* According to DW Mobile Storage databook it is required
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* to use "Hold Register" if card is enumerated in SDR12 or
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* SDR25 modes.
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*
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* Utilization of "Hold Register" is already implemented via
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* dw_mci_pltfm_prepare_command() which in its turn gets
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* used through dw_mci_drv_data->prepare_command call-back.
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* This call-back is used in Altera Socfpga platform and so
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* we may reuse it saying that we're compatible with their
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* "altr,socfpga-dw-mshc".
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*
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* Most probably "Hold Register" utilization is platform-
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* independent requirement which means that single unified
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* "snps,dw-mshc" should be enough for all users of DW MMC once
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* dw_mci_pltfm_prepare_command() is used in generic platform
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* code.
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*/
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mmc@0x15000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = < 0x15000 0x400 >;
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num-slots = < 1 >;
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fifo-depth = < 16 >;
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card-detect-delay = < 200 >;
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clocks = <&apbclk>, <&mmcclk>;
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clock-names = "biu", "ciu";
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interrupts = < 7 >;
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bus-width = < 4 >;
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};
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uart@0x20000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <17>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@0x21000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x21000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <18>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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/* UART muxed with USB data port (ttyS3) */
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uart@0x22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <19>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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i2c@0x1d000 {
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compatible = "snps,designware-i2c";
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reg = <0x1d000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <14>;
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};
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i2c@0x1e000 {
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compatible = "snps,designware-i2c";
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reg = <0x1e000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <15>;
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};
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i2c@0x1f000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <16>;
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eeprom@0x54{
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compatible = "24c01";
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reg = <0x54>;
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pagesize = <0x8>;
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};
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eeprom@0x57{
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compatible = "24c04";
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reg = <0x57>;
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pagesize = <0x8>;
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};
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};
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gpio0:gpio@13000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x13000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio0_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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gpio0_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <1>;
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};
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gpio0_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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gpio1:gpio@14000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x14000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio1_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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};
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gpio1_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <10>;
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reg = <1>;
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};
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gpio1_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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};
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};
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@@ -1,71 +0,0 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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model = "Synopsys ARC770 nSIM simulator";
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compatible = "snps,nsim";
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clock-frequency = <80000000>; /* 80 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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intc: interrupt-controller {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupts = <5>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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ethernet@c0fc2000 {
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compatible = "snps,arc-emac";
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reg = <0xc0fc2000 0x3c>;
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interrupts = <6>;
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mac-address = [ 00 11 22 33 44 55 ];
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clock-frequency = <80000000>;
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max-speed = <100>;
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phy = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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arcpmu0: pmu {
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compatible = "snps,arc700-pct";
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};
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};
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};
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@@ -1,37 +0,0 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Skeleton device tree; the bare minimum needed to boot; just include and
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* add a compatible value.
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*/
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/ {
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compatible = "snps,arc";
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clock-frequency = <80000000>; /* 80 MHZ */
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,arc770d";
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reg = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256M */
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};
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};
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@@ -15,7 +15,7 @@ define Build/calculate-ep
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endef
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define Build/patch-dtb
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$(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb)
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$(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$@.dtb)
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$(STAGING_DIR_HOST)/bin/patch-dtb $@ $@.dtb
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endef
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