realtek: add support for Hasivo S1100W-8XGT-SE switch
This commit adds support for Hasivo S1100W-8XGT-SE switch.
Device specification
--------------------
SoC Type: RTL9303
RAM: Samsung K4B461646E-BYKO (512MB)
Flash: Fudan FM25Q128A (16 MB)
Ethernet: 8x 10G via 2x RTL8264 PHY
LEDs: 2 LEDs, 1 power green, 1 system green
Button: Reset
USB ports: None
Bootloader: Realtek U-Boot - U-Boot 2011.12.(3.6.6.55087) (Nov 13 2022 - 14:37:31)
Fan: 2 fans controlled by STC8G1K08 TSOP-20 microcontroller
Note: The fan appears to operate the same irrespective of the running
firmware. The STC9G1K08 is likely operating independently.
To explore the stock vendor firmware, there are 2 avenues to gain root
access. This is not necessary to install OpenWrt, but is here for
reference.
Root access via serial
----------------------
1. ctrl+t
2. password: switchrtk
3. press 's' for shell
Root access via SSH
-------------------
1. ctrl+t
2. password: switchrtk
3. sys command sh
4. log in with your username+password
5. ctrl+t
6. password: switchrtk
7. press 's' for shell
Credit to https://forum.openwrt.org/t/hasivo-switches/151758/174 for rooting instructions.
Installing OpenWrt
------------------
1. Connect to UART. UART requires soldering an RJ45 connector to the
console footprint on the board. The header is on the top right of
this image: 4d2ab97fad.jpeg
2. Set computer IP to 192.168.0.111.
3. Enter bootloader by pressing esc key during boot.
4. Enter password 'Hs2021cfgmg'.
5. Type 'XXXX'.
6. setenv bootcmd 'rtk network on; bootm 0xb4300000'
7. saveenv
8. rtk network on
9. tftpboot 0x84f00000 <openwrt-initramfs>
10. bootm 0x84f00000
Now you can copy over the sysupgrade image and install.
Credit to
https://forum.openwrt.org/t/hasivo-switches/151758/22?u=andrewjlamarche
for u-boot console access instructions.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17137
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Andrew LaMarche
committed by
Hauke Mehrtens
Hauke Mehrtens
parent
6fa1775348
commit
ed7d62caf2
275
target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
Normal file
275
target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
Normal file
@@ -0,0 +1,275 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "hasivo,s1100w-8xgt-se", "realtek,rtl930x-soc";
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model = "Hasivo S1100W-8XGT-SE";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
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<0x20000000 0x10000000>; /* 256 MiB highmem */
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_sys: led-0 {
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gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/*
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* LED set 0
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*
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* - LED[0](Amber): 5G/LINK/ACT
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* - LED[1](Green): 10G/LINK/ACT
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* - LED[2](Amber): 1G/100M/10M/LINK/ACT
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* - LED[3](Green): 2.5G/LINK/ACT
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*/
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led_set0 = <0x0a02 0x0a01 0x0ba0 0x0a08>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* stock is LOADER */
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x00e0000>;
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read-only;
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};
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/* stock is BDINFO */
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partition@e0000 {
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label = "u-boot-env";
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reg = <0x00e0000 0x0010000>;
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};
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/* stock is SYSINFO */
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0x00f0000 0x0010000>;
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read-only;
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};
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/* stock is JFFS2_CFG */
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partition@100000 {
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label = "jffs";
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reg = <0x0100000 0x0100000>;
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};
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/* stock is JFFS2_LOG */
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partition@200000 {
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label = "jffs2";
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reg = <0x0200000 0x0100000>;
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};
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/* stock is RUNTIME */
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partition@300000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x0300000 0x0c00000>;
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};
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/* stock is OEMINFO */
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partition@f00000 {
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label = "oeminfo";
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reg = <0x0f00000 0x0100000>;
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read-only;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 0>;
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reg = <0>;
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sds = <2>;
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};
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phy8: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 1>;
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reg = <8>;
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sds = <3>;
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};
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phy16: ethernet-phy@16 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 2>;
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reg = <16>;
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sds = <4>;
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};
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phy20: ethernet-phy@20 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <0 3>;
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reg = <20>;
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sds = <5>;
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};
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phy24: ethernet-phy@24 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <3 16>;
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reg = <24>;
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sds = <6>;
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};
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phy25: ethernet-phy@25 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <3 17>;
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reg = <25>;
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sds = <7>;
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};
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phy26: ethernet-phy@26 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <3 18>;
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reg = <26>;
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sds = <8>;
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};
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phy27: ethernet-phy@27 {
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <3 19>;
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reg = <27>;
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sds = <9>;
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};
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-mode = "usxgmii";
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phy-handle = <&phy0>;
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led-set = <0>;
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};
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port@8 {
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reg = <8>;
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label = "lan2";
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phy-mode = "usxgmii";
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phy-handle = <&phy8>;
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led-set = <0>;
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};
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port@16 {
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reg = <16>;
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label = "lan3";
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phy-mode = "usxgmii";
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phy-handle = <&phy16>;
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led-set = <0>;
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};
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port@20 {
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reg = <20>;
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label = "lan4";
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phy-mode = "usxgmii";
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phy-handle = <&phy20>;
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led-set = <0>;
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};
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port@24 {
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reg = <24>;
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label = "lan5";
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phy-mode = "usxgmii";
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phy-handle = <&phy24>;
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led-set = <0>;
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};
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port@25 {
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reg = <25>;
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label = "lan6";
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phy-mode = "usxgmii";
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phy-handle = <&phy25>;
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led-set = <0>;
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};
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port@26 {
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reg = <26>;
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label = "lan7";
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phy-mode = "usxgmii";
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phy-handle = <&phy26>;
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led-set = <0>;
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};
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port@27 {
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reg = <27>;
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label = "lan8";
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phy-mode = "usxgmii";
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phy-handle = <&phy27>;
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led-set = <0>;
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};
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/* Internal SoC */
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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};
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@@ -5,6 +5,19 @@ define Build/xikestor-nosimg
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mv $@.new $@
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mv $@.new $@
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endef
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endef
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define Device/hasivo_s1100w-8xgt-se
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SOC := rtl9303
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DEVICE_VENDOR := Hasivo
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DEVICE_MODEL := S1100W-8XGT-SE
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IMAGE_SIZE := 12288k
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KERNEL_INITRAMFS := \
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kernel-bin | \
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append-dtb | \
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lzma | \
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uImage lzma
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endef
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TARGET_DEVICES += hasivo_s1100w-8xgt-se
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define Device/tplink_tl-st1008f_v2
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define Device/tplink_tl-st1008f_v2
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SOC := rtl9303
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SOC := rtl9303
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UIMAGE_MAGIC := 0x93030000
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UIMAGE_MAGIC := 0x93030000
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@@ -195,6 +195,7 @@ CONFIG_REGMAP_I2C=y
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CONFIG_REGMAP_MDIO=y
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CONFIG_REGMAP_MDIO=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RTL8261N_PHY=y
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# CONFIG_RTL838X is not set
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# CONFIG_RTL838X is not set
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# CONFIG_RTL839X is not set
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# CONFIG_RTL839X is not set
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CONFIG_RTL930X=y
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CONFIG_RTL930X=y
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Reference in New Issue
Block a user