 1cfd45ae0b
			
		
	
	1cfd45ae0b
	
	
	
		
			
			Adds support for debugfs on RTL9300, in particular the drop counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
		
			
				
	
	
		
			604 lines
		
	
	
		
			21 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			604 lines
		
	
	
		
			21 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-only
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| 
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| #include <linux/debugfs.h>
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| #include <linux/kernel.h>
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| 
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| #include <asm/mach-rtl838x/mach-rtl83xx.h>
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| #include "rtl83xx.h"
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| 
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| #define RTL838X_DRIVER_NAME "rtl838x"
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| 
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| #define RTL8380_LED_GLB_CTRL			(0xA000)
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| #define RTL8380_LED_MODE_SEL			(0x1004)
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| #define RTL8380_LED_MODE_CTRL			(0xA004)
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| #define RTL8380_LED_P_EN_CTRL			(0xA008)
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| #define RTL8380_LED_SW_CTRL			(0xA00C)
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| #define RTL8380_LED0_SW_P_EN_CTRL		(0xA010)
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| #define RTL8380_LED1_SW_P_EN_CTRL		(0xA014)
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| #define RTL8380_LED2_SW_P_EN_CTRL		(0xA018)
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| #define RTL8380_LED_SW_P_CTRL(p)		(0xA01C + (((p) << 2)))
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| 
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| #define RTL8390_LED_GLB_CTRL			(0x00E4)
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| #define RTL8390_LED_SET_2_3_CTRL		(0x00E8)
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| #define RTL8390_LED_SET_0_1_CTRL		(0x00EC)
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| #define RTL8390_LED_COPR_SET_SEL_CTRL(p)	(0x00F0 + (((p >> 4) << 2)))
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| #define RTL8390_LED_FIB_SET_SEL_CTRL(p)		(0x0100 + (((p >> 4) << 2)))
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| #define RTL8390_LED_COPR_PMASK_CTRL(p)		(0x0110 + (((p >> 5) << 2)))
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| #define RTL8390_LED_FIB_PMASK_CTRL(p)		(0x00118 + (((p >> 5) << 2)))
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| #define RTL8390_LED_COMBO_CTRL(p)		(0x0120 + (((p >> 5) << 2)))
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| #define RTL8390_LED_SW_CTRL			(0x0128)
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| #define RTL8390_LED_SW_P_EN_CTRL(p)		(0x012C + (((p / 10) << 2)))
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| #define RTL8390_LED_SW_P_CTRL(p)		(0x0144 + (((p) << 2)))
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| 
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| #define RTL838X_MIR_QID_CTRL(grp)		(0xAD44 + (((grp) << 2)))
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| #define RTL838X_MIR_RSPAN_VLAN_CTRL(grp)	(0xA340 + (((grp) << 2)))
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| #define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp)	(0xAA70 + (((grp) << 2)))
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| #define RTL838X_MIR_RSPAN_TX_CTRL		(0xA350)
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| #define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL	(0xAA80)
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| #define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL	(0xAA84)
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| #define RTL839X_MIR_RSPAN_VLAN_CTRL(grp)	(0xA340 + (((grp) << 2)))
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| #define RTL839X_MIR_RSPAN_TX_CTRL		(0x69b0)
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| #define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL	(0x2550)
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| #define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL	(0x2554)
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| #define RTL839X_MIR_SAMPLE_RATE_CTRL		(0x2558)
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| 
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| #define RTL838X_STAT_PRVTE_DROP_COUNTERS	(0x6A00)
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| #define RTL839X_STAT_PRVTE_DROP_COUNTERS	(0x3E00)
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| #define RTL930X_STAT_PRVTE_DROP_COUNTERS	(0xB5B8)
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| 
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| int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
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| void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
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| void rtl83xx_fast_age(struct dsa_switch *ds, int port);
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| u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
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| u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
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| int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
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| int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
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| 
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| 
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| const char *rtl838x_drop_cntr[] = {
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|     "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP",
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|     "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP",
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|     "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP",
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|     "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP",
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|     "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP",
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|     "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP",
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|     "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP",
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|     "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP",
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|     "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP",
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|     "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards"
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| };
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| 
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| const char *rtl839x_drop_cntr[] = {
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|     "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
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|     "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
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|     "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
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|     "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
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|     "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
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|     "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING",
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|     "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP",
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|     "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE",
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|     "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL",
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|     "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR",
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|     "LINK_STATUS_BEFORE_MIRROR",
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|     "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR",
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|     "LINK_STATUS_AFTER_MIRROR",
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|     "WRED_AFTER_MIRROR"
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| };
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| 
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| const char *rtl930x_drop_cntr[] = {
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| 	"OAM_PARSER", "UC_RPF", "DEI_CFI", "MAC_IP_SUBNET_BASED_VLAN", "VLAN_IGR_FILTER",
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| 	"L2_UC_MC", "IPV_IP6_MC_BRIDGE", "PTP", "USER_DEF_0_3", "RESERVED",
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| 	"RESERVED1", "RESERVED2", "BPDU_RMA", "LACP", "LLDP",
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| 	"EAPOL", "XX_RMA", "L3_IPUC_NON_IP", "IP4_IP6_HEADER_ERROR", "L3_BAD_IP",
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| 	"L3_DIP_DMAC_MISMATCH", "IP4_IP_OPTION", "IP_UC_MC_ROUTING_LOOK_UP_MISS", "L3_DST_NULL_INTF",
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| 	"L3_PBR_NULL_INTF",
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| 	"HOST_NULL_INTF", "ROUTE_NULL_INTF", "BRIDGING_ACTION", "ROUTING_ACTION", "IPMC_RPF",
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| 	"L2_NEXTHOP_AGE_OUT", "L3_UC_TTL_FAIL", "L3_MC_TTL_FAIL", "L3_UC_MTU_FAIL", "L3_MC_MTU_FAIL",
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| 	"L3_UC_ICMP_REDIR", "IP6_MLD_OTHER_ACT", "ND", "IP_MC_RESERVED", "IP6_HBH",
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| 	"INVALID_SA", "L2_HASH_FULL", "NEW_SA", "PORT_MOVE_FORBID", "STATIC_PORT_MOVING",
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| 	"DYNMIC_PORT_MOVING", "L3_CRC", "MAC_LIMIT", "ATTACK_PREVENT", "ACL_FWD_ACTION",
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| 	"OAMPDU", "OAM_MUX", "TRUNK_FILTER", "ACL_DROP", "IGR_BW",
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| 	"ACL_METER", "VLAN_ACCEPT_FRAME_TYPE", "MSTP_SRC_DROP_DISABLED_BLOCKING", "SA_BLOCK", "DA_BLOCK",
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| 	"STORM_CONTROL", "VLAN_EGR_FILTER", "MSTP_DESTINATION_DROP", "SRC_PORT_FILTER", "PORT_ISOLATION",
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| 	"TX_MAX_FRAME_SIZE", "EGR_LINK_STATUS", "MAC_TX_DISABLE", "MAC_PAUSE_FRAME", "MAC_RX_DROP",
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| 	"MIRROR_ISOLATE", "RX_FC", "EGR_QUEUE", "HSM_RUNOUT", "ROUTING_DISABLE", "INVALID_L2_NEXTHOP_ENTRY",
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| 	"L3_MC_SRC_FLT", "CPUTAG_FLT", "FWD_PMSK_NULL", "IPUC_ROUTING_LOOKUP_MISS", "MY_DEV_DROP",
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| 	"STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER"
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| };
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| 
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| static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
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| 					loff_t *ppos, unsigned int value)
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| {
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| 	char *buf;
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| 	ssize_t len;
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| 
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| 	if (*ppos != 0)
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| 		return 0;
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| 
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| 	buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
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| 	if (!buf)
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| 		return -ENOMEM;
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| 
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| 	if (count < strlen(buf)) {
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| 		kfree(buf);
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| 		return -ENOSPC;
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| 	}
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| 
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| 	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
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| 	kfree(buf);
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| 
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| 	return len;
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| }
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| 
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| static ssize_t rtl838x_common_write(const char __user *buffer, size_t count,
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| 				 loff_t *ppos, unsigned int *value)
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| {
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| 	char b[32];
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| 	ssize_t len;
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| 	int ret;
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| 
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| 	if (*ppos != 0)
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| 		return -EINVAL;
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| 
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| 	if (count >= sizeof(b))
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| 		return -ENOSPC;
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| 
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| 	len = simple_write_to_buffer(b, sizeof(b) - 1, ppos,
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| 				     buffer, count);
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| 	if (len < 0)
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| 		return len;
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| 
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| 	b[len] = '\0';
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| 	ret = kstrtouint(b, 16, value);
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| 	if (ret)
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| 		return -EIO;
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| 
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| 	return len;
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| }
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| 
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| static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,
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| 			     loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	struct dsa_switch *ds = p->dp->ds;
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| 	int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index);
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| 
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| 	if (value < 0)
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| 		return -EINVAL;
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| 
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| 	return rtl838x_common_read(buffer, count, ppos, (u32)value);
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| }
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| 
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| static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
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| 				size_t count, loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	u32 value;
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| 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
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| 	if (res < 0)
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| 		return res;
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| 
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| 	rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value);
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| 
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| 	return res;
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| }
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| 
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| static const struct file_operations stp_state_fops = {
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| 	.owner = THIS_MODULE,
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| 	.open = simple_open,
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| 	.read = stp_state_read,
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| 	.write = stp_state_write,
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| };
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| 
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| static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count,
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| 			     loff_t *ppos)
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| {
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| 	struct rtl838x_switch_priv *priv = filp->private_data;
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| 	int i;
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| 	const char **d;
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| 	u32 v;
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| 	char *buf;
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| 	int n = 0, len, offset;
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| 	int num;
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| 
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| 	switch (priv->family_id) {
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| 	case RTL8380_FAMILY_ID:
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| 		d = rtl838x_drop_cntr;
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| 		offset = RTL838X_STAT_PRVTE_DROP_COUNTERS;
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| 		num = 40;
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| 		break;
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| 	case RTL8390_FAMILY_ID:
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| 		d = rtl839x_drop_cntr;
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| 		offset = RTL839X_STAT_PRVTE_DROP_COUNTERS;
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| 		num = 45;
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| 		break;
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| 	case RTL9300_FAMILY_ID:
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| 		d = rtl930x_drop_cntr;
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| 		offset = RTL930X_STAT_PRVTE_DROP_COUNTERS;
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| 		num = 85;
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| 		break;
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| 	}
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| 
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| 	buf = kmalloc(30 * num, GFP_KERNEL);
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| 	if (!buf)
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| 		return -ENOMEM;
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| 
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| 	for (i = 0; i < num; i++) {
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| 		v = sw_r32(offset + (i << 2)) & 0xffff;
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| 		n += sprintf(buf + n, "%s: %d\n", d[i], v);
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| 	}
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| 
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| 	if (count < strlen(buf)) {
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| 		kfree(buf);
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| 		return -ENOSPC;
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| 	}
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| 
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| 	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
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| 	kfree(buf);
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| 
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| 	return len;
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| }
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| 
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| static const struct file_operations drop_counter_fops = {
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| 	.owner = THIS_MODULE,
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| 	.open = simple_open,
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| 	.read = drop_counter_read,
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| };
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| 
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| static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,
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| 			     loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	struct dsa_switch *ds = p->dp->ds;
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| 	struct rtl838x_switch_priv *priv = ds->priv;
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| 	int value = sw_r32(priv->r->l2_port_aging_out);
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| 
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| 	if (value < 0)
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| 		return -EINVAL;
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| 
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| 	return rtl838x_common_read(buffer, count, ppos, (u32)value);
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| }
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| 
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| static ssize_t age_out_write(struct file *filp, const char __user *buffer,
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| 				size_t count, loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	u32 value;
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| 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
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| 	if (res < 0)
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| 		return res;
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| 
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| 	rtl83xx_fast_age(p->dp->ds, p->dp->index);
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| 
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| 	return res;
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| }
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| 
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| static const struct file_operations age_out_fops = {
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| 	.owner = THIS_MODULE,
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| 	.open = simple_open,
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| 	.read = age_out_read,
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| 	.write = age_out_write,
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| };
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| 
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| static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,
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| 				loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	struct dsa_switch *ds = p->dp->ds;
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| 	struct rtl838x_switch_priv *priv = ds->priv;
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| 	int value;
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| 	if (priv->family_id == RTL8380_FAMILY_ID)
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| 		value = rtl838x_get_egress_rate(priv, p->dp->index);
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| 	else
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| 		value = rtl839x_get_egress_rate(priv, p->dp->index);
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| 
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| 	if (value < 0)
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| 		return -EINVAL;
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| 
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| 	return rtl838x_common_read(buffer, count, ppos, (u32)value);
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| }
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| 
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| static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,
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| 				size_t count, loff_t *ppos)
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| {
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| 	struct rtl838x_port *p = filp->private_data;
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| 	struct dsa_switch *ds = p->dp->ds;
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| 	struct rtl838x_switch_priv *priv = ds->priv;
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| 	u32 value;
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| 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
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| 	if (res < 0)
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| 		return res;
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| 
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| 	if (priv->family_id == RTL8380_FAMILY_ID)
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| 		rtl838x_set_egress_rate(priv, p->dp->index, value);
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| 	else
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| 		rtl839x_set_egress_rate(priv, p->dp->index, value);
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| 
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| 	return res;
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| }
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| 
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| static const struct file_operations port_egress_fops = {
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| 	.owner = THIS_MODULE,
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| 	.open = simple_open,
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| 	.read = port_egress_rate_read,
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| 	.write = port_egress_rate_write,
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| };
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| 
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| 
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| static const struct debugfs_reg32 port_ctrl_regs[] = {
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| 	{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
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| 	{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
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| };
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| 
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| void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
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| {
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| 	debugfs_remove_recursive(priv->dbgfs_dir);
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| 
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| //	kfree(priv->dbgfs_entries);
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| }
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| 
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| static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
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| 				   int port)
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| {
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| 	struct dentry *port_dir;
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| 	struct debugfs_regset32 *port_ctrl_regset;
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| 
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| 	port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
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| 
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| 	if (priv->family_id == RTL8380_FAMILY_ID) {
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| 		debugfs_create_x32("storm_rate_uc", 0644, port_dir,
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| 				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
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| 
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| 		debugfs_create_x32("storm_rate_mc", 0644, port_dir,
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| 				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
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| 
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| 		debugfs_create_x32("storm_rate_bc", 0644, port_dir,
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| 				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
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| 
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| 		debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
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| 				(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL 
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| 				+ (port << 2)));
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| 	} else {
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| 		debugfs_create_x32("storm_rate_uc", 0644, port_dir,
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| 				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
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| 
 | |
| 		debugfs_create_x32("storm_rate_mc", 0644, port_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
 | |
| 
 | |
| 		debugfs_create_x32("storm_rate_bc", 0644, port_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
 | |
| 
 | |
| 		debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_PORT_TAG_STS_CTRL
 | |
| 				+ (port << 2)));
 | |
| 	}
 | |
| 
 | |
| 	debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);
 | |
| 
 | |
| 	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 | |
| 	if (!port_ctrl_regset)
 | |
| 		return -ENOMEM;
 | |
| 
 | |
| 	port_ctrl_regset->regs = port_ctrl_regs;
 | |
| 	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 | |
| 	port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2));
 | |
| 	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 | |
| 
 | |
| 	debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops);
 | |
| 	debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops);
 | |
| 	debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port],
 | |
| 			    &port_egress_fops);
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv)
 | |
| {
 | |
| 	struct dentry *led_dir;
 | |
| 	int p;
 | |
| 	char led_sw_p_ctrl_name[20];
 | |
| 	char port_led_name[20];
 | |
| 
 | |
| 	led_dir = debugfs_create_dir("led", parent);
 | |
| 
 | |
| 	if (priv->family_id == RTL8380_FAMILY_ID) {
 | |
| 		debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL));
 | |
| 		debugfs_create_x32("led_mode_sel", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL));
 | |
| 		debugfs_create_x32("led_mode_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL));
 | |
| 		debugfs_create_x32("led_p_en_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL));
 | |
| 		debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL));
 | |
| 		debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL));
 | |
| 		debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL));
 | |
| 		debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL));
 | |
| 		for (p = 0; p < 28; p++) {
 | |
| 			snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),
 | |
| 				 "led_sw_p_ctrl.%02d", p);
 | |
| 			debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p)));
 | |
| 		}
 | |
| 	} else if (priv->family_id == RTL8390_FAMILY_ID) {
 | |
| 		debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
 | |
| 		debugfs_create_x32("led_set_2_3", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
 | |
| 		debugfs_create_x32("led_set_0_1", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
 | |
| 		for (p = 0; p < 4; p++) {
 | |
| 			snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p);
 | |
| 			debugfs_create_x32(port_led_name, 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
 | |
| 			snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p);
 | |
| 			debugfs_create_x32(port_led_name, 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
 | |
| 		}
 | |
| 		debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
 | |
| 		debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
 | |
| 		debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
 | |
| 		debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
 | |
| 		debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
 | |
| 		debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
 | |
| 		debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
 | |
| 		for (p = 0; p < 5; p++) {
 | |
| 			snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p);
 | |
| 			debugfs_create_x32(port_led_name, 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
 | |
| 		}
 | |
| 		for (p = 0; p < 28; p++) {
 | |
| 			snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p);
 | |
| 			debugfs_create_x32(port_led_name, 0644, led_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
 | |
| 		}
 | |
| 	}
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
 | |
| {
 | |
| 	struct dentry *rtl838x_dir;
 | |
| 	struct dentry *port_dir;
 | |
| 	struct dentry *mirror_dir;
 | |
| 	struct debugfs_regset32 *port_ctrl_regset;
 | |
| 	int ret, i;
 | |
| 	char lag_name[10];
 | |
| 	char mirror_name[10];
 | |
| 
 | |
| 	pr_info("%s called\n", __func__);
 | |
| 	rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
 | |
| 	if (!rtl838x_dir)
 | |
| 		rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
 | |
| 
 | |
| 	priv->dbgfs_dir = rtl838x_dir;
 | |
| 
 | |
| 	debugfs_create_u32("soc", 0444, rtl838x_dir,
 | |
| 			   (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
 | |
| 
 | |
| 	/* Create one directory per port */
 | |
| 	for (i = 0; i < priv->cpu_port; i++) {
 | |
| 		if (priv->ports[i].phy) {
 | |
| 			ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
 | |
| 			if (ret)
 | |
| 				goto err;
 | |
| 		}
 | |
| 	}
 | |
| 
 | |
| 	/* Create directory for CPU-port */
 | |
| 	port_dir = debugfs_create_dir("cpu_port", rtl838x_dir);
 | |
| 	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
 | |
| 	if (!port_ctrl_regset) {
 | |
| 		ret = -ENOMEM;
 | |
| 		goto err;
 | |
| 	}
 | |
| 
 | |
| 	port_ctrl_regset->regs = port_ctrl_regs;
 | |
| 	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
 | |
| 	port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));
 | |
| 	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
 | |
| 	debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
 | |
| 
 | |
| 	/* Create entries for LAGs */
 | |
| 	for (i = 0; i < priv->n_lags; i++) {
 | |
| 		snprintf(lag_name, sizeof(lag_name), "lag.%02d", i);
 | |
| 		if (priv->family_id == RTL8380_FAMILY_ID)
 | |
| 			debugfs_create_x32(lag_name, 0644, rtl838x_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 | |
| 		else
 | |
| 			debugfs_create_x64(lag_name, 0644, rtl838x_dir,
 | |
| 				(u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
 | |
| 	}
 | |
| 
 | |
| 	/* Create directories for mirror groups */
 | |
| 	for (i = 0; i < 4; i++) {
 | |
| 		snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i);
 | |
| 		mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);
 | |
| 		if (priv->family_id == RTL8380_FAMILY_ID) {
 | |
| 			debugfs_create_x32("ctrl", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
 | |
| 			debugfs_create_x32("ingress_pm", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4));
 | |
| 			debugfs_create_x32("egress_pm", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4));
 | |
| 			debugfs_create_x32("qid", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
 | |
| 			debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
 | |
| 			debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
 | |
| 			debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
 | |
| 			debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
 | |
| 			debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
 | |
| 		} else {
 | |
| 			debugfs_create_x32("ctrl", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
 | |
| 			debugfs_create_x64("ingress_pm", 0644, mirror_dir,
 | |
| 				(u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8));
 | |
| 			debugfs_create_x64("egress_pm", 0644, mirror_dir,
 | |
| 				(u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8));
 | |
| 			debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
 | |
| 			debugfs_create_x32("rspan_tx", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
 | |
| 			debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
 | |
| 			debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
 | |
| 			debugfs_create_x64("sample_rate", 0644, mirror_dir,
 | |
| 				(u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
 | |
| 		}
 | |
| 	}
 | |
| 
 | |
| 	if (priv->family_id == RTL8380_FAMILY_ID)
 | |
| 		debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 | |
| 	else
 | |
| 		debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir,
 | |
| 				(u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
 | |
| 
 | |
| 	if (priv->family_id == RTL8380_FAMILY_ID)
 | |
| 		debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
 | |
| 	else
 | |
| 		debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
 | |
| 				(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
 | |
| 
 | |
| 	ret = rtl838x_dbgfs_leds(rtl838x_dir, priv);
 | |
| 	if (ret)
 | |
| 		goto err;
 | |
| 
 | |
| 	debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops);
 | |
| 
 | |
| 	return;
 | |
| err:
 | |
| 	rtl838x_dbgfs_cleanup(priv);
 | |
| }
 | |
| 
 | |
| void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv)
 | |
| {
 | |
| 	struct dentry *dbg_dir;
 | |
| 
 | |
| 	pr_info("%s called\n", __func__);
 | |
| 	dbg_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
 | |
| 	if (!dbg_dir)
 | |
| 		dbg_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
 | |
| 
 | |
| 	priv->dbgfs_dir = dbg_dir;
 | |
| 
 | |
| 	debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops);
 | |
| }
 |