2f663cab46
Replace patches for MediaTek Ethernet driver SGMII/SerDes unit with their corresponding upstream patches. Not all of the patches in our tree went upstream as-is, some are slightly different implementations, and they require the phylink_pcs helpers now made available. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From b6a709cb51f7bdc55c01cec886098a9753ce8c28 Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Thu, 27 Oct 2022 14:10:42 +0100
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Subject: [PATCH 01/10] net: mtk_eth_soc: add definitions for PCS
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As a result of help from Frank Wunderlich to investigate and test, we
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know a bit more about the PCS on the Mediatek platforms. Update the
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definitions from this investigation.
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This PCS appears similar, but not identical to the Lynx PCS.
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Although not included in this patch, but for future reference, the PHY
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ID registers at offset 4 read as 0x4d544950 'MTIP'.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 13 ++++++++++---
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1 file changed, 10 insertions(+), 3 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -501,8 +501,10 @@
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#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
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/* SGMII subsystem config registers */
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-/* Register to auto-negotiation restart */
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+/* BMCR (low 16) BMSR (high 16) */
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#define SGMSYS_PCS_CONTROL_1 0x0
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+#define SGMII_BMCR GENMASK(15, 0)
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+#define SGMII_BMSR GENMASK(31, 16)
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#define SGMII_AN_RESTART BIT(9)
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#define SGMII_ISOLATE BIT(10)
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#define SGMII_AN_ENABLE BIT(12)
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@@ -512,13 +514,18 @@
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#define SGMII_PCS_FAULT BIT(23)
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#define SGMII_AN_EXPANSION_CLR BIT(30)
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+#define SGMSYS_PCS_ADVERTISE 0x8
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+#define SGMII_ADVERTISE GENMASK(15, 0)
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+#define SGMII_LPA GENMASK(31, 16)
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+
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/* Register to programmable link timer, the unit in 2 * 8ns */
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#define SGMSYS_PCS_LINK_TIMER 0x18
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-#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
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+#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
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+#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK)
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/* Register to control remote fault */
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#define SGMSYS_SGMII_MODE 0x20
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-#define SGMII_IF_MODE_BIT0 BIT(0)
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+#define SGMII_IF_MODE_SGMII BIT(0)
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#define SGMII_SPEED_DUPLEX_AN BIT(1)
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#define SGMII_SPEED_MASK GENMASK(3, 2)
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#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
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