f31ab2abef
Some VRX518 modems fail to initialize properly with the error message "dc_ep_clk_on failed". As a result, the DSL data path doesn't work. This hack, which is based on code from the FRITZ!Box 7530 GPL archive, fixes the issue. It changes the PCIe vendor/device ID to values matching a Lantiq SoC. It also appears to emulate a Lantiq CPU ID register for connected PCIe devices, by remapping the matching address area to a specially crafted buffer using the address translation unit. A dedicated compatible is created to activate this in the device tree, so this shouldn't affect any devices other than FRITZ!Box 7530/7520. Original investigation was done in59f5212517which used the "avm,host_magic" property to enabled the patch. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Florian Maurer <f.maurer@outlook.de> Link: https://github.com/openwrt/openwrt/pull/17622 Signed-off-by: Robert Marko <robimarko@gmail.com> (cherry picked from commit676dcb1b2c)
103 lines
3.9 KiB
Diff
103 lines
3.9 KiB
Diff
From 9f4f3dfad8cf08208fbb78b1b9cbf957c12618b9 Mon Sep 17 00:00:00 2001
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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Date: Tue, 10 Oct 2023 21:29:14 +0530
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Subject: [PATCH] PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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ASPM is supported by Qcom host controllers/bridges on most of the recent
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platforms and so the devices tested so far. But for enabling ASPM by
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default (without using Kconfig, kernel command-line or sysfs), BIOS has
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to enable ASPM on both host bridge and downstream devices during boot.
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Unfortunately, none of the BIOS available on Qcom platforms enables
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ASPM. Due to this, the platforms making use of Qcom SoCs draw high power
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during runtime.
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To fix this power draw issue, users have to enable ASPM using Kconfig,
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kernel command-line, sysfs or the BIOS has to start enabling ASPM.
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The latter may happen in the future, but that won't address the issue on
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current platforms. Also, asking users to enable a feature to get the power
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management right would provide an unpleasant out-of-the-box experience.
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So the apt solution is to enable ASPM in the controller driver itself. And
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this is being accomplished by calling pci_enable_link_state() in the newly
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introduced host_post_init() callback for all the devices connected to the
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bus. This function enables all supported link low power states for both
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host bridge and the downstream devices.
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Due to limited testing, ASPM is only enabled for platforms making use of
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ops_1_9_0 callbacks.
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[kwilczynski: commit log]
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Link: https://lore.kernel.org/linux-pci/20231010155914.9516-3-manivannan.sadhasivam@linaro.org
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Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++++++++++++++++++++++++
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1 file changed, 28 insertions(+)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -222,6 +222,7 @@ struct qcom_pcie_ops {
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int (*get_resources)(struct qcom_pcie *pcie);
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int (*init)(struct qcom_pcie *pcie);
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int (*post_init)(struct qcom_pcie *pcie);
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+ void (*host_post_init)(struct qcom_pcie *pcie);
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void (*deinit)(struct qcom_pcie *pcie);
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void (*ltssm_enable)(struct qcom_pcie *pcie);
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int (*config_sid)(struct qcom_pcie *pcie);
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@@ -966,6 +967,22 @@ static int qcom_pcie_post_init_2_7_0(str
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return 0;
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}
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+static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata)
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+{
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+ /* Downstream devices need to be in D0 state before enabling PCI PM substates */
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+ pci_set_power_state(pdev, PCI_D0);
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+ pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL);
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+
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+ return 0;
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+}
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+
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+static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)
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+{
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+ struct dw_pcie_rp *pp = &pcie->pci->pp;
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+
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+ pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL);
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+}
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+
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static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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@@ -1224,9 +1241,19 @@ static void qcom_pcie_host_deinit(struct
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pcie->cfg->ops->deinit(pcie);
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}
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+static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)
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+{
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+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
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+
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+ if (pcie->cfg->ops->host_post_init)
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+ pcie->cfg->ops->host_post_init(pcie);
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+}
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+
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static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
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.host_init = qcom_pcie_host_init,
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.host_deinit = qcom_pcie_host_deinit,
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+ .host_post_init = qcom_pcie_host_post_init,
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};
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/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
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@@ -1288,6 +1315,7 @@ static const struct qcom_pcie_ops ops_1_
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.get_resources = qcom_pcie_get_resources_2_7_0,
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.init = qcom_pcie_init_2_7_0,
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.post_init = qcom_pcie_post_init_2_7_0,
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+ .host_post_init = qcom_pcie_host_post_init_2_7_0,
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.deinit = qcom_pcie_deinit_2_7_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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.config_sid = qcom_pcie_config_sid_1_9_0,
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