e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
80 lines
2.0 KiB
Diff
80 lines
2.0 KiB
Diff
From e366df2ff64e9f93a5b35eea6a198b005d5a0911 Mon Sep 17 00:00:00 2001
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From: William Qiu <william.qiu@starfivetech.com>
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Date: Fri, 22 Dec 2023 17:45:45 +0800
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Subject: [PATCH 006/116] dt-bindings: pwm: Add bindings for OpenCores PWM
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Controller
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add bindings for OpenCores PWM Controller.
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Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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---
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.../bindings/pwm/opencores,pwm.yaml | 55 +++++++++++++++++++
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1 file changed, 55 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
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@@ -0,0 +1,55 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: OpenCores PWM controller
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+
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+maintainers:
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+ - William Qiu <william.qiu@starfivetech.com>
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+
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+description:
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+ The OpenCores PTC ip core contains a PWM controller. When operating in PWM
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+ mode, the PTC core generates binary signal with user-programmable low and
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+ high periods. All PTC counters and registers are 32-bit.
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+
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+allOf:
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+ - $ref: pwm.yaml#
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - starfive,jh7100-pwm
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+ - starfive,jh7110-pwm
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+ - const: opencores,pwm-v1
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+
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+ "#pwm-cells":
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+ const: 3
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pwm@12490000 {
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+ compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
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+ reg = <0x12490000 0x10000>;
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+ clocks = <&clkgen 181>;
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+ resets = <&rstgen 109>;
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+ #pwm-cells = <3>;
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+ };
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