Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
		
			
				
	
	
		
			114 lines
		
	
	
		
			3.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			114 lines
		
	
	
		
			3.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
From 5eda2331a252436756fb40861f01a7a38b1502c7 Mon Sep 17 00:00:00 2001
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From: William Qiu <william.qiu@starfivetech.com>
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Date: Thu, 15 Jun 2023 20:14:22 +0800
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Subject: [PATCH 069/116] dt-bindings: CAN: Add StarFive CAN module
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Add documentation to describe StarFive CAN engine.
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Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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---
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 .../devicetree/bindings/net/can/ipms-can.yaml | 97 +++++++++++++++++++
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 1 file changed, 97 insertions(+)
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 create mode 100644 Documentation/devicetree/bindings/net/can/ipms-can.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/can/ipms-can.yaml
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@@ -0,0 +1,97 @@
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+# SPDX-License-Identifier: GPL-2.0
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+%YAML 1.2
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+---
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+#$id: http://devicetree.org/schemas/net/can/ipms-can.yaml#
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+#$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: IPMS CAN/CANFD controller Device Tree Bindings
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+
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+properties:
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+  compatible:
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+    const:ipms,can
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+
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+  reg:
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+    maxItems: 1
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+    items:
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+      - description:CAN controller registers
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+
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+  interrupts:
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+    maxItems: 1
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+
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+  clocks:
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+    minItems: 1
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+    items:
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+      - description:apb_clk clock
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+      - description:core_clk clock
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+      - description:timer_clk clock
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+
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+  clock-names:
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+    minItems: 1
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+    items:
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+      - const:apb_clk
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+      - const:core_clk
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+      - const:timer_clk
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+  resets:
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+   minItems: 1
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+    items:
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+      - description:apb_clk reset
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+      - description:core_clk reset
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+      - description:timer_clk reset
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+  reset-names:
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+    minItems: 1
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+    items:
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+      - const:rst_apb
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+      - const:rst_core
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+      - const:rst_timer
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+  starfive,sys-syscon:
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+    format:
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+    starfive,sys-syscon = <&arg0 arg1 arg2 arg3>
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+    description:
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+      arg0:arg0 is sys_syscon.
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+      arg1:arg1 is syscon register offset, used to enable can2.0/canfd function, can0 is 0x10, can1 is 0x88.
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+      arg2:arg2 is used to enable the register shift of the can2.0/canfd function, can0 is 0x3, can1 is 0x12.
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+      arg3:arg3 is used to enable the register mask of the can2.0/canfd function, can0 is 0x8, can1 is 0x40000
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+
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+  syscon,can_or_canfd:
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+    description:
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+    IPMS CAN-CTRL core is a serial communications controller that performs serial communication according to the CAN protocol.
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+    This CAN bus interface uses the basic CAN principle and meets all constraints of the CAN-specification 2.0B active.
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+    Furthermore this CAN core can be configured to meet the specification of CAN with flexible data rate CAN FD.
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+    When syscon,can_or_canfd is set to 0, use CAN2.0B.
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+    when syscon,can_or_canfd is set to 1, use CAN FD.
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+required:
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+  - compatible
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+  - reg
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+  - interrupts
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+  - clocks
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+  - clock-names
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+  - resets
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+  - reset-names
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+  - starfive,sys-syscon
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+  - syscon,can_or_canfd
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+additionalProperties:false
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+
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+examples:
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+  - |
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+    can0: can@130d0000{
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+    compatible = "ipms,can";
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+    reg = <0x0 0x130d0000 0x0 0x1000>;
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+    interrupts = <112>;
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+    interrupt-parent = <&plic>;
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+    clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
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+             <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
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+             <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
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+    clock-names = "apb_clk",
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+                  "core_clk",
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+                  "timer_clk";
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+    resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
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+             <&rstgen RSTN_U0_CAN_CTRL_CORE>,
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+             <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
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+    reset-names = "rst_apb",
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+                  "rst_core",
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+                  "rst_timer";
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+    starfive,sys-syscon = <&sys_syscon, 0x10 0x3 0x8>;
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+    syscon,can_or_canfd = <0>;
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+    };
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+
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+...
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