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openwrt-R7800-nss/target/linux/ipq806x/patches-6.6/990-000-Add-required-entries-in-dts-files-for-NSS-support.patch
Lucas Asvio 290156f351 ipq806x: nss patches for k6.x 
SqTER-PL <r.napierala@asta-net.pl>
2025-08-04 12:58:17 +02:00

284 lines
7.5 KiB
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi
@@ -22,6 +22,15 @@
reg = <0x41200000 0x300000>;
no-map;
};
+
+ ramoops@42100000 {
+ compatible = "ramoops";
+ reg = <0x42100000 0x40000>;
+ record-size = <0x4000>;
+ console-size = <0x4000>;
+ ftrace-size = <0x4000>;
+ pmsg-size = <0x4000>;
+ };
};
};
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -670,6 +670,20 @@
};
};
+ nss-common {
+ compatible = "qcom,nss-common";
+ reg = <0x03000000 0x00001000>;
+ reg-names = "nss_fpb_base";
+ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>,
+ <&rpmcc RPM_NSS_FABRIC_0_CLK>, <&rpmcc RPM_NSS_FABRIC_1_CLK>;
+ clock-names = "nss_core_clk", "nss_tcm_clk",
+ "nss-fab0-clk", "nss-fab1-clk";
+ nss_core-supply = <&smb208_s1b>;
+ nss_core_vdd_nominal = <1100000>;
+ nss_core_vdd_high = <1150000>;
+ nss_core_threshold_freq = <733000000>;
+ };
+
sfpb_mutex: hwlock@1200600 {
compatible = "qcom,sfpb-mutex";
reg = <0x01200600 0x100>;
@@ -856,6 +870,132 @@
status = "disabled";
};
+ nss0: nss@40000000 {
+ compatible = "qcom,nss";
+ qcom,low-frequency = <733000000>; /* orig value 110000000 */
+ qcom,mid-frequency = <733000000>; /* orig value 550000000 */
+ qcom,max-frequency = <733000000>;
+
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x36000000 0x1000 0x39000000 0x10000>;
+ reg-names = "nphys", "vphys";
+ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK_SRC>,
+ <&gcc NSSTCM_CLK>, <&rpmcc RPM_NSS_FABRIC_0_CLK>,
+ <&rpmcc RPM_NSS_FABRIC_1_CLK>;
+ clock-names = "nss-core-clk", "nss-tcm-src",
+ "nss-tcm-clk", "nss-fab0-clk",
+ "nss-fab1-clk";
+ resets = <&gcc UBI32_CORE1_CLKRST_CLAMP_RESET>,
+ <&gcc UBI32_CORE1_CLAMP_RESET>,
+ <&gcc UBI32_CORE1_AHB_RESET>,
+ <&gcc UBI32_CORE1_AXI_RESET>;
+ reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
+
+ qcom,id = <0>;
+ qcom,num-irq = <2>;
+ qcom,num-queue = <2>;
+ qcom,load-addr = <0x40000000>;
+ qcom,turbo-frequency;
+
+ qcom,bridge-enabled;
+ qcom,gre-enabled;
+ qcom,gre-redir-enabled;
+ qcom,gre_tunnel_enabled;
+ qcom,ipv4-enabled;
+ qcom,ipv4-reasm-enabled;
+ qcom,ipv6-enabled;
+ qcom,ipv6-reasm-enabled;
+ qcom,l2tpv2-enabled;
+ qcom,map-t-enabled;
+ qcom,pppoe-enabled;
+ qcom,pptp-enabled;
+ qcom,portid-enabled;
+ qcom,shaping-enabled;
+ qcom,tun6rd-enabled;
+ qcom,tunipip6-enabled;
+ qcom,vlan-enabled;
+ qcom,wlan-dataplane-offload-enabled;
+ qcom,wlanredirect-enabled;
+ qcom,pxvlan-enabled;
+ qcom,vxlan-enabled;
+ qcom,match-enabled;
+ qcom,mirror-enabled;
+ qcom,rmnet-enabled;
+ qcom,clmap-enabled;
+ };
+
+ nss1: nss@40800000 {
+ compatible = "qcom,nss";
+ qcom,low-frequency = <733000000>; /* orig value 110000000 */
+ qcom,mid-frequency = <733000000>; /* orig value 550000000 */
+ qcom,max-frequency = <733000000>;
+
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x36400000 0x1000 0x39010000 0x10000>;
+ reg-names = "nphys", "vphys";
+ resets = <&gcc UBI32_CORE2_CLKRST_CLAMP_RESET>,
+ <&gcc UBI32_CORE2_CLAMP_RESET>,
+ <&gcc UBI32_CORE2_AHB_RESET>,
+ <&gcc UBI32_CORE2_AXI_RESET>;
+ reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
+
+ qcom,id = <1>;
+ qcom,num-irq = <2>;
+ qcom,load-addr = <0x40800000>;
+ qcom,num-queue = <2>;
+ qcom,turbo-frequency;
+
+ qcom,capwap-enabled;
+ qcom,crypto-enabled;
+ qcom,dtls-enabled;
+ qcom,ipsec-enabled;
+ };
+
+ crypto1: crypto@38000000 {
+ compatible = "qcom,nss-crypto";
+ reg = <0x38000000 0x20000>, <0x38004000 0x22000>;
+ reg-names = "crypto_pbase", "bam_base";
+ clocks = <&gcc CE5_CORE_CLK>, <&gcc CE5_A_CLK>, <&gcc CE5_H_CLK>;
+ clock-names = "ce5_core", "ce5_aclk", "ce5_hclk";
+ resets = <&gcc CRYPTO_ENG1_RESET>, <&gcc CRYPTO_AHB_RESET>;
+ reset-names = "rst_eng", "rst_ahb";
+ qcom,id = <0>;
+ qcom,ee = <0>;
+ };
+
+ crypto2: crypto@38400000 {
+ compatible = "qcom,nss-crypto";
+ reg = <0x38400000 0x20000>, <0x38404000 0x22000>;
+ reg-names = "crypto_pbase", "bam_base";
+ resets = <&gcc CRYPTO_ENG2_RESET>;
+ reset-names = "rst_eng";
+ qcom,id = <1>;
+ qcom,ee = <0>;
+ };
+
+ crypto3: crypto@38800000 {
+ compatible = "qcom,nss-crypto";
+ reg = <0x38800000 0x20000>, <0x38804000 0x22000>;
+ reg-names = "crypto_pbase", "bam_base";
+ resets = <&gcc CRYPTO_ENG3_RESET>;
+ reset-names = "rst_eng";
+ qcom,id = <2>;
+ qcom,ee = <0>;
+ };
+
+ crypto4: crypto@38c00000 {
+ compatible = "qcom,nss-crypto";
+ reg = <0x38c00000 0x20000>, <0x38c04000 0x22000>;
+ reg-names = "crypto_pbase", "bam_base";
+ resets = <&gcc CRYPTO_ENG4_RESET>;
+ reset-names = "rst_eng";
+ qcom,id = <3>;
+ qcom,ee = <0>;
+ };
+
+
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
@@ -1462,6 +1602,12 @@
status = "disabled";
};
+ nss-gmac-common {
+ compatible = "qcom,nss-gmac-common";
+ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>;
+ reg-names = "nss_reg_base", "qsgmii_reg_base", "clk_ctl_base";
+ };
+
gmac0: ethernet@37000000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
@@ -1559,3 +1705,27 @@
};
};
};
+
+ &gmac1 {
+ compatible = "qcom,nss-gmac";
+ qcom,id = <0>;
+ qcom,pcs-chanid = <0>;
+ qcom,phy_mii_type = <0>;
+ qcom,emulation = <0>;
+ qcom,forced-speed = <1000>;
+ qcom,forced-duplex = <1>;
+ qcom,socver = <0>;
+ mdiobus = <&mdio0>;
+ };
+
+ &gmac2 {
+ compatible = "qcom,nss-gmac";
+ qcom,id = <1>;
+ qcom,pcs-chanid = <1>;
+ qcom,phy_mii_type = <1>;
+ qcom,emulation = <0>;
+ qcom,forced-speed = <1000>;
+ qcom,forced-duplex = <1>;
+ qcom,socver = <0>;
+ mdiobus = <&mdio0>;
+ };
--- a/arch/arm/boot/dts/qcom/qcom-ipq8065-nighthawk.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065-nighthawk.dtsi
@@ -360,13 +360,23 @@
&gmac1 {
status = "okay";
+ compatible = "qcom,nss-gmac";
+ reg = <0x37200000 0x200000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
+ qcom,pcs-chanid = <0>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <0>;
qcom,rgmii_delay = <1>;
+ qcom,phy-mdio-addr = <4>;
+ qcom,poll-required = <0>;
+ qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
+ qcom,forced-speed = <1000>;
+ qcom,forced-duplex = <1>;
+ qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
@@ -385,13 +395,23 @@
&gmac2 {
status = "okay";
+ compatible = "qcom,nss-gmac";
+ reg = <0x37400000 0x200000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
+ qcom,pcs-chanid = <1>;
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
+ qcom,phy-mdio-addr = <0>;
+ qcom,poll-required = <0>;
+ qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
+ qcom,forced-speed = <1000>;
+ qcom,forced-duplex = <1>;
+ qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
--- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
@@ -95,3 +95,15 @@
opp-level = <2>;
};
};
+
+ &nss0 {
+ qcom,low-frequency = <110000000>;
+ qcom,mid-frequency = <600000000>;
+ qcom,max-frequency = <800000000>;
+ };
+
+ &nss1 {
+ qcom,low-frequency = <110000000>;
+ qcom,mid-frequency = <600000000>;
+ qcom,max-frequency = <800000000>;
+ };
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