9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 7f7315db3d262298ab33d198d3f0b09cabfa7b6b Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 6 Aug 2024 17:55:48 +0200
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Subject: [PATCH] phy: airoha: adjust initialization delay in
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airoha_pcie_phy_init()
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Align phy-pcie initialization delay to the vendor sdk in
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airoha_pcie_phy_init routine and allow the hw to complete required
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configuration before proceeding
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/8af6f27857619f1e0dd227f08b8584ae8fb22fb2.1722959625.git.lorenzo@kernel.org
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/phy-airoha-pcie.c | 6 +++++-
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1 file changed, 5 insertions(+), 1 deletion(-)
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--- a/drivers/phy/phy-airoha-pcie.c
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+++ b/drivers/phy/phy-airoha-pcie.c
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@@ -18,6 +18,9 @@
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#define LEQ_LEN_CTRL_MAX_VAL 7
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#define FREQ_LOCK_MAX_ATTEMPT 10
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+/* PCIe-PHY initialization time in ms needed by the hw to complete */
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+#define PHY_HW_INIT_TIME_MS 30
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+
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enum airoha_pcie_port_gen {
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PCIE_PORT_GEN1 = 1,
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PCIE_PORT_GEN2,
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@@ -1181,7 +1184,8 @@ static int airoha_pcie_phy_init(struct p
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airoha_phy_pma1_set_bits(pcie_phy, REG_PCIE_PMA_SS_DA_XPON_PWDB0,
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PCIE_DA_XPON_CDR_PR_PWDB);
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- usleep_range(100, 200);
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+ /* Wait for the PCIe PHY to complete initialization before returning */
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+ msleep(PHY_HW_INIT_TIME_MS);
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return 0;
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}
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