98f73552a7
Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to PPL(PLL?)_RESET bit of AR724x. Refresh patches by `make target/linux/refresh`. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15432 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
68 lines
2.3 KiB
Diff
68 lines
2.3 KiB
Diff
From: Daniel Golle <daniel@makrotopia.org>
|
|
Subject: [PATCH] ath79: add support for Atheros AR934x HS UART
|
|
|
|
AR934x chips also got the 'old' qca,ar9330-uart in addition to the
|
|
'new' ns16550a compatible one. Add support for UART1 clock selector as
|
|
well as device-tree bindings in ar934x.dtsi to make use of that uart.
|
|
|
|
Reported-by: Piotr Dymacz <pepe2k@gmail.com>
|
|
Submitted-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
arch/mips/ath79/clock.c | 7 +++++++
|
|
.../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
|
|
include/dt-bindings/clock/ath79-clk.h | 3 ++-
|
|
3 files changed, 10 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/mips/ath79/clock.c
|
|
+++ b/arch/mips/ath79/clock.c
|
|
@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
|
|
[ATH79_CLK_AHB] = "ahb",
|
|
[ATH79_CLK_REF] = "ref",
|
|
[ATH79_CLK_MDIO] = "mdio",
|
|
+ [ATH79_CLK_UART1] = "uart1",
|
|
};
|
|
|
|
static const char * __init ath79_clk_name(int type)
|
|
@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
|
|
if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
|
|
ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
|
|
|
|
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
|
|
+ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
|
|
+
|
|
iounmap(dpll_base);
|
|
}
|
|
|
|
@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
|
|
if (!clks[ATH79_CLK_MDIO])
|
|
clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
|
|
|
|
+ if (!clks[ATH79_CLK_UART1])
|
|
+ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
|
|
+
|
|
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
|
|
pr_err("%pOF: could not register clk provider\n", np);
|
|
goto err_iounmap;
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -350,6 +350,7 @@
|
|
#define AR934X_PLL_PCIE_CONFIG_PLL_PWD BIT(30)
|
|
|
|
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
|
|
|
|
#define QCA953X_PLL_CPU_CONFIG_REG 0x00
|
|
#define QCA953X_PLL_DDR_CONFIG_REG 0x04
|
|
--- a/include/dt-bindings/clock/ath79-clk.h
|
|
+++ b/include/dt-bindings/clock/ath79-clk.h
|
|
@@ -11,7 +11,8 @@
|
|
#define ATH79_CLK_AHB 2
|
|
#define ATH79_CLK_REF 3
|
|
#define ATH79_CLK_MDIO 4
|
|
+#define ATH79_CLK_UART1 5
|
|
|
|
-#define ATH79_CLK_END 5
|
|
+#define ATH79_CLK_END 6
|
|
|
|
#endif /* __DT_BINDINGS_ATH79_CLK_H */
|