e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
68 lines
2.4 KiB
Diff
68 lines
2.4 KiB
Diff
From 1be9bd37fdb5f50162dba0158e1fee295ebca9aa Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Tue, 17 Oct 2023 17:22:52 +0800
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Subject: [PATCH 053/116] ASoC: dwc: i2s: Add RX master support for StarFive
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JH7110 SoC
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Add JH7110 I2S RX master support, so the PDM can work on JH7110
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EVB board.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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---
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sound/soc/dwc/dwc-i2s.c | 31 +++++++++++++++++++++++++++++++
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1 file changed, 31 insertions(+)
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--- a/sound/soc/dwc/dwc-i2s.c
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+++ b/sound/soc/dwc/dwc-i2s.c
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@@ -906,6 +906,27 @@ static int jh7110_i2srx_crg_init(struct
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return jh7110_i2s_crg_slave_init(dev);
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}
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+/* Special syscon initialization about RX channel with master mode on JH7110 SoC */
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+static int jh7110_i2srx_mst_crg_init(struct dw_i2s_dev *dev)
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+{
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+ struct regmap *regmap;
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+ unsigned int args[5];
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+
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+ regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,
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+ "starfive,syscon",
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+ 5, args);
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+ if (IS_ERR(regmap))
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+ return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n");
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+
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+ /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */
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+ regmap_update_bits(regmap, args[0], args[1], args[1]);
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+
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+ /* Change I2Srx source (PDM) with syscon register, args[0]: offset, args[1]: mask */
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+ regmap_update_bits(regmap, args[2], args[3], args[4]);
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+
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+ return jh7110_i2s_crg_master_init(dev);
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+}
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+
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static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config)
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{
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struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config);
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@@ -1086,11 +1107,21 @@ static const struct i2s_platform_data jh
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.i2s_pd_init = jh7110_i2srx_crg_init,
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};
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+static const struct i2s_platform_data jh7110_i2srx_mst_data = {
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+ .cap = DWC_I2S_RECORD | DW_I2S_MASTER,
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+ .channel = TWO_CHANNEL_SUPPORT,
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+ .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
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+ .snd_rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000,
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+ .i2s_clk_cfg = jh7110_i2stx0_clk_cfg,
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+ .i2s_pd_init = jh7110_i2srx_mst_crg_init,
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+};
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+
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static const struct of_device_id dw_i2s_of_match[] = {
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{ .compatible = "snps,designware-i2s", },
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{ .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, },
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{ .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,},
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{ .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,},
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+ { .compatible = "starfive,jh7110-i2srx-master", .data = &jh7110_i2srx_mst_data,},
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{},
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};
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