e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 30fb5963f4cf3b7d114a8212358147615480685c Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Thu, 30 Nov 2023 16:19:25 +0100
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Subject: [PATCH 1017/1024] riscv: errata: Add StarFive JH7100 errata
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This not really an errata, but since the JH7100 was made before
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the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
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RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
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Acked-by: Conor Dooley <conor.dooley@microchip.com>
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
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Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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arch/riscv/Kconfig.errata | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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--- a/arch/riscv/Kconfig.errata
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+++ b/arch/riscv/Kconfig.errata
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@@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200
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If you don't know what to do here, say "Y".
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+config ERRATA_STARFIVE_JH7100
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+ bool "StarFive JH7100 support"
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+ depends on ARCH_STARFIVE && NONPORTABLE
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+ select DMA_GLOBAL_POOL
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+ select RISCV_DMA_NONCOHERENT
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+ select RISCV_NONSTANDARD_CACHE_OPS
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+ select SIFIVE_CCACHE
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+ default n
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+ help
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+ The StarFive JH7100 was a test chip for the JH7110 and has
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+ caches that are non-coherent with respect to peripheral DMAs.
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+ It was designed before the Zicbom extension so needs non-standard
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+ cache operations through the SiFive cache controller.
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+
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+ Say "Y" if you want to support the BeagleV Starlight and/or
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+ StarFive VisionFive V1 boards.
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+
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config ERRATA_THEAD
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bool "T-HEAD errata"
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depends on RISCV_ALTERNATIVE
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