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domenico
2025-06-24 12:51:15 +02:00
commit 27c9d80f51
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61
package/boot/apex/Makefile Normal file
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# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2006-2023 OpenWrt.org
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=apex
# This version was created from the stalled and unreleased v1.6.10
# with some patches on top.
PKG_VERSION:=1.6.10-openwrt
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/linusw/apex.git
PKG_SOURCE_VERSION:=483e18aa133d5e25866570c29b124530b2d1e0d3
PKG_MIRROR_HASH:=75e0be55e779a6c1f582bf12f5f98ac175404be9172750c1c1015ad78aa8aa3d
PKG_TARGETS:=bin
PKG_FLAGS:=nonshared
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=COPYING
include $(INCLUDE_DIR)/package.mk
export GCC_HONOUR_COPTS=s
define Package/apex
SECTION:=boot
CATEGORY:=Boot Loaders
DEPENDS:=@TARGET_ixp4xx @!IN_SDK
DEFAULT:=y
TITLE:=Boot loader for NSLU2, FSG3, NAS100D and others
endef
define build_apex
$(MAKE) -C $(PKG_BUILD_DIR) \
ARCH=arm \
$(1)_config
$(MAKE) -C $(PKG_BUILD_DIR) \
$(TARGET_CONFIGURE_OPTS) \
KBUILD_HAVE_NLS=no \
ARCH=arm \
clean all
$(INSTALL_BIN) $(PKG_BUILD_DIR)/apex.bin $(PKG_BUILD_DIR)/out/apex-$(2).bin
endef
define Build/Compile
$(INSTALL_DIR) $(PKG_BUILD_DIR)/out
$(call build_apex,openwrt-nslu2-armeb,nslu2-armeb)
$(call build_apex,openwrt-nslu2-16mb-armeb,nslu2-16mb-armeb)
$(call build_apex,openwrt-fsg3-armeb,fsg3-armeb)
$(call build_apex,openwrt-nas100d-armeb,nas100d-armeb)
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/apex
$(CP) $(PKG_BUILD_DIR)/out/*.bin $(STAGING_DIR_IMAGE)/apex
endef
$(eval $(call BuildPackage,apex))

43
package/boot/arm-trusted-firmware-bcm63xx/Makefile Normal file
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# SPDX-License-Identifier: GPL-2.0
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.2
PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/bcm63xx/atf.git
PKG_SOURCE_DATE:=2021-12-24
PKG_SOURCE_VERSION:=e6d46baf3fae79f693f90bf34f7284c3dfc64aef
PKG_MIRROR_HASH:=5646abc01152210a8181455151f01145001d61b3fb09619b1cee48008e36b0fa
PKG_MAINTAINER:=Rafał Miłecki <rafal@milecki.pl>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
PLAT:=bcm
DEFAULT:=y
endef
define Trusted-Firmware-A/bcm4908
BUILD_TARGET:=bcm4908
NAME:=BCM4908
BRCM_CHIP=4908
TFA_IMAGE:=bl31.bin
endef
TFA_TARGETS:= \
bcm4908
TFA_MAKE_FLAGS += \
BRCM_CHIP=$(BRCM_CHIP)
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/$(TFA_IMAGE) $(STAGING_DIR_IMAGE)/
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

568
package/boot/arm-trusted-firmware-mediatek/Makefile Normal file
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#
# Copyright (C) 2017 Hauke Mehrtens
# Copyright (C) 2021-2023 Daniel Golle
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-mediatek
PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git
PKG_SOURCE_DATE:=2024-01-17
PKG_SOURCE_VERSION:=bacca82a8cac369470df052a9d801a0ceb9b74ca
PKG_MIRROR_HASH:=1138649f64ac3982330925c38c795ca6860289adbd95755991f80afa30ebdea7
PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
BUILD_TARGET:=mediatek
TFA_IMAGE:=bl2.img bl31.bin
HIDDEN:=y
BOOT_DEVICE:=
DDR3_FLYBY:=
DDR_TYPE:=
NAND_TYPE:=
BOARD_QFN:=
DRAM_USE_COMB:=
RAM_BOOT_UART_DL:=
USE_UBI:=
endef
define Trusted-Firmware-A/mt7622-nor-1ddr
NAME:=MediaTek MT7622 (SPI-NOR, 1x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=nor
endef
define Trusted-Firmware-A/mt7622-nor-2ddr
NAME:=MediaTek MT7622 (SPI-NOR, 2x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=nor
DDR3_FLYBY:=1
endef
define Trusted-Firmware-A/mt7622-snand-1ddr
NAME:=MediaTek MT7622 (SPI-NAND, 1x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=snand
endef
define Trusted-Firmware-A/mt7622-snand-ubi-1ddr
NAME:=MediaTek MT7622 (SPI-NAND using UBI, 1x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=snand
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7622-snand-2ddr
NAME:=MediaTek MT7622 (SPI-NAND, 2x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=snand
DDR3_FLYBY:=1
endef
define Trusted-Firmware-A/mt7622-snand-ubi-2ddr
NAME:=MediaTek MT7622 (SPI-NAND using UBI, 2x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=snand
DDR3_FLYBY:=1
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7622-emmc-1ddr
NAME:=MediaTek MT7622 (eMMC, 1x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=emmc
endef
define Trusted-Firmware-A/mt7622-emmc-2ddr
NAME:=MediaTek MT7622 (eMMC, 2x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=emmc
DDR3_FLYBY:=1
endef
define Trusted-Firmware-A/mt7622-sdmmc-1ddr
NAME:=MediaTek MT7622 (SD card, 1x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=sdmmc
endef
define Trusted-Firmware-A/mt7622-sdmmc-2ddr
NAME:=MediaTek MT7622 (SD card, 2x DDR3)
BUILD_SUBTARGET:=mt7622
PLAT:=mt7622
BOOT_DEVICE:=sdmmc
DDR3_FLYBY:=1
endef
define Trusted-Firmware-A/mt7981-ram-ddr4
NAME:=MediaTek MT7981 (RAM, DDR4)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr4
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7981-emmc-ddr4
NAME:=MediaTek MT7981 (eMMC, DDR4)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7981-spim-nand-ddr4
NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7981-nor-ddr3
NAME:=MediaTek MT7981 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7981-ram-ddr3
NAME:=MediaTek MT7981 (RAM, DDR3)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7981-nor-ddr4
NAME:=MediaTek MT7981 (SPI-NOR, DDR4)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7981-emmc-ddr3
NAME:=MediaTek MT7981 (eMMC, DDR3)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7981-sdmmc-ddr3
NAME:=MediaTek MT7981 (SD card, DDR3)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7981-snand-ddr3
NAME:=MediaTek MT7981 (SPI-NAND via SNFI, DDR3)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7981-spim-nand-ddr3
NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR3)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7986-ram-ddr4
NAME:=MediaTek MT7986 (RAM, DDR4)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7981-spim-nand-ubi-ddr4
NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7981
DDR_TYPE:=ddr4
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7986-nor-ddr4
NAME:=MediaTek MT7986 (SPI-NOR, DDR4)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7986-emmc-ddr4
NAME:=MediaTek MT7986 (eMMC, DDR4)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7986-sdmmc-ddr4
NAME:=MediaTek MT7986 (SD card, DDR4)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7986-snand-ddr4
NAME:=MediaTek MT7986 (SPI-NAND via SNFI, DDR4)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7986-spim-nand-ddr4
NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
NAND_TYPE:=spim:2k+64
endef
define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr4
NAME:=MediaTek MT7986 (SPI-NAND via SPIM using UBI, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
NAND_TYPE:=spim:2k+64
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4
NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr4
NAND_TYPE:=spim:4k+256
endef
define Trusted-Firmware-A/mt7986-ram-ddr3
NAME:=MediaTek MT7986 (RAM, DDR3)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7986-nor-ddr3
NAME:=MediaTek MT7986 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7986-emmc-ddr3
NAME:=MediaTek MT7986 (eMMC, DDR3)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7986-sdmmc-ddr3
NAME:=MediaTek MT7986 (SD card, DDR3)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7986-snand-ddr3
NAME:=MediaTek MT7986 (SPI-NAND via SNFI, DDR3)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7986-spim-nand-ddr3
NAME:=MediaTek MT7986 (SPI-NAND via SPIM, DDR3)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7986
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-nor-ddr3
NAME:=MediaTek MT7988 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-emmc-ddr3
NAME:=MediaTek MT7988 (eMMC, DDR3)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-sdmmc-ddr3
NAME:=MediaTek MT7988 (SD card, DDR3)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-snand-ddr3
NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR3)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-spim-nand-ddr3
NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR3)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr3
endef
define Trusted-Firmware-A/mt7988-nor-ddr4
NAME:=MediaTek MT7988 (SPI-NOR, DDR4)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7988-emmc-ddr4
NAME:=MediaTek MT7988 (eMMC, DDR4)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7988-sdmmc-ddr4
NAME:=MediaTek MT7988 (SD card, DDR4)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7988-snand-ddr4
NAME:=MediaTek MT7988 (SPI-NAND via SNFI, DDR4)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7988-spim-nand-ddr4
NAME:=MediaTek MT7988 (SPI-NAND via SPIM, DDR4)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DDR_TYPE:=ddr4
endef
define Trusted-Firmware-A/mt7988-ram-comb
NAME:=MediaTek MT7988 (RAM)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7988-nor-comb
NAME:=MediaTek MT7988 (SPI-NOR)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7988-emmc-comb
NAME:=MediaTek MT7988 (eMMC)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7988-sdmmc-comb
NAME:=MediaTek MT7988 (SD card)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7988-snand-comb
NAME:=MediaTek MT7988 (SPI-NAND via SNFI)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7988-snand-ubi-comb
NAME:=MediaTek MT7988 (SPI-NAND via SNFI, UBI)
BOOT_DEVICE:=snand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7988-spim-nand-comb
NAME:=MediaTek MT7988 (SPI-NAND via SPIM)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7988-spim-nand-ubi-comb
NAME:=MediaTek MT7988 (SPI-NAND via SPIM, UBI)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7988
DRAM_USE_COMB:=1
USE_UBI:=1
endef
TFA_TARGETS:= \
mt7622-nor-1ddr \
mt7622-nor-2ddr \
mt7622-snand-1ddr \
mt7622-snand-ubi-1ddr \
mt7622-snand-2ddr \
mt7622-snand-ubi-2ddr \
mt7622-emmc-1ddr \
mt7622-emmc-2ddr \
mt7622-sdmmc-1ddr \
mt7622-sdmmc-2ddr \
mt7981-ram-ddr3 \
mt7981-emmc-ddr3 \
mt7981-nor-ddr3 \
mt7981-nor-ddr4 \
mt7981-sdmmc-ddr3 \
mt7981-snand-ddr3 \
mt7981-spim-nand-ddr3 \
mt7981-spim-nand-ubi-ddr4 \
mt7981-ram-ddr4 \
mt7981-emmc-ddr4 \
mt7981-spim-nand-ddr4 \
mt7986-ram-ddr3 \
mt7986-emmc-ddr3 \
mt7986-nor-ddr3 \
mt7986-sdmmc-ddr3 \
mt7986-snand-ddr3 \
mt7986-spim-nand-ddr3 \
mt7986-ram-ddr4 \
mt7986-emmc-ddr4 \
mt7986-nor-ddr4 \
mt7986-sdmmc-ddr4 \
mt7986-snand-ddr4 \
mt7986-spim-nand-ddr4 \
mt7986-spim-nand-ubi-ddr4 \
mt7986-spim-nand-4k-ddr4 \
mt7988-emmc-ddr3 \
mt7988-nor-ddr3 \
mt7988-sdmmc-ddr3 \
mt7988-snand-ddr3 \
mt7988-spim-nand-ddr3 \
mt7988-emmc-ddr4 \
mt7988-nor-ddr4 \
mt7988-sdmmc-ddr4 \
mt7988-snand-ddr4 \
mt7988-spim-nand-ddr4 \
mt7988-ram-comb \
mt7988-emmc-comb \
mt7988-nor-comb \
mt7988-sdmmc-comb \
mt7988-snand-comb \
mt7988-snand-ubi-comb \
mt7988-spim-nand-comb \
mt7988-spim-nand-ubi-comb
TFA_MAKE_FLAGS += \
BOOT_DEVICE=$(BOOT_DEVICE) \
USE_MKIMAGE=1 MKIMAGE=$(STAGING_DIR_HOST)/bin/mkimage \
$(if $(findstring ddr4,$(DDR_TYPE)),DRAM_USE_DDR4=1) \
$(if $(BOARD_QFN),BOARD_QFN=1,BOARD_BGA=1) \
$(if $(NAND_TYPE),NAND_TYPE=$(NAND_TYPE)) \
HAVE_DRAM_OBJ_FILE=yes \
$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
$(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7981,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x100000)) \
all
define Package/trusted-firmware-a-ram/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.bin $(BIN_DIR)/$(BUILD_VARIANT)-bl2.bin
endef
Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7986-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7988-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl2.img
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl31.bin
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

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package/boot/arm-trusted-firmware-mediatek/patches/0001-mediatek-snfi-FM35Q1GA-is-x4-only.patch Normal file
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From fb2a2b669ec9bbf5c448d4b56499bc83de075c93 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 29 Feb 2024 18:01:08 +0000
Subject: [PATCH 1/3] mediatek: snfi: FM35Q1GA is x4-only
Dont allow x2 read and cache read operations on FM35Q1GA.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
@@ -423,7 +423,7 @@ static const struct snand_flash_info sna
SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
SNAND_MEMORG_1G_2K_64,
- &snand_cap_read_from_cache_x4,
+ &snand_cap_read_from_cache_x4_only,
&snand_cap_program_load_x4),
SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),

99
package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-snfi-adjust-pin-drive-strength-for-Fidelix-.patch Normal file
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@@ -0,0 +1,99 @@
From 6470986f037880ce76960c369d6e5a5270e7ce32 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sun, 10 Mar 2024 15:39:07 +0000
Subject: [PATCH 2/3] mediatek: snfi: adjust pin drive strength for Fidelix
SPI-NAND
It seems like we might need to adjust the pin driver strength to 12mA
for Fidelix SPI-NAND chip on MT7622 to avoid SPI data corruption on
some devices.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
.../apsoc_common/drivers/snfi/mtk-snand-def.h | 7 +++++
.../apsoc_common/drivers/snfi/mtk-snand-ids.c | 4 ++-
.../apsoc_common/drivers/snfi/mtk-snand.c | 30 +++++++++++++++++++
3 files changed, 40 insertions(+), 1 deletion(-)
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
@@ -86,6 +86,12 @@ struct snand_mem_org {
typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
+enum snand_drv {
+ SNAND_DRV_NO_CHANGE = 0,
+ SNAND_DRV_8mA = 8,
+ SNAND_DRV_12mA = 12,
+};
+
struct snand_flash_info {
const char *model;
struct snand_id id;
@@ -93,6 +99,7 @@ struct snand_flash_info {
const struct snand_io_cap *cap_rd;
const struct snand_io_cap *cap_pl;
snand_select_die_t select_die;
+ enum snand_drv drv;
};
#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
@@ -424,7 +424,9 @@ static const struct snand_flash_info sna
SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_x4_only,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
SNAND_MEMORG_1G_2K_128,
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk
return -EINVAL;
}
+#define MT7622_GPIO_BASE (void *)0x10211000
+#define MT7622_GPIO_DRIV(x) (MT7622_GPIO_BASE + 0x900 + 0x10 * x)
+
+void mtk_mt7622_snand_adjust_drive(void *dev, enum snand_drv drv)
+{
+ uint32_t e4, e8;
+
+ e4 = readl(MT7622_GPIO_DRIV(6)) & ~(0x3f00);
+ e8 = readl(MT7622_GPIO_DRIV(7)) & ~(0x3f00);
+
+ switch (drv) {
+ case SNAND_DRV_8mA:
+ e4 |= 0x3f00;
+ break;
+ case SNAND_DRV_12mA:
+ e8 |= 0x3f00;
+ break;
+ default:
+ return;
+ }
+
+ snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
+
+ writel(e4, MT7622_GPIO_DRIV(6));
+ writel(e8, MT7622_GPIO_DRIV(7));
+}
+
int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
struct mtk_snand **psnf)
{
@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const stru
if (ret)
return ret;
+ if (pdata->soc == SNAND_SOC_MT7622 && snand_info->drv)
+ mtk_mt7622_snand_adjust_drive(dev, snand_info->drv);
+
rawpage_size = snand_info->memorg.pagesize +
snand_info->memorg.sparesize;

135
package/boot/arm-trusted-firmware-mediatek/patches/0003-mediatek-snfi-adjust-drive-strength-to-12mA-like-old.patch Normal file
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@@ -0,0 +1,135 @@
From 40a3661bebb3d738ab95b7de66e9d8382d5b9ab1 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sun, 10 Mar 2024 17:48:09 +0000
Subject: [PATCH 3/3] mediatek: snfi: adjust drive strength to 12mA like old
loader does
In addition to FM35X1GA, also change the driver strength to 12mA for
all chips where this is done by the old/legacy U-Boot:
* Winbond 512Mb
* Winbond 1Gb
* Winbond 2Gb
* GD5F4GQ4UBYIG
* GD5F4GQ4UAYIG
* GD5F1GQ4UX
* GD5F1GQ4UE
* GD5F2GQ4UX
* GD5F2GQ4UE
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
.../apsoc_common/drivers/snfi/mtk-snand-ids.c | 59 ++++++++++++++-----
1 file changed, 44 insertions(+), 15 deletions(-)
--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
@@ -80,65 +80,94 @@ static const struct snand_flash_info sna
SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
SNAND_MEMORG_512M_2K_64,
&snand_cap_read_from_cache_quad,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
SNAND_MEMORG_2G_2K_64_2D,
&snand_cap_read_from_cache_quad,
&snand_cap_program_load_x4,
- mtk_snand_winbond_select_die),
+ mtk_snand_winbond_select_die,
+ SNAND_DRV_12mA),
SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
SNAND_MEMORG_1G_2K_128,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
SNAND_MEMORG_1G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
SNAND_MEMORG_2G_2K_64,
&snand_cap_read_from_cache_quad_a8d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
SNAND_MEMORG_2G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
SNAND_MEMORG_4G_4K_256,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
SNAND_MEMORG_4G_2K_64,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
SNAND_MEMORG_2G_2K_128,
&snand_cap_read_from_cache_quad_a8d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
SNAND_MEMORG_4G_4K_256,
&snand_cap_read_from_cache_quad_q2d,
- &snand_cap_program_load_x4),
+ &snand_cap_program_load_x4,
+ NULL,
+ SNAND_DRV_12mA),
SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
SNAND_MEMORG_1G_2K_64,

247
package/boot/arm-trusted-firmware-mvebu/Makefile Normal file
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@@ -0,0 +1,247 @@
#
# Copyright (C) 2019 Sartura Ltd.
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.9
PKG_RELEASE:=2
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
BUILD_TARGET:=mvebu
BUILD_SUBTARGET:=cortexa53
TFA_IMAGE:=flash-image.bin uart-images.tgz.bin
UBOOT:=
DDR_TOPOLOGY:=
CLOCKSPRESET:=
endef
define Trusted-Firmware-A/espressobin-512mb
NAME:=Marvell ESPRESSObin (512MB)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin
UBOOT:=espressobin
DDR_TOPOLOGY:=0
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/espressobin-v3-v5-1gb-1cs
NAME:=Marvell ESPRESSObin V3-V5 (1GB 1CS)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin
UBOOT:=espressobin
DDR_TOPOLOGY:=4
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/espressobin-v3-v5-1gb-2cs
NAME:=Marvell ESPRESSObin V3-V5 (1GB, 2CS)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin
UBOOT:=espressobin
DDR_TOPOLOGY:=2
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/espressobin-v3-v5-2gb
NAME:=Marvell ESPRESSObin V3-V5 (2GB)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin
UBOOT:=espressobin
DDR_TOPOLOGY:=7
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/espressobin-v7-1gb
NAME:=Marvell ESPRESSObin V7 (1GB)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin-v7
UBOOT:=espressobin
DDR_TOPOLOGY:=5
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/espressobin-v7-2gb
NAME:=Marvell ESPRESSObin V7 (2GB)
DEPENDS:=+u-boot-espressobin
BUILD_DEVICES:=globalscale_espressobin-v7
UBOOT:=espressobin
DDR_TOPOLOGY:=6
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/udpu
NAME:=Methode uDPU
DEPENDS:=+u-boot-uDPU
BUILD_DEVICES:=methode_udpu
UBOOT:=uDPU
DDR_TOPOLOGY:=0
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
define Trusted-Firmware-A/edpu
NAME:=Methode eDPU
DEPENDS:=+u-boot-eDPU
BUILD_DEVICES:=methode_edpu
UBOOT:=eDPU
DDR_TOPOLOGY:=0
CLOCKSPRESET:=CPU_1000_DDR_800
PLAT:=a3700
endef
TFA_TARGETS:= \
espressobin-512mb \
espressobin-v3-v5-1gb-1cs \
espressobin-v3-v5-1gb-2cs \
espressobin-v3-v5-2gb \
espressobin-v7-1gb \
espressobin-v7-2gb \
udpu \
edpu
TFA_MAKE_FLAGS += \
CROSS_CM3=$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \
BL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \
MV_DDR_PATH=$(BUILD_DIR)/$(MV_DDR_NAME) \
WTP=$(BUILD_DIR)/$(A3700_UTILS_NAME) \
WTMI_IMG=$(BUILD_DIR)/$(MOX_BB_NAME)/wtmi_app.bin \
CRYPTOPP_PATH=$(BUILD_DIR)/$(CRYPTOPP_NAME) \
HOST_LDFLAGS="$(HOST_LDFLAGS)" \
HOST_CPPFLAGS="$(HOST_CPPFLAGS)" \
USE_COHERENT_MEM=0 \
FIP_ALIGN=0x100 \
DDR_TOPOLOGY=$(DDR_TOPOLOGY) \
CLOCKSPRESET=$(CLOCKSPRESET) \
A3700_UTILS_COMMIT_ID=$(A3700_UTILS_RELEASE) \
MV_DDR_COMMIT_ID=$(MV_DDR_RELEASE) \
all \
mrvl_flash \
mrvl_uart
A3700_UTILS_NAME:=a3700-utils
A3700_UTILS_RELEASE:=a3e1c67
A3700_UTILS_SOURCE=$(A3700_UTILS_NAME)-$(A3700_UTILS_RELEASE).tar.bz2
define Download/a3700-utils
FILE:=$(A3700_UTILS_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
SOURCE_VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
MIRROR_HASH:=0e6b8ef6423dcb52a5e282669a8aeebc6eea2d45a7c3a2c9a2fc7a749b3275a7
SUBDIR:=$(A3700_UTILS_NAME)
endef
CRYPTOPP_NAME:=cryptopp
CRYPTOPP_RELEASE:=4d0cad5
CRYPTOPP_SOURCE=$(CRYPTOPP_NAME)-$(CRYPTOPP_RELEASE).tar.bz2
define Download/cryptopp
FILE:=$(CRYPTOPP_SOURCE)
PROTO:=git
URL:=https://github.com/weidai11/cryptopp.git
SOURCE_VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
MIRROR_HASH:=6c53c8b4dfa07df0c5915a90c20f70c64d150b652cf5ac52e2eae08c5a9cc7cd
SUBDIR:=$(CRYPTOPP_NAME)
endef
MV_DDR_NAME:=mv-ddr-marvell
MV_DDR_RELEASE:=541616b
MV_DDR_SOURCE:=$(MV_DDR_NAME)-$(MV_DDR_RELEASE).tar.bz2
define Download/mv-ddr-marvell
FILE:=$(MV_DDR_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
SOURCE_VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
MIRROR_HASH:=9e86a986c7400ed1a72165a88150b6c494ebd87303b16314b43e5785e3f13068
SUBDIR:=$(MV_DDR_NAME)
endef
MOX_BB_NAME:=mox-boot-builder
MOX_BB_RELEASE:=604f8f51
MOX_BB_SOURCE:=$(MOX_BB_NAME)-$(MOX_BB_RELEASE).tar.bz2
define Download/mox-boot-builder
FILE:=$(MOX_BB_SOURCE)
PROTO:=git
SUBMODULES:=skip
URL:=https://gitlab.nic.cz/turris/mox-boot-builder.git
SOURCE_VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
MIRROR_HASH:=b09337a7dde140f57e40133b6e7b7e1eb338e7cea9b15a3af6874824462f15f7
SUBDIR:=$(MOX_BB_NAME)
endef
CM3_GCC_NAME:=arm-gnu-toolchain
CM3_GCC_RELEASE:=12.3.rel1
CM3_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi
CM3_GCC_SOURCE=$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION).tar.xz
define Download/cm3-gcc
FILE:=$(CM3_GCC_SOURCE)
URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(CM3_GCC_RELEASE)/binrel
ifeq ($(HOST_ARCH),aarch64)
HASH:=14c0487d5753f6071d24e568881f7c7e67f80dd83165dec5164b3731394af431
else
HASH:=12a2815644318ebcceaf84beabb665d0924b6e79e21048452c5331a56332b309
endif
endef
define Build/Clean
rm -rf \
$(BUILD_DIR)/$(CRYPTOPP_NAME) \
$(BUILD_DIR)/$(A3700_UTILS_NAME) \
$(BUILD_DIR)/$(MV_DDR_NAME) \
$(BUILD_DIR)/$(MOX_BB_NAME) \
$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)
endef
define Build/Prepare
# Download sources
$(eval $(call Download,a3700-utils))
$(eval $(call Download,mv-ddr-marvell))
$(eval $(call Download,mox-boot-builder))
$(eval $(call Download,cryptopp))
$(eval $(call Download,cm3-gcc))
$(call Build/Prepare/Default,)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(CRYPTOPP_SOURCE)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(A3700_UTILS_SOURCE)
$(call PatchDir/Default,$(BUILD_DIR)/$(A3700_UTILS_NAME),./patches-a3700-utils)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(MV_DDR_SOURCE)
$(call PatchDir/Default,$(BUILD_DIR)/$(MV_DDR_NAME),./patches-mv-ddr-marvell)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(MOX_BB_SOURCE)
$(call PatchDir/Default,$(BUILD_DIR)/$(MOX_BB_NAME),./patches-mox-boot-builder)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(CM3_GCC_SOURCE)
endef
define Build/Compile
+$(MAKE) \
CROSS_CM3=$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \
WTMI_VERSION=$(MOX_BB_RELEASE) \
CRYPTOPP_PATH=$PWD/cryptopp/ \
-C $(BUILD_DIR)/$(MOX_BB_NAME) \
wtmi_app.bin
$(call Build/Compile/Default)
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

14
package/boot/arm-trusted-firmware-mvebu/patches-a3700-utils/001-version.patch Normal file
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@@ -0,0 +1,14 @@
diff --git a/wtmi/sys_init/Makefile b/wtmi/sys_init/Makefile
--- a/wtmi/sys_init/Makefile
+++ b/wtmi/sys_init/Makefile
@@ -51,8 +51,8 @@ ECHO = @echo
SED = @sed
LOCAL_VERSION_STRING ?= -armada
-BUILD_STRING := $(shell git log -n 1 --pretty=format:"%h" && (git diff-index --quiet HEAD || echo -dirty))
-VERSION_STRING := $(LOCAL_VERSION_STRING)-$(BUILD_STRING)
+A3700_UTILS_COMMIT_ID ?= $(shell git log -n 1 --pretty=format:"%h" && (git diff-index --quiet HEAD || echo -dirty))
+VERSION_STRING := $(LOCAL_VERSION_STRING)-$(A3700_UTILS_COMMIT_ID)
CPUOPTS = -mthumb -mcpu=cortex-m3 -mlittle-endian
BINPATH = build

12
package/boot/arm-trusted-firmware-mvebu/patches-a3700-utils/002-version_mv_ddr_fix.patch Normal file
View File

@@ -0,0 +1,12 @@
--- a/Makefile
+++ b/Makefile
@@ -28,7 +28,7 @@
@cp -f ${MV_DDR_PATH}/a3700_tool $(TIM_DDR_PATH)/ddr_tool
$(TIM_DDR_PATH)/ddr_tool.verstr: $(MV_DDR_PATH)/a3700_tool
- @echo mv_ddr-$(shell sed 's/^mv_ddr-//' $(MV_DDR_PATH)/localversion 2>/dev/null || echo 'unknown')$(if $(shell git -C $(MV_DDR_PATH) rev-parse --git-dir 2>/dev/null),-g$(shell git -C $(MV_DDR_PATH) rev-parse --verify --quiet --short HEAD 2>/dev/null)$(shell git -C $(MV_DDR_PATH) diff-index --quiet HEAD || echo -d)) > $@
+ @echo mv_ddr-$(shell sed 's/^mv_ddr-//' $(MV_DDR_PATH)/localversion 2>/dev/null || echo 'unknown')-g$(MV_DDR_COMMIT_ID) > $@
mv_ddr: $(TIM_DDR_PATH)/ddr_tool $(TIM_DDR_PATH)/ddr_tool.verstr

12
package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/001-version.patch Normal file
View File

@@ -0,0 +1,12 @@
diff --git a/wtmi/Makefile b/wtmi/Makefile
index 75754dc..3602ec3 100644
--- a/wtmi/Makefile
+++ b/wtmi/Makefile
@@ -41,7 +41,6 @@ else
LTO_FLAGS =
endif
-override WTMI_VERSION = $(shell git describe --always --dirty --tags)
ifndef WTMI_VERSION
$(error Repository is without git tags, please do a full git clone again)
endif

12
package/boot/arm-trusted-firmware-mvebu/patches-mv-ddr-marvell/001-version.patch Normal file
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@@ -0,0 +1,12 @@
diff --git a/scripts/localversion.sh b/scripts/localversion.sh
--- a/scripts/localversion.sh
+++ b/scripts/localversion.sh
@@ -103,7 +103,7 @@ MV_DDR_ROOT=$1
MV_DDR_VER_CSRC=$2
# get mv_ddr git commit id
-MV_DDR_COMMIT_ID=`git -C $MV_DDR_ROOT rev-parse --verify --quiet --short HEAD 2> /dev/null`
+test -z "$MV_DDR_COMMIT_ID" && MV_DDR_COMMIT_ID=`git -C $MV_DDR_ROOT rev-parse --verify --quiet --short HEAD 2> /dev/null`
# check for uncommitted changes in mv_ddr git
MV_DDR_DIRTY_CHK=`git -C $MV_DDR_ROOT diff-index --name-only HEAD 2> /dev/null`

21
package/boot/arm-trusted-firmware-mvebu/patches/001-no-git.patch Normal file
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@@ -0,0 +1,21 @@
We're not building with full fledged git checkouts here, get rid of the
overzealous checks.
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -78,7 +78,6 @@ ifdef WTP
# Do not remove! Following checks are required to ensure correct TF-A builds, removing these checks leads to broken TF-A builds
$(if $(wildcard $(value WTP)/*),,$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' directory does not exist"))
-$(if $(shell git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid A3700-utils-marvell git repository"))
TBB := $(WTP)/wtptp/src/TBB_Linux/release/TBB_linux
@@ -164,7 +163,6 @@ $(TIMDDRTOOL): FORCE
# Do not remove! Following checks are required to ensure correct TF-A builds, removing these checks leads to broken TF-A builds
$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
- $(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
$(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL)

13
package/boot/arm-trusted-firmware-mvebu/patches/002-cryptopp_ldflags.patch Normal file
View File

@@ -0,0 +1,13 @@
Forward the host compiler flags to the compilation of the cryptopp library.
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -149,7 +149,7 @@ $(TBB): FORCE
$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
$(if $(wildcard $(CRYPTOPP_INCDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_INCDIR' was set to '$(CRYPTOPP_INCDIR)', but '$(CRYPTOPP_INCDIR)' does not exist"))
ifdef CRYPTOPP_PATH
- $(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
+ $(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile LDFLAGS="$(HOST_LDFLAGS)" CPPFLAGS="$(HOST_CPPFLAGS)"
endif
$(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)

72
package/boot/arm-trusted-firmware-rockchip/Makefile Normal file
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@@ -0,0 +1,72 @@
#
# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.10
PKG_RELEASE:=1
PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
NAME:=Rockchip $(1) SoCs
BUILD_TARGET:=rockchip
endef
define Trusted-Firmware-A/rk3328
BUILD_SUBTARGET:=armv8
PLAT=rk3328
endef
define Trusted-Firmware-A/rk3399
BUILD_SUBTARGET:=armv8
PLAT:=rk3399
endef
TFA_TARGETS:= \
rk3328 \
rk3399
ifeq ($(BUILD_VARIANT),rk3399)
M0_GCC_NAME:=gcc-arm
M0_GCC_RELEASE:=11.2-2022.02
M0_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi
M0_GCC_SOURCE:=$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION).tar.xz
define Download/m0-gcc
FILE:=$(M0_GCC_SOURCE)
URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(M0_GCC_RELEASE)/binrel
ifeq ($(HOST_ARCH),aarch64)
HASH:=ef1d82e5894e3908cb7ed49c5485b5b95deefa32872f79c2b5f6f5447cabf55f
else
HASH:=8c5acd5ae567c0100245b0556941c237369f210bceb196edfe5a2e7532c60326
endif
endef
define Build/Prepare
$(eval $(call Download,m0-gcc))
$(call Build/Prepare/Default)
xzcat $(DL_DIR)/$(M0_GCC_SOURCE) | $(HOST_TAR) -C $(PKG_BUILD_DIR)/ $(TAR_OPTIONS)
endef
TFA_MAKE_FLAGS+= \
M0_CROSS_COMPILE=$(PKG_BUILD_DIR)/$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION)/bin/arm-none-eabi-
endif
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31/bl31.elf $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)_bl31.elf
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

54
package/boot/arm-trusted-firmware-sunxi/Makefile Normal file
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@@ -0,0 +1,54 @@
#
# Copyright (C) 2017 Hauke Mehrtens
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.10
PKG_RELEASE:=1
PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=license.md
PKG_MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
BUILD_TARGET:=sunxi
BUILD_SUBTARGET:=cortexa53
endef
define Trusted-Firmware-A/sunxi-a64
NAME:=Allwinner A64
PLAT:=sun50i_a64
endef
define Trusted-Firmware-A/sunxi-h6
NAME:=Allwinner H6
PLAT:=sun50i_h6
endef
define Trusted-Firmware-A/sunxi-h616
NAME:=Allwinner H616
PLAT:=sun50i_h616
endef
TFA_TARGETS:= \
sunxi-a64 \
sunxi-h6 \
sunxi-h616
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31_$(BUILD_VARIANT).bin
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

51
package/boot/arm-trusted-firmware-tools/Makefile Normal file
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@@ -0,0 +1,51 @@
#
# Copyright 2021 Daniel Golle
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=arm-trusted-firmware-tools
PKG_VERSION:=2.9
PKG_RELEASE:=1
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
PKG_HOST_ONLY:=1
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/trusted-firmware-a-$(PKG_VERSION)
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/host-build.mk
define Package/arm-trusted-firmware-tools
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:=ARM Trusted Firmware tools
URL:=https://www.trustedfirmware.org
BUILDONLY:=1
endef
define Host/Compile
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/fiptool \
CPPFLAGS="$(HOST_CFLAGS)" \
LDFLAGS="$(HOST_LDFLAGS)"
endef
define Host/Install
$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin/
$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/
$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sptool.py $(STAGING_DIR_HOST)/bin/
endef
define Host/Clean
rm -f $(STAGING_DIR_HOST)/bin/fiptool
rm -f $(STAGING_DIR_HOST)/bin/sptool.py $(STAGING_DIR_HOST)/bin/sptool
endef
$(eval $(call BuildPackage,arm-trusted-firmware-tools))
$(eval $(call HostBuild))

11
package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch Normal file
View File

@@ -0,0 +1,11 @@
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -38,7 +38,7 @@
${PROJECT}: ${OBJECTS} Makefile
@echo " HOSTLD $@"
- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}
+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}

21
package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch Normal file
View File

@@ -0,0 +1,21 @@
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-
+#define _DARWIN_C_SOURCE
#ifndef _MSC_VER
#include <sys/mount.h>
#endif
@@ -18,6 +18,9 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <unistd.h>
+
+#define uuid_t fiptool_uuid_t
#include "fiptool.h"
#include "tbbr_config.h"

204
package/boot/at91bootstrap/Makefile Normal file
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@@ -0,0 +1,204 @@
#
# Copyright (C) 2016 Microchip Technology Inc.
# <Sandeepsheriker.mallikarjun@microchip.com>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=at91bootstrap
PKG_VERSION:=v4.0.3
PKG_MIRROR_HASH:=9c1d42337294b549e6c229ae4c9996efd21e00ae5f968bd780d352e054e24cb7
PKG_SOURCE_VERSION:=1d9e673698d9db4a4f2301559f481274de2e75ae
BINARIES_DIR:=build/binaries
PKG_CPE_ID:=cpe:/a:linux4sam:at91bootstrap
AT91BOOTSTRAP_V4=y
ifdef CONFIG_PACKAGE_at91bootstrap-sama5d4_xplaineddf_uboot_secure
AT91BOOTSTRAP_V4=n
else ifdef CONFIG_TARGET_at91_sam9x
ifndef CONFIG_TARGET_at91_sam9x_DEVICE_microchip_sam9x60ek
AT91BOOTSTRAP_V4=n
endif
endif
ifeq ($(AT91BOOTSTRAP_V4),n)
PKG_VERSION=v3.10.4
PKG_MIRROR_HASH:=08ab81c37b995592992d6eda3f76ce9aad6e2b3e9d9c4f7e88c1ba8bb8346657
PKG_SOURCE_VERSION=404846dd283894367a015ca59189bcf927d92e11
BINARIES_DIR=binaries
endif
PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/linux4sam/at91bootstrap.git
PKG_BUILD_DIR = \
$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
include at91bootstrap.mk
include $(INCLUDE_DIR)/package.mk
define AT91Bootstrap/Default
BUILD_TARGET:=at91
HIDDEN:=1
AT91BOOTSTRAP_IMAGE:=at91bootstrap.bin
endef
define AT91Bootstrap/at91sam9x5eknf_uboot
NAME:=AT91Bootstrap for AT91SAM9X5-EK board (NandFlash)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=atmel_at91sam9x25ek atmel_at91sam9x35ek
endef
define AT91Bootstrap/at91sam9x5eksd_uboot
NAME:=AT91Bootstrap for AT91SAM9X5-EK board (SDcard)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=atmel_at91sam9x25ek atmel_at91sam9x35ek
endef
define AT91Bootstrap/sam9x60eknf_uboot
NAME:=AT91Bootstrap for SAM9X60-EK board (NandFlash)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=microchip_sam9x60ek
endef
define AT91Bootstrap/sam9x60eksd_uboot
NAME:=AT91Bootstrap for SAM9X60-EK board (SDcard)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=microchip_sam9x60ek
endef
define AT91Bootstrap/sama5d2_icpdf_qspi_uboot
TITLE:=AT91Bootstrap for SAMA5D2 ICP board (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-icp
endef
define AT91Bootstrap/sama5d2_icpsd_uboot
TITLE:=AT91Bootstrap for SAMA5D2 ICP board (SDcard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-icp
endef
define AT91Bootstrap/sama5d2_xplaineddf_uboot
TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (SPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-xplained
endef
define AT91Bootstrap/sama5d2_xplaineddf_qspi_uboot
TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-xplained
endef
define AT91Bootstrap/sama5d2_xplainedsd_uboot
TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (SDcard/EMMC)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-xplained
endef
define AT91Bootstrap/sama5d3_xplainednf_uboot
TITLE:=AT91Bootstrap for SAMA5D3 Xplained board (Nand Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define AT91Bootstrap/sama5d3_xplainedsd_uboot
TITLE:=AT91Bootstrap for SAMA5D3 Xplained board (SDcard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define AT91Bootstrap/sama5d4_xplainednf_uboot_secure
TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (Nand Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d4-xplained
endef
define AT91Bootstrap/sama5d4_xplaineddf_uboot_secure
TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (SPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d4-xplained
endef
define AT91Bootstrap/sama5d4_xplainedsd_uboot_secure
TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (SDcard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d4-xplained
endef
define AT91Bootstrap/sama5d27_som1_eksd_uboot
TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (SDcard0)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define AT91Bootstrap/sama5d27_som1_ekqspi_uboot
TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define AT91Bootstrap/sama5d27_wlsom1_eksd_uboot
TITLE:=AT91Bootstrap for SAMA5D27 WLSOM1 Ek (SDcard0)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek
endef
define AT91Bootstrap/sama5d27_wlsom1_ekdf_qspi_uboot
TITLE:=AT91Bootstrap for SAMA5D27 WLSOM1 Ek (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek
endef
define AT91Bootstrap/sama5d2_ptc_eknf_uboot
TITLE:=AT91Bootstrap for SAMA5D2 PTC EK (Nand Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-ptc-ek
endef
define AT91Bootstrap/sama5d2_ptc_eksd_uboot
TITLE:=AT91Bootstrap for SAMA5D2 PTC EK (SDCard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-ptc-ek
endef
define AT91Bootstrap/sama7g5eksd_uboot
TITLE:=AT91Bootstrap for SAMA7G5-EK (SDCard)
BUILD_SUBTARGET:=sama7
BUILD_DEVICES:=microchip_sama7g5-ek
endef
AT91BOOTSTRAP_TARGETS := \
at91sam9x5eknf_uboot \
at91sam9x5eksd_uboot \
sam9x60eknf_uboot \
sam9x60eksd_uboot \
sama5d2_icpdf_qspi_uboot \
sama5d2_icpsd_uboot \
sama5d2_xplaineddf_uboot \
sama5d2_xplaineddf_qspi_uboot \
sama5d2_xplainedsd_uboot \
sama5d3_xplainednf_uboot \
sama5d3_xplainedsd_uboot \
sama5d4_xplainednf_uboot_secure \
sama5d4_xplaineddf_uboot_secure \
sama5d4_xplainedsd_uboot_secure \
sama5d27_som1_eksd_uboot \
sama5d27_som1_ekqspi_uboot \
sama5d27_wlsom1_eksd_uboot \
sama5d27_wlsom1_ekdf_qspi_uboot \
sama5d2_ptc_eknf_uboot \
sama5d2_ptc_eksd_uboot \
sama7g5eksd_uboot
define Build/Compile
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
CROSS_COMPILE=$(TARGET_CROSS)
endef
$(eval $(call BuildPackage/AT91Bootstrap))

88
package/boot/at91bootstrap/at91bootstrap.mk Normal file
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@@ -0,0 +1,88 @@
PKG_TARGETS := bin
PKG_FLAGS:=nonshared
export GCC_HONOUR_COPTS=s
define Package/at91bootstrap/install/default
$(CP) -avL $(PKG_BUILD_DIR)/$(BINARIES_DIR)/at91bootstrap.bin $(1)/
endef
Package/at91bootstrap/install = $(Package/at91bootstrap/install/default)
define AT91Bootstrap/Init
BUILD_TARGET:=
BUILD_SUBTARGET:=
BUILD_DEVICES:=
NAME:=
DEPENDS:=
HIDDEN:=
DEFAULT:=
VARIANT:=$(1)
AT91BOOTSTRAP_CONFIG:=$(1)
endef
TARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))
AT91BOOTSTRAP_MAKE_FLAGS = \
HOSTCC="$(HOSTCC)" \
HOSTCFLAGS="$(HOST_CFLAGS) $(HOST_CPPFLAGS)" \
HOSTLDFLAGS=""
define Build/AT91Bootstrap/Target
$(eval $(call AT91Bootstrap/Init,$(1)))
$(eval $(call AT91Bootstrap/Default,$(1)))
$(eval $(call AT91Bootstrap/$(1),$(1)))
define Package/at91bootstrap-$(1)
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:= .$(NAME)
VARIANT:=$(VARIANT)
DEPENDS:=@!IN_SDK $(DEPENDS)
HIDDEN:=$(HIDDEN)
ifneq ($(BUILD_TARGET),)
DEPENDS += @$(TARGET_DEP)
ifneq ($(BUILD_DEVICES),)
DEFAULT := y if ($(TARGET_DEP)_Default \
$(patsubst %,|| $(TARGET_DEP)_DEVICE_%,$(BUILD_DEVICES)) \
$(patsubst %,|| $(patsubst TARGET_%,TARGET_DEVICE_%, \
$(TARGET_DEP))_DEVICE_%,$(BUILD_DEVICES)))
endif
endif
$(if $(DEFAULT),DEFAULT:=$(DEFAULT))
URL:=https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap
endef
define Package/at91bootstrap-$(1)/install
$$(Package/at91bootstrap/install)
endef
endef
define Build/Configure/AT91Bootstrap
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
$(AT91BOOTSTRAP_CONFIG)_defconfig
endef
define Build/Compile/AT91Bootstrap
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
CROSS_COMPILE=$(TARGET_CROSS) \
$(AT91BOOTSTRAP_MAKE_FLAGS)
endef
define BuildPackage/AT91Bootstrap/Defaults
Build/Configure/Default = $$$$(Build/Configure/AT91Bootstrap)
Build/Compile/Default = $$$$(Build/Compile/AT91Bootstrap)
endef
define BuildPackage/AT91Bootstrap
$(eval $(call BuildPackage/AT91Bootstrap/Defaults))
$(foreach type,$(if $(DUMP),$(AT91BOOTSTRAP_TARGETS),$(BUILD_VARIANT)), \
$(eval $(call Build/AT91Bootstrap/Target,$(type)))
)
$(eval $(call Build/DefaultTargets))
$(foreach type,$(if $(DUMP),$(AT91BOOTSTRAP_TARGETS),$(BUILD_VARIANT)), \
$(call BuildPackage,at91bootstrap-$(type))
)
endef

38
package/boot/fconfig/Makefile Normal file
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@@ -0,0 +1,38 @@
#
# Copyright (C) 2006-2008 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=fconfig
PKG_VERSION:=20080329
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@OPENWRT
PKG_HASH:=4ff0e8f07e35e46b705c0dbe9d9544ede01ea092a69e3f7db03e55a3f2bb8eb7
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)
include $(INCLUDE_DIR)/package.mk
define Package/fconfig
SECTION:=utils
CATEGORY:=Utilities
SUBMENU:=Boot Loaders
TITLE:=RedBoot configuration editor
endef
define Package/fconfig/description
displays and (if writable) also edits the RedBoot configuration.
endef
define Package/fconfig/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/fconfig $(1)/usr/sbin/
endef
$(eval $(call BuildPackage,fconfig))

225
package/boot/grub2/Makefile Normal file
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@@ -0,0 +1,225 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2006-2021 OpenWrt.org
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=grub
PKG_VERSION:=2.12
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/grub
PKG_HASH:=f3c97391f7c4eaa677a78e090c7e97e6dc47b16f655f04683ebd37bef7fe0faa
PKG_LICENSE:=GPL-3.0-or-later
PKG_CPE_ID:=cpe:/a:gnu:grub2
HOST_BUILD_PARALLEL:=1
PKG_BUILD_DEPENDS:=grub2/host
ifneq ($(BUILD_VARIANT),none)
PKG_ASLR_PIE:=0
PKG_SSP:=0
endif
PKG_FLAGS:=nonshared
PKG_BUILD_FLAGS:=no-gc-sections no-lto no-mold
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/package.mk
define Package/grub2/Default
CATEGORY:=Boot Loaders
SECTION:=boot
TITLE:=GRand Unified Bootloader ($(2))
URL:=http://www.gnu.org/software/grub/
DEPENDS:=@TARGET_$(1)
VARIANT:=$(2)
endef
Package/grub2=$(call Package/grub2/Default,x86,pc)
Package/grub2-efi=$(call Package/grub2/Default,x86,efi)
Package/grub2-efi-arm=$(call Package/grub2/Default,armsr,efi)
Package/grub2-efi-loongarch64=$(call Package/grub2/Default,loongarch64,efi)
define Package/grub2-editenv
CATEGORY:=Utilities
SECTION:=utils
SUBMENU:=Boot Loaders
TITLE:=Grub2 Environment editor
URL:=http://www.gnu.org/software/grub/
DEPENDS:=@TARGET_x86
VARIANT:=none
endef
define Package/grub2-editenv/description
Edit grub2 environment files.
endef
define Package/grub2-bios-setup
CATEGORY:=Utilities
SECTION:=utils
SUBMENU:=Boot Loaders
TITLE:=Grub2 BIOS boot setup tool
URL:=http://www.gnu.org/software/grub/
DEPENDS:=@TARGET_x86
VARIANT:=none
endef
define Package/grub2-bios-setup/description
Set up images to bootable.
endef
HOST_BUILD_PREFIX := $(STAGING_DIR_HOST)
CONFIGURE_VARS += \
grub_build_mkfont_excuse="don't want fonts"
CONFIGURE_ARGS += \
--target=$(REAL_GNU_TARGET_NAME) \
--disable-werror \
--disable-nls \
--disable-device-mapper \
--disable-libzfs \
--disable-liblzma \
--disable-grub-mkfont \
--with-platform=$(BUILD_VARIANT)
HOST_CONFIGURE_VARS += \
grub_build_mkfont_excuse="don't want fonts"
HOST_CONFIGURE_ARGS += \
--disable-grub-mkfont \
--target=$(REAL_GNU_TARGET_NAME) \
--sbindir="$(STAGING_DIR_HOST)/bin" \
--disable-werror \
--disable-libzfs \
--disable-nls \
--with-platform=none
HOST_MAKE_FLAGS += \
TARGET_RANLIB=$(TARGET_RANLIB) \
LIBLZMA=$(STAGING_DIR_HOST)/lib/liblzma.a
ifneq ($(BUILD_VARIANT),none)
TARGET_CFLAGS := $(filter-out -O2 -O3 -fno-plt,$(TARGET_CFLAGS))
MAKE_PATH := grub-core
endif
ifeq ($(CONFIG_arm),y)
TARGET_CFLAGS := $(filter-out -mfloat-abi=hard,$(TARGET_CFLAGS))
endif
define Host/Configure
$(SED) 's,(RANLIB),(TARGET_RANLIB),' $(HOST_BUILD_DIR)/grub-core/Makefile.in
$(Host/Configure/Default)
endef
define Package/grub2/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2
$(CP) $(PKG_BUILD_DIR)/grub-core/boot.img $(STAGING_DIR_IMAGE)/grub2/
$(CP) $(PKG_BUILD_DIR)/grub-core/cdboot.img $(STAGING_DIR_IMAGE)/grub2/
sed 's#msdos1#gpt1#g' ./files/grub-early.cfg >$(PKG_BUILD_DIR)/grub-early.cfg
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O i386-pc \
-c $(PKG_BUILD_DIR)/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/gpt-core.img \
at_keyboard biosdisk boot chain configfile fat linux ls part_gpt reboot search serial test vga
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O i386-pc \
-c ./files/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/generic-core.img \
at_keyboard biosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial test vga
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O i386-pc \
-c ./files/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/eltorito.img \
at_keyboard biosdisk boot chain configfile iso9660 linux ls part_msdos reboot search serial test vga
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O i386-pc \
-c ./files/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/legacy-core.img \
biosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial vga
endef
define Package/grub2-efi/install
sed 's#msdos1#gpt1#g' ./files/grub-early.cfg >$(PKG_BUILD_DIR)/grub-early.cfg
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O $(CONFIG_ARCH)-efi \
-c $(PKG_BUILD_DIR)/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_x86_64),x64,ia32).efi \
at_keyboard boot chain configfile fat linux ls part_gpt reboot serial test efi_gop efi_uga
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O $(CONFIG_ARCH)-efi \
-c ./files/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/iso-boot$(if $(CONFIG_x86_64),x64,ia32).efi \
boot chain configfile fat iso9660 linux ls part_msdos part_gpt reboot serial test efi_gop efi_uga
endef
define Package/grub2-efi-arm/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2
cp ./files/grub-early-gpt.cfg $(PKG_BUILD_DIR)/grub-early.cfg
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O arm$(if $(CONFIG_aarch64),64,)-efi \
-c $(PKG_BUILD_DIR)/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_aarch64),aa64,arm).efi \
boot chain configfile fat linux ls part_gpt part_msdos reboot search \
search_fs_uuid search_label serial efi_gop lsefi minicmd ext2
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O arm$(if $(CONFIG_aarch64),64,)-efi \
-c ./files/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/iso-bootaa$(if $(CONFIG_aarch64),aa64,arm).efi \
boot chain configfile fat iso9660 linux ls lsefi minicmd part_msdos part_gpt \
reboot serial test efi_gop
endef
define Package/grub2-efi-loongarch64/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2
cp ./files/grub-early-gpt.cfg $(PKG_BUILD_DIR)/grub-early.cfg
$(STAGING_DIR_HOST)/bin/grub-mkimage \
-d $(PKG_BUILD_DIR)/grub-core \
-p /boot/grub \
-O loongarch64-efi \
-c $(PKG_BUILD_DIR)/grub-early.cfg \
-o $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi \
boot chain configfile fat linux ls lsefi minicmd part_gpt part_msdos reboot search \
search_fs_uuid search_label serial efi_gop all_video gfxterm ext2
endef
define Package/grub2-editenv/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/grub-editenv $(1)/usr/sbin/
endef
define Package/grub2-bios-setup/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/grub-bios-setup $(1)/usr/sbin/
endef
$(eval $(call HostBuild))
$(eval $(call BuildPackage,grub2))
$(eval $(call BuildPackage,grub2-efi))
$(eval $(call BuildPackage,grub2-efi-arm))
$(eval $(call BuildPackage,grub2-efi-loongarch64))
$(eval $(call BuildPackage,grub2-editenv))
$(eval $(call BuildPackage,grub2-bios-setup))

2
package/boot/grub2/files/grub-early-gpt.cfg Normal file
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@@ -0,0 +1,2 @@
search --set=root --label kernel
configfile ($root)/efi/openwrt/grub.cfg

1
package/boot/grub2/files/grub-early.cfg Normal file
View File

@@ -0,0 +1 @@
configfile (hd0,msdos1)/boot/grub/grub.cfg

31
package/boot/grub2/patches/001-add-missing-extra_deps-list.patch Normal file
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@@ -0,0 +1,31 @@
From 4d4dae6a52b1749642261a15f5dcc1e3d4150b36 Mon Sep 17 00:00:00 2001
From: Julien Olivain <ju.o@free.fr>
Date: Fri, 22 Dec 2023 19:02:53 +0100
Subject: [PATCH] Add missing grub-core/extra_deps.lst file in release tarball
A file is missing in the grub-2.12 release tarballs (both .gz and .xz).
See [1]. The issue was reported in [2] and fixed upstream in [3].
This patch adds the missing file, on top of the release tarball. This
patch won't apply on upstream git, since the file is present in the
source repository. Since the issue is fixed upstream in [3], it is
expected upcoming releases tarballs will include the file.
The file content was fetched from the upstream git repo:
https://git.savannah.gnu.org/gitweb/?p=grub.git;a=blob_plain;f=grub-core/extra_deps.lst;hb=refs/tags/grub-2.12
[1] https://ftp.gnu.org/gnu/grub/grub-2.12.tar.xz
[2] https://lists.gnu.org/archive/html/grub-devel/2023-12/msg00054.html
[3] https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
Signed-off-by: Julien Olivain <ju.o@free.fr>
Upstream: Fixed by: https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
---
grub-core/extra_deps.lst | 1 +
1 file changed, 1 insertion(+)
create mode 100644 grub-core/extra_deps.lst
--- /dev/null
+++ b/grub-core/extra_deps.lst
@@ -0,0 +1 @@
+depends bli part_gpt

119
package/boot/grub2/patches/100-grub_setup_root.patch Normal file
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@@ -0,0 +1,119 @@
--- a/include/grub/util/install.h
+++ b/include/grub/util/install.h
@@ -199,13 +199,13 @@ grub_install_get_image_target (const cha
void
grub_util_bios_setup (const char *dir,
const char *boot_file, const char *core_file,
- const char *dest, int force,
+ const char *root, const char *dest, int force,
int fs_probe, int allow_floppy,
int add_rs_codes, int warn_short_mbr_gap);
void
grub_util_sparc_setup (const char *dir,
const char *boot_file, const char *core_file,
- const char *dest, int force,
+ const char *root, const char *dest, int force,
int fs_probe, int allow_floppy,
int add_rs_codes, int warn_short_mbr_gap);
--- a/util/grub-install.c
+++ b/util/grub-install.c
@@ -1770,7 +1770,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_bios_setup (platdir, "boot.img", "core.img",
- install_drive, force,
+ NULL, install_drive, force,
fs_probe, allow_floppy, add_rs_codes,
!grub_install_is_short_mbrgap_supported ());
@@ -1801,7 +1801,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_sparc_setup (platdir, "boot.img", "core.img",
- install_drive, force,
+ NULL, install_drive, force,
fs_probe, allow_floppy,
0 /* unused */, 0 /* unused */ );
--- a/util/grub-setup.c
+++ b/util/grub-setup.c
@@ -87,6 +87,8 @@ static struct argp_option options[] = {
N_("install even if problems are detected"), 0},
{"skip-fs-probe",'s',0, 0,
N_("do not probe for filesystems in DEVICE"), 0},
+ {"root-device", 'r', N_("DEVICE"), 0,
+ N_("use DEVICE as the root device"), 0},
{"verbose", 'v', 0, 0, N_("print verbose messages."), 0},
{"allow-floppy", 'a', 0, 0,
/* TRANSLATORS: The potential breakage isn't limited to floppies but it's
@@ -130,6 +132,7 @@ struct arguments
char *core_file;
char *dir;
char *dev_map;
+ char *root_dev;
int force;
int fs_probe;
int allow_floppy;
@@ -178,6 +181,13 @@ argp_parser (int key, char *arg, struct
arguments->dev_map = xstrdup (arg);
break;
+ case 'r':
+ if (arguments->root_dev)
+ free (arguments->root_dev);
+
+ arguments->root_dev = xstrdup (arg);
+ break;
+
case 'f':
arguments->force = 1;
break;
@@ -313,7 +323,7 @@ main (int argc, char *argv[])
GRUB_SETUP_FUNC (arguments.dir ? : DEFAULT_DIRECTORY,
arguments.boot_file ? : DEFAULT_BOOT_FILE,
arguments.core_file ? : DEFAULT_CORE_FILE,
- dest_dev, arguments.force,
+ arguments.root_dev, dest_dev, arguments.force,
arguments.fs_probe, arguments.allow_floppy,
arguments.add_rs_codes, 0);
--- a/util/setup.c
+++ b/util/setup.c
@@ -252,14 +252,13 @@ identify_partmap (grub_disk_t disk __att
void
SETUP (const char *dir,
const char *boot_file, const char *core_file,
- const char *dest, int force,
+ const char *root, const char *dest, int force,
int fs_probe, int allow_floppy,
int add_rs_codes __attribute__ ((unused)), /* unused on sparc64 */
int warn_small)
{
char *core_path;
char *boot_img, *core_img, *boot_path;
- char *root = 0;
size_t boot_size, core_size;
grub_uint16_t core_sectors;
grub_device_t root_dev = 0, dest_dev, core_dev;
@@ -311,7 +310,10 @@ SETUP (const char *dir,
core_dev = dest_dev;
- {
+ if (root)
+ root_dev = grub_device_open(root);
+
+ if (!root_dev) {
char **root_devices = grub_guess_root_devices (dir);
char **cur;
int found = 0;
@@ -324,6 +326,8 @@ SETUP (const char *dir,
char *drive;
grub_device_t try_dev;
+ if (root_dev)
+ break;
drive = grub_util_get_grub_dev (*cur);
if (!drive)
continue;

42
package/boot/imx-bootlets/Makefile Normal file
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@@ -0,0 +1,42 @@
#
# Copyright (C) 2006 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=imx-bootlets
PKG_VERSION:=10.05.02
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://trabant.uid0.hu/openwrt/
PKG_HASH:=09ecd81a64db5166a235932146faf08d0689bfc7ac04ac9fcc3a5bd809fba74a
include $(INCLUDE_DIR)/package.mk
define Package/imx-bootlets
SECTION:=boot
CATEGORY:=Boot Loaders
TITLE:=i.MX23/i.MX28 bootlets
DEPENDS:=@TARGET_mxs
endef
define Package/imx-bootlets/description
i.MX23/i.MX28 bootlets (for oLinuxino)
endef
define Build/Compile
$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)"
endef
define Package/imx-bootlets/install
@echo Copying boot_prep and power_prep into staging - $(STAGING_DIR)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/boot_prep/boot_prep $(STAGING_DIR)/boot_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prep/output-target/linux_prep $(STAGING_DIR)/linux_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/power_prep/power_prep $(STAGING_DIR)/power_prep
$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prebuilt.db $(STAGING_DIR)/linux_prebuilt.db
endef
$(eval $(call BuildPackage,imx-bootlets))

18
package/boot/imx-bootlets/patches/001-skip_sb_generation.patch Normal file
View File

@@ -0,0 +1,18 @@
--- a/Makefile
+++ b/Makefile
@@ -32,10 +32,11 @@ ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IM
sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db
elftosb2 -z -c ./uboot.db -o i$(ARCH)_uboot.sb
else
- @echo "by using the pre-built kernel"
- elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb
- @echo "generating U-Boot boot stream image"
- elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb
+ @echo "... not generating any image for now."
+ #@echo "by using the pre-built kernel"
+ #elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb
+ #@echo "generating U-Boot boot stream image"
+ #elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb
endif
#@echo "generating kernel bootstream file sd_mmc_bootstream.raw"
#Please use cfimager to burn xxx_linux.sb. The below way will no

17
package/boot/imx-bootlets/patches/002-set_elftosb_config.patch Normal file
View File

@@ -0,0 +1,17 @@
--- a/linux_prebuilt.db
+++ b/linux_prebuilt.db
@@ -4,10 +4,10 @@ options {
flags = 0x01;
}
sources {
- power_prep="./power_prep/power_prep";
- sdram_prep="./boot_prep/boot_prep";
- linux_prep="./linux_prep/output-target/linux_prep";
- zImage = "./zImage";
+ power_prep="./power_prep";
+ sdram_prep="./boot_prep";
+ linux_prep="./linux_prep";
+ zImage = "./zImage_dtb";
}
section (0) {

143
package/boot/imx-bootlets/patches/003-add-olinuxino.patch Normal file
View File

@@ -0,0 +1,143 @@
--- /dev/null
+++ b/linux_prep/board/imx23_olinuxino_dev.c
@@ -0,0 +1,54 @@
+/*
+ * Platform specific data for the IMX23_OLINUXINO development board
+ *
+ * Fadil Berisha <fadil.r.berisha@gmail.com>
+ *
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <setup.h>
+#include <keys.h>
+#include <lradc_buttons.h>
+
+/************************************************
+ * LRADC keyboard data *
+ ************************************************/
+int lradc_keypad_ch = LRADC_CH0;
+int lradc_vddio_ch = LRADC_CH6;
+
+struct lradc_keycode lradc_keycodes[] = {
+ { 100, KEY4 },
+ { 306, KEY5 },
+ { 601, KEY6 },
+ { 932, KEY7 },
+ { 1260, KEY8 },
+ { 1424, KEY9 },
+ { 1707, KEY10 },
+ { 2207, KEY11 },
+ { 2525, KEY12 },
+ { 2831, KEY13 },
+ { 3134, KEY14 },
+ { -1, 0 },
+};
+
+/************************************************
+ * Magic key combinations for Armadillo *
+ ************************************************/
+u32 magic_keys[MAGIC_KEY_NR] = {
+ [MAGIC_KEY1] = KEY4,
+ [MAGIC_KEY2] = KEY6,
+ [MAGIC_KEY3] = KEY10,
+};
+
+/************************************************
+ * Default command line *
+ ************************************************/
+char cmdline_def[] = "console=ttyAMA0,115200";
--- /dev/null
+++ b/linux_prep/cmdlines/imx23_olinuxino_dev.txt
@@ -0,0 +1 @@
+noinitrd console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait ssp1=mmc
--- a/linux_prep/core/setup.c
+++ b/linux_prep/core/setup.c
@@ -84,6 +84,8 @@ static void *memcpy(void *s1, const void
#include "../../mach-mx28/includes/registers/regsrtc.h"
#elif defined(STMP378X)
#include "../../mach-mx23/includes/registers/regsrtc.h"
+#elif defined(IMX23_OLINUXINO)
+#include "../../mach-mx23/includes/registers/regsrtc.h"
#endif
#define NAND_SECONDARY_BOOT 0x00000002
--- a/linux_prep/include/mx23/platform.h
+++ b/linux_prep/include/mx23/platform.h
@@ -19,6 +19,10 @@
#if defined (BOARD_STMP378X_DEV)
#define MACHINE_ID 0xa45
+
+#elif defined (BOARD_IMX23_OLINUXINO_DEV)
+#define MACHINE_ID 0x1009
+
#else
#error "Allocate a machine ID for your board"
#endif
--- a/linux_prep/Makefile
+++ b/linux_prep/Makefile
@@ -69,6 +69,11 @@ ARCH = mx28
HW_OBJS = $(LRADC_OBJS)
CFLAGS += -DMX28 -DBOARD_MX28_EVK
endif
+ifeq ($(BOARD), imx23_olinuxino_dev)
+ARCH = mx23
+HW_OBJS = $(LRADC_OBJS)
+CFLAGS += -DIMX23_OLINUXINO -DBOARD_IMX23_OLINUXINO_DEV
+endif
# Generic code
CORE_OBJS = entry.o resume.o cmdlines.o setup.o keys.o
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@ MEM_TYPE ?= MEM_DDR1
export MEM_TYPE
DFT_IMAGE=$(DEV_IMAGE)/boot/zImage
-DFT_UBOOT=$(DEV_IMAGE)/boot/u-boot
+DFT_UBOOT=../boot/u-boot
-BOARD ?= stmp378x_dev
+BOARD ?= imx23_olinuxino_dev
ifeq ($(BOARD), stmp37xx_dev)
ARCH = 37xx
@@ -16,6 +16,9 @@ endif
ifeq ($(BOARD), iMX28_EVK)
ARCH = mx28
endif
+ifeq ($(BOARD), imx23_olinuxino_dev)
+ARCH = mx23
+endif
all: build_prep gen_bootstream
@@ -94,6 +97,8 @@ distclean: clean
clean:
-rm -rf *.sb
rm -f sd_mmc_bootstream.raw
+ rm -f linux_prep/board/*.o
+ rm -f power_prep/*.o
$(MAKE) -C linux_prep clean ARCH=$(ARCH)
$(MAKE) -C boot_prep clean ARCH=$(ARCH)
$(MAKE) -C power_prep clean ARCH=$(ARCH)
--- a/uboot.db
+++ b/uboot.db
@@ -3,7 +3,7 @@
sources {
power_prep="./power_prep/power_prep";
sdram_prep="./boot_prep/boot_prep";
- image="/home/b18647/repos/ltib_latest/rootfs/boot/u-boot";
+ image="../boot/u-boot";
}
section (0) {

14
package/boot/kexec-tools/Config.in Normal file
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@@ -0,0 +1,14 @@
menu "Configuration"
depends on PACKAGE_kexec
config KEXEC_ZLIB
bool
prompt "zlib support"
default y
config KEXEC_LZMA
bool
prompt "lzma support"
default n
endmenu

132
package/boot/kexec-tools/Makefile Normal file
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@@ -0,0 +1,132 @@
#
# Copyright (C) 2006-2012 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=kexec-tools
PKG_VERSION:=2.0.28
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec
PKG_HASH:=d2f0ef872f39e2fe4b1b01feb62b0001383207239b9f8041f98a95564161d053
PKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA
PKG_BUILD_FLAGS:=gc-sections
include $(INCLUDE_DIR)/package.mk
define Package/kexec-tools/Default
SECTION:=utils
CATEGORY:=Utilities
URL:=http://kernel.org/pub/linux/kernel/people/horms/kexec-tools/
endef
define Package/kexec-tools
$(call Package/kexec-tools/Default)
TITLE:=kexec-tools transition meta package
DEPENDS:=+kexec
endef
define Package/kexec-tools/description
kexec is a set of system calls that allows you to load
another kernel from the currently executing Linux kernel.
The kexec utility allows to load and boot another kernel.
endef
define Package/kexec
$(call Package/kexec-tools/Default)
TITLE:=Kernel boots kernel
DEPENDS:=\
@(armeb||arm||i386||x86_64||powerpc64||mipsel||mips) \
+KEXEC_ZLIB:zlib +KEXEC_LZMA:liblzma @KERNEL_KEXEC
endef
define Package/kexec/description
The kexec utility allows to load and boot another kernel.
endef
define Package/kdump
$(call Package/kexec-tools/Default)
TITLE:=Kernel crash analysis
DEPENDS:=+kexec @(i386||x86_64||arm) @KERNEL_CRASH_DUMP
endef
define Package/kdump/description
The kdump package allows to automatically boot into a
special kernel for analyzing kernel crashes using kdump.
endef
define Package/kexec/config
source "$(SOURCE)/Config.in"
endef
KEXEC_TARGET_NAME:=$(ARCH)-linux-$(TARGET_SUFFIX)
CONFIGURE_ARGS = \
--target=$(KEXEC_TARGET_NAME) \
--host=$(REAL_GNU_TARGET_NAME) \
--build=$(GNU_HOST_NAME) \
--program-prefix="" \
--program-suffix="" \
--prefix=/usr \
--exec-prefix=/usr \
--bindir=/usr/bin \
--sbindir=/usr/sbin \
--libexecdir=/usr/lib \
--sysconfdir=/etc \
$(if $(CONFIG_KEXEC_ZLIB),--with,--without)-zlib \
$(if $(CONFIG_KEXEC_LZMA),--with,--without)-lzma \
TARGET_LD="$(TARGET_CROSS)ld"
CONFIGURE_VARS += \
BUILD_CC="$(HOSTCC)" \
TARGET_CC="$(TARGET_CC)"
define Build/Compile
$(MAKE) -C $(PKG_BUILD_DIR) DESTDIR="$(PKG_INSTALL_DIR)" all install
endef
define Package/kexec-tools/install
:
endef
define Package/kexec/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/kexec $(1)/usr/sbin
# make a link for compatability with other distros
$(INSTALL_DIR) $(1)/sbin
$(LN) ../usr/sbin/kexec $(1)/sbin/kexec
endef
define Package/kdump/install
$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d $(1)/etc/config $(1)/etc/uci-defaults
$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/vmcore-dmesg $(1)/usr/sbin
$(INSTALL_BIN) ./files/kdump.init $(1)/etc/init.d/kdump
$(INSTALL_BIN) ./files/kdump.defaults $(1)/etc/uci-defaults/kdump
$(INSTALL_CONF) ./files/kdump.config $(1)/etc/config/kdump
endef
define Package/kdump/prerm
#!/bin/sh
case $$(uname -m) in
i?86|x86_64)
if grep -q " crashkernel=" /boot/grub/grub.cfg; then
mount /boot -o remount,rw
sed -i 's/ crashkernel=[^ ]*//' /boot/grub/grub.cfg
mount /boot -o remount,ro
fi
;;
esac
endef
$(eval $(call BuildPackage,kexec-tools))
$(eval $(call BuildPackage,kexec))
$(eval $(call BuildPackage,kdump))

7
package/boot/kexec-tools/files/kdump.config Normal file
View File

@@ -0,0 +1,7 @@
config kdump
option enabled '1'
option save_dmesg '1'
option save_vmcore '0'
# using an external partition to store vmcore is highly recommended!
# option path '/mnt/crashdump'

23
package/boot/kexec-tools/files/kdump.defaults Normal file
View File

@@ -0,0 +1,23 @@
#!/bin/sh
# kB disable if mem low than 256MB
memtotal=`grep MemTotal /proc/meminfo | awk '{print $2}'`
if test $memtotal -le 262144; then
exit 0
fi
KZ=128
if test $memtotal -ge 8388608; then
KZ=512
elif test $memtotal -ge 4194304; then
KZ=256
fi
case $(uname -m) in
i?86|x86_64)
if ! grep -q crashkernel /boot/grub/grub.cfg; then
mount /boot -o remount,rw
sed -i "s/linux.*/& crashkernel=${KZ}M/" /boot/grub/grub.cfg
mount /boot -o remount,ro
fi
;;
esac

186
package/boot/kexec-tools/files/kdump.init Executable file
View File

@@ -0,0 +1,186 @@
#!/bin/sh /etc/rc.common
START=41
STOP=90
BOOT_IMAGE=/boot/vmlinuz
EXTRA_COMMANDS="status"
EXTRA_HELP=" status Print crashkernel status"
verify_kdump() {
local cfg="$1"
local enabled
local path
local save_vmcore
local save_dmesg
config_get_bool enabled "$cfg" enabled 1
config_get_bool save_dmesg "$cfg" save_dmesg 1
config_get_bool save_vmcore "$cfg" save_vmcore 0
[ "$enabled" -gt 0 ] || return 2
[ "$save_dmesg" -gt 0 ] || [ "$save_vmcore" -gt 0 ] || return 2
config_get path "$cfg" path "/"
[ -d "$path" ] || mkdir -p "$path" 2>/dev/null || return 1
}
run_kdump() {
local cfg="$1"
local enabled
local path
local save_vmcore
local save_dmesg
config_get_bool enabled "$cfg" enabled 1
[ "$enabled" -gt 0 ] || return
config_get_bool save_dmesg "$cfg" save_dmesg 1
config_get_bool save_vmcore "$cfg" save_vmcore 0
config_get path "$cfg" path "/"
timestamp=$(date "+%Y%m%dT%H%M%S")
if [ "$save_vmcore" -eq 1 ]; then
echo -n "Saving vmcore (this may take a while)..."
# would like 'sparse' but busybox doesn't support it
dd if=/proc/vmcore of="$path/vmcore-$timestamp" conv=fsync bs=1M
echo " done"
fi
if [ "$save_dmesg" -eq 1 ]; then
vmcore-dmesg /proc/vmcore > "$path/dmesg-$timestamp"
fi
sync
reboot -f
}
find_kernel() {
. /lib/functions.sh
local kernel
kernel="$BOOT_IMAGE"
if [ -r "$kernel" ]; then
echo $kernel
return 0
fi
kernel="$(find_mtd_part kernel)"
if [ -r "$kernel" ]; then
echo $kernel
return 0
fi
for voldir in /sys/class/ubi/ubi*_*; do
[ ! -e "$voldir" ] && continue
if [ "$(cat "${voldir}/name")" = "kernel" ]; then
kernel="/dev/$(basename "$voldir")"
echo $kernel
return 0
fi
done
return 1
}
load_crashkernel() {
local append_cmdline
local kernel
kernel="$(find_kernel)"
[ $? -gt 0 ] && return 1
case "$(uname -m)" in
i?86|x86_64)
grep -q "crashkernel=" /proc/cmdline || return 1
append_cmdline="1 irqpoll reset_devices maxcpus=1"
;;
arm*)
append_cmdline="1 maxcpus=1 reset_devices"
;;
esac
kexec -p "$kernel" --reuse-cmdline --append="$append_cmdline"
return $?
}
start() {
local retval
if [ ! -e /sys/kernel/kexec_crash_loaded ]; then
return 1
fi
if [ -e /proc/vmcore ]; then
config_load kdump
config_foreach run_kdump kdump
else
config_load kdump
config_foreach verify_kdump kdump
retval=$?
[ $retval = 1 ] && return 1
[ $retval = 0 ] && load_crashkernel
return $?
fi
}
stop() {
[ "$(cat /sys/kernel/kexec_crash_loaded)" = "1" ] || return
if [ -e "$BOOT_IMAGE" ]; then
kexec -p -u "$BOOT_IMAGE"
fi
}
status() {
local retval kernel
if [ ! -e /sys/kernel/kexec_crash_loaded ]; then
echo "crashdump not supported by kernel"
return
fi
if [ $(cat /sys/kernel/kexec_crash_size) -eq 0 ]; then
echo "memory for crashdump kernel not reserved!"
echo "check crashkernel= kernel cmdline parameter"
echo "(a reboot is required after installing kdump)"
return
fi
kernel="$(find_kernel)"
if [ $? -gt 0 ]; then
echo "cannot find kernel image"
return
else
echo "using kernel image $kernel"
fi
echo -n "kdump configuration is "
config_load kdump
retval=$?
if [ $retval = 0 ]; then
if [ "$(config_foreach echo kdump)" ]; then
config_foreach verify_kdump kdump
retval=$?
else
retval=1
fi
fi
if [ $retval = 0 ]; then
echo "valid"
elif [ $retval = 2 ]; then
echo "disabled"
else
echo "BROKEN"
fi
echo -n "kexec crash kernel "
if [ "$(cat /sys/kernel/kexec_crash_loaded)" = "0" ]; then
echo -n "not "
fi
echo "loaded"
}

81
package/boot/kexec-tools/patches/010-Fix-building-on-x86_64-with-binutils-2.41.patch Normal file
View File

@@ -0,0 +1,81 @@
From 328de8e00e298f00d7ba6b25dc3950147e9642e6 Mon Sep 17 00:00:00 2001
From: Michel Lind <salimma@fedoraproject.org>
Date: Tue, 30 Jan 2024 04:14:31 -0600
Subject: [PATCH] Fix building on x86_64 with binutils 2.41
Newer versions of the GNU assembler (observed with binutils 2.41) will
complain about the ".arch i386" in files assembled with "as --64",
with the message "Error: 64bit mode not supported on 'i386'".
Fix by moving ".arch i386" below the relevant ".code32" directive, so
that the assembler is no longer expecting 64-bit instructions to be used
by the time that the ".arch i386" directive is encountered.
Based on similar iPXE fix:
https://github.com/ipxe/ipxe/commit/6ca597eee
Signed-off-by: Michel Lind <michel@michel-slm.name>
Signed-off-by: Simon Horman <horms@kernel.org>
---
purgatory/arch/i386/entry32-16-debug.S | 2 +-
purgatory/arch/i386/entry32-16.S | 2 +-
purgatory/arch/i386/entry32.S | 2 +-
purgatory/arch/i386/setup-x86.S | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
--- a/purgatory/arch/i386/entry32-16-debug.S
+++ b/purgatory/arch/i386/entry32-16-debug.S
@@ -25,10 +25,10 @@
.globl entry16_debug_pre32
.globl entry16_debug_first32
.globl entry16_debug_old_first32
- .arch i386
.balign 16
entry16_debug:
.code32
+ .arch i386
/* Compute where I am running at (assumes esp valid) */
call 1f
1: popl %ebx
--- a/purgatory/arch/i386/entry32-16.S
+++ b/purgatory/arch/i386/entry32-16.S
@@ -20,10 +20,10 @@
#undef i386
.text
.globl entry16, entry16_regs
- .arch i386
.balign 16
entry16:
.code32
+ .arch i386
/* Compute where I am running at (assumes esp valid) */
call 1f
1: popl %ebx
--- a/purgatory/arch/i386/entry32.S
+++ b/purgatory/arch/i386/entry32.S
@@ -20,10 +20,10 @@
#undef i386
.text
- .arch i386
.globl entry32, entry32_regs
entry32:
.code32
+ .arch i386
/* Setup a gdt that should that is generally usefully */
lgdt %cs:gdt
--- a/purgatory/arch/i386/setup-x86.S
+++ b/purgatory/arch/i386/setup-x86.S
@@ -21,10 +21,10 @@
#undef i386
.text
- .arch i386
.globl purgatory_start
purgatory_start:
.code32
+ .arch i386
/* Load a gdt so I know what the segment registers are */
lgdt %cs:gdt

37
package/boot/kexec-tools/patches/020-i386-improve-basename-compatibility.patch Normal file
View File

@@ -0,0 +1,37 @@
From 99f62f58fac57214ecc3c9aabf6bf61ac1e1201d Mon Sep 17 00:00:00 2001
From: Tony Ambardar <itugrok@yahoo.com>
Date: Fri, 7 Jun 2024 21:54:56 -0700
Subject: [PATCH] i386: improve basename() compatibility
Drop usage of glibc basename() in favour of a simpler implementation that
works across GNU and musl libc, and is similar to existing code in fs2dt.c.
This fixes compile errors seen building against musl.
Signed-off-by: Tony Ambardar <itugrok@yahoo.com>
---
kexec/arch/i386/x86-linux-setup.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/kexec/arch/i386/x86-linux-setup.c
+++ b/kexec/arch/i386/x86-linux-setup.c
@@ -318,6 +318,7 @@ static int add_edd_entry(struct x86_linu
uint8_t devnum, version;
uint32_t mbr_sig;
struct edd_info *edd_info;
+ char *basename = strrchr(sysfs_name,'/') + 1;
if (!current_mbr || !current_edd) {
fprintf(stderr, "%s: current_edd and current_edd "
@@ -329,9 +330,9 @@ static int add_edd_entry(struct x86_linu
memset(edd_info, 0, sizeof(struct edd_info));
/* extract the device number */
- if (sscanf(basename(sysfs_name), "int13_dev%hhx", &devnum) != 1) {
+ if (sscanf(basename, "int13_dev%hhx", &devnum) != 1) {
fprintf(stderr, "Invalid format of int13_dev dir "
- "entry: %s\n", basename(sysfs_name));
+ "entry: %s\n", basename);
return -1;
}

46
package/boot/kobs-ng/Makefile Normal file
View File

@@ -0,0 +1,46 @@
#
# Copyright (C) 2013-2014 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=kobs-ng
PKG_VERSION:=5.4
PKG_RELEASE:=1
PKG_SOURCE:=imx-kobs-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://www.freescale.com/lgfiles/NMG/MAD/YOCTO/
PKG_HASH:=85171b46068ac47c42fedb8104167bf9afd33dd9527ed127e1ca2eb29d7a86bf
PKG_BUILD_DIR:=$(BUILD_DIR)/imx-kobs-$(PKG_VERSION)
PKG_LICENSE:=GPLv2
PKG_LICENSE_FILES:=COPYING
include $(INCLUDE_DIR)/package.mk
define Package/kobs-ng
SECTION:=utils
CATEGORY:=Utilities
TITLE:=Application for writing bootstreams to NAND flash
DEPENDS:=@TARGET_imx
endef
define Package/kobs-ng/description
The kobs-ng application writes a bootstream to NAND flash with the proper
FCB/DBBT headers and replicated streams.
endef
define Build/Prepare
$(call Build/Prepare/Default)
echo "const char* git_sha = \"$(PKG_VERSION)\";" > $(PKG_BUILD_DIR)/autoversion.h
endef
define Package/kobs-ng/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/kobs-ng $(1)/usr/sbin/
endef
$(eval $(call BuildPackage,kobs-ng))

24
package/boot/kobs-ng/patches/001-compile.patch Normal file
View File

@@ -0,0 +1,24 @@
--- a/src/mtd.c
+++ b/src/mtd.c
@@ -28,6 +28,7 @@
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
+#include <stddef.h>
#include <fcntl.h>
#include <ctype.h>
#include <errno.h>
--- a/src/mtd.h
+++ b/src/mtd.h
@@ -25,8 +25,11 @@
#ifndef MTD_H
#define MTD_H
+#define _GNU_SOURCE
#include <mtd/mtd-user.h>
#include <endian.h>
+#include <stdint.h>
+#include <fcntl.h>
#include "BootControlBlocks.h"
#include "rom_nand_hamming_code_ecc.h"

45
package/boot/kobs-ng/patches/002-add-init-size-param.patch Normal file
View File

@@ -0,0 +1,45 @@
Add --chip_0_size param to override the size of the mtd partition which is
required if the SPL does not occupy the entire partition. For Gateworks
Ventana boards the 'uboot' partition contains both the SPL and uboot.
--- a/src/main.c
+++ b/src/main.c
@@ -94,6 +94,7 @@ void usage(void)
" [KOBS] boot structures config options\n"
" --chip_0_device_path=<path> .......... Device of boot (default /dev/mtd0)\n"
" --chip_1_device_path=<path> .......... The second chip in case of multichip NAND\n"
+ " --chip_0_size=<size> ................. Override size of chip_0 device\n"
" --search_exponent=<value> ............ NCB field (default 2)\n"
" --data_setup_time=<value> ............ NCB field (default 80)\n"
" --data_hold_time=<value> ............. NCB field (default 60)\n"
--- a/src/mtd.c
+++ b/src/mtd.c
@@ -876,6 +876,11 @@ struct mtd_data *mtd_open(const struct m
goto out;
}
+ /* override MTD size */
+ if (md->cfg.chip_0_size) {
+ miu->size = md->cfg.chip_0_size;
+ }
+
/* verify it's a nand */
if (miu->type != MTD_NANDFLASH
&& miu->type != MTD_MLCNANDFLASH) {
@@ -3385,7 +3390,7 @@ static const struct {
} mtd_int_args[] = {
ARG_IGNORE(chip_count),
ARG_IGNORE(chip_0_offset),
- ARG_IGNORE(chip_0_size),
+ ARG(chip_0_size),
ARG_IGNORE(chip_1_offset),
ARG_IGNORE(chip_1_size),
ARG(search_exponent),
@@ -3578,7 +3583,7 @@ void mtd_cfg_dump(struct mtd_config *cfg
// Pd(chip_count);
Ps(chip_0_device_path);
// Pd(chip_0_offset);
-// Pd(chip_0_size);
+ Pd(chip_0_size);
Ps(chip_1_device_path);
// Pd(chip_1_offset);
// Pd(chip_1_size);

45
package/boot/kobs-ng/patches/003-raw-mode.patch Normal file
View File

@@ -0,0 +1,45 @@
The downstream Freescale vendor kernel has a patch that allows determining
if raw NAND flash mode is provided via a debugfs file. This is not present
in upstream kernels, but the raw access support was added in the 3.19
kernel, so we will check the kernel version if we can't find the file.
--- a/src/mtd.c
+++ b/src/mtd.c
@@ -34,6 +34,7 @@
#include <errno.h>
#include <sys/types.h>
#include <sys/ioctl.h>
+#include <sys/utsname.h>
#include "mtd.h"
#include "rand.h"
@@ -808,15 +809,27 @@ struct mtd_data *mtd_open(const struct m
md->cfg = *cfg;
/* check if use new raw access mode */
+ /* by looking for debugfs from fsl patch */
+ md->raw_mode_flag = 0;
fp = fopen("/sys/kernel/debug/gpmi-nand/raw_mode", "r");
if (!fp) {
- md->raw_mode_flag = 0;
- vp(md, "mtd: use legacy raw access mode\n");
+ /* fallback to kernel version: raw access added in 3.19 */
+ struct utsname uts;
+ if (!uname(&uts)) {
+ int major = 0, minor = 0;
+ sscanf(uts.release, "%d.%d", &major, &minor);
+ vp(md, "mtd: Linux %d.%d\n", major, minor);
+ if ((major << 8 | minor) > (3 << 8 | 18))
+ md->raw_mode_flag = 1;
+ }
} else {
fclose(fp);
md->raw_mode_flag = 1;
- vp(md, "mtd: use new bch layout raw access mode\n");
}
+ if (md->raw_mode_flag)
+ vp(md, "mtd: use new bch layout raw access mode\n");
+ else
+ vp(md, "mtd: use legacy raw access mode\n");
if (plat_config_data->m_u32UseMultiBootArea) {

27
package/boot/kobs-ng/patches/004-fix-cal_nfc_geometry.patch Normal file
View File

@@ -0,0 +1,27 @@
The Freescale downstream vendor kernel has a patch that exports the bch
flash geometry via a debugfs file. This is not available in mainline linux
kernels so the fallback method calculates the geometry based on known info
from the mtd partition. A bug exists in this funcion where it fails to
assume that block0 ECC is the same as the other blocks by default.
--- a/src/mtd.c
+++ b/src/mtd.c
@@ -610,7 +610,7 @@ static int cal_nfc_geometry(struct mtd_d
/* The two are fixed, please change them when the driver changes. */
geo->metadata_size_in_bytes = 10;
geo->gf_len = 13;
- geo->ecc_chunkn_size_in_bytes = 512;
+ geo->ecc_chunkn_size_in_bytes = geo->ecc_chunk0_size_in_bytes = 512;
if (mtd->oobsize > geo->ecc_chunkn_size_in_bytes) {
geo->gf_len = 14;
@@ -700,8 +700,9 @@ int parse_nfc_geometry(struct mtd_data *
unsigned int value;
if (!plat_config_data->m_u32UseNfcGeo) {
+ /* fsl kernel patch provides bch_geometry via debugfs */
if (!(node = fopen(dbg_geometry_node_path, "r"))) {
- fprintf(stderr, "Cannot open BCH geometry node: \"%s\"",
+ fprintf(stderr, "Cannot open BCH geometry node: \"%s\"\n",
dbg_geometry_node_path);
return cal_nfc_geometry(md);
}

69
package/boot/mt7623n-preloader/Makefile Normal file
View File

@@ -0,0 +1,69 @@
#
# Copyright © 2020 David Woodhouse <dwmw2@infradead.org>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=mt7623n-preloader
PKG_VERSION:=2020-03-11
PKG_RELEASE:=b27114e184449a33b5d875fda14198f5e6fee2bb
PKG_MAINTAINER:=David Woodhouse <dwmw2@infradead.org>
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)/$(PKG_NAME)-$(PKG_RELEASE)
PKG_FLAGS:=nonshared
include $(INCLUDE_DIR)/package.mk
BPI_PRELOADER_URL:=@GITHUB/BPI-SINOVOIP/BPI-files/$(PKG_RELEASE)/SD/100MB/
BPI_PRELOADER_PREFIX:=bpi-preloader-$(PKG_RELEASE)
define Download/BPI-R2-preloader-2k.img.gz
FILE:=$(BPI_PRELOADER_PREFIX)-BPI-R2-preloader-DDR1600-20191024-2k.img.gz
URL:=$(BPI_PRELOADER_URL)
URL_FILE:=BPI-R2-preloader-DDR1600-20191024-2k.img.gz
HASH:=c731cc166c912c84846e2ed5faf727504e4dec1463754baa6328e9908c84a373
endef
$(eval $(call Download,BPI-R2-preloader-2k.img.gz))
define Download/BPI-R64-preloader-2k.img.gz
FILE:=$(BPI_PRELOADER_PREFIX)-BPI-R64-preloader-2k.img.gz
URL:=$(BPI_PRELOADER_URL)
URL_FILE:=BPI-R64-preloader-2k.img.gz
HASH:=1a4b55da1717190aa4e790ce93850605e9b15aae4c3248bcf8734aac020ab0e4
endef
$(eval $(call Download,BPI-R64-preloader-2k.img.gz))
define Package/mt7623n-preloader
SECTION:=boot
CATEGORY:=Boot Loaders
DEPENDS:=@TARGET_mediatek_mt7623
TITLE:=mt7623n-preloader
DEFAULT:=y if TARGET_mediatek
endef
define Package/mt7623n-preloader/description
Preloader image for mt7623n based boards like Banana Pi R2.
endef
define Build/Prepare
rm -rf $(PKG_BUILD_DIR)
mkdir -p $(PKG_BUILD_DIR)
cp $(DL_DIR)/$(BPI_PRELOADER_PREFIX)-BPI-R2-preloader-DDR1600-20191024-2k.img.gz $(PKG_BUILD_DIR)/mt7623n_bpir2-preloader.bin.gz
endef
define Build/Compile
true
endef
define Build/InstallDev
mkdir -p $(STAGING_DIR_IMAGE)
gunzip -c $(PKG_BUILD_DIR)/mt7623n_bpir2-preloader.bin.gz > $(STAGING_DIR_IMAGE)/mt7623n_bpir2-preloader.bin
endef
$(eval $(call BuildPackage,mt7623n-preloader))

63
package/boot/opensbi/Makefile Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2022 OpenWrt.org
#
include $(TOPDIR)/rules.mk
PKG_NAME:=opensbi
PKG_RELEASE:=1.4
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/riscv/opensbi
PKG_SOURCE_DATE:=2023-12-24
PKG_SOURCE_VERSION:=a2b255b88918715173942f2c5e1f97ac9e90c877
PKG_MIRROR_HASH:=a81d7b3622feba80b2a45fe0d38600be73cfbee64a0426be82a71545c10c54d3
PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_TARGETS:=bin
PKG_FLAGS:=nonshared
PKG_LICENSE:=BSD-2-Clause
PKG_LICENSE_FILES:=COPYING.BSD
PKG_BUILD_PARALLEL:=1
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
include $(INCLUDE_DIR)/package.mk
define Package/opensbi
SECTION:=boot
CATEGORY:=Boot Loaders
DEPENDS:=@(TARGET_sifiveu||TARGET_d1)
URL:=https://github.com/riscv/opensbi/blob/master/README.md
VARIANT:=$(subst _,/,$(subst opensbi_,,$(1)))
TITLE:=OpenSBI generic
OPENSBI_IMAGE:=
PLAT:=
endef
define Package/opensbi_generic
$(Package/opensbi)
TITLE:=OpenSBI generic
OPENSBI_IMAGE:=fw_dynamic.bin
PLAT:=generic
endef
export GCC_HONOUR_COPTS=s
MAKE_VARS = \
CROSS_COMPILE="$(TARGET_CROSS)"
define Build/Compile
$(eval $(Package/opensbi_$(BUILD_VARIANT))) \
+$(MAKE_VARS) $(MAKE) -C $(PKG_BUILD_DIR) \
PLATFORM=$(PLAT)
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/build/platform/$(PLAT)/firmware/fw_dynamic.bin $(STAGING_DIR_IMAGE)/fw_dynamic-${BUILD_VARIANT}.bin
endef
$(eval $(call BuildPackage,opensbi_generic))

109
package/boot/rkbin/Makefile Normal file
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@@ -0,0 +1,109 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2021-2023 ImmortalWrt.org
include $(TOPDIR)/rules.mk
PKG_NAME:=rkbin
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/rockchip-linux/rkbin.git
PKG_SOURCE_DATE:=2024-02-22
PKG_SOURCE_VERSION:=a2a0b89b6c8c612dca5ed9ed8a68db8a07f68bc0
PKG_MIRROR_HASH:=39f15e5f8fac02026065b6747b355b93f4e06202783ae448c43607763211597c
PKG_LICENSE_FILES:=LICENSE
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
include $(INCLUDE_DIR)/kernel.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
define Trusted-Firmware-A/Default
NAME:=Rockchip $(1) SoCs
BUILD_TARGET:=rockchip
endef
define Trusted-Firmware-A/rk3308
BUILD_SUBTARGET:=armv8
ATF:=rk33/rk3308_bl31_v2.26.elf
TPL:=rk33/rk3308_ddr_589MHz_uart2_m1_v2.07.bin
endef
define Trusted-Firmware-A/rk3308-rock-pi-s
NAME:=Radxa ROCK Pi S
BUILD_SUBTARGET:=armv8
ATF:=rk33/rk3308_bl31_v2.26.elf
TPL:=rk33/rk3308_ddr_589MHz_uart0_m0_v2.07.bin
endef
define Trusted-Firmware-A/rk3566
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.44.elf
TPL:=rk35/rk3566_ddr_1056MHz_v1.21.bin
endef
define Trusted-Firmware-A/rk3568
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.44.elf
TPL:=rk35/rk3568_ddr_1560MHz_v1.21.bin
endef
define Trusted-Firmware-A/rk3568-e25
NAME:=Radxa E25 board
BUILD_SUBTARGET:=armv8
ATF:=rk35/rk3568_bl31_v1.44.elf
TPL:=rk35/rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin
endef
TFA_TARGETS:= \
rk3308 \
rk3308-rock-pi-s \
rk3566 \
rk3568 \
rk3568-e25
ifeq ($(BUILD_VARIANT),rk3308-rock-pi-s)
TPL_FILE:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin
define Download/rk3308-tpl-rock-pi-s
FILE:=$(TPL_FILE)
URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk33/
HASH:=8a1a42df23cccb86a2dabc14a5c0e9227d64a51b9b83e9968ef5af3b30787f7d
endef
define Build/Prepare
$(eval $(call Download,rk3308-tpl-rock-pi-s))
$(call Build/Prepare/Default)
$(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk33/
endef
endif
ifeq ($(BUILD_VARIANT),rk3568-e25)
TPL_FILE:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin
define Download/rk3568-tpl-e25
FILE:=$(TPL_FILE)
URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk35/
HASH:=1815f9649dc5661a3ef184b052da39286e51453a66f6ff53cc3e345d65dfabd4
endef
define Build/Prepare
$(eval $(call Download,rk3568-tpl-e25))
$(call Build/Prepare/Default)
$(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk35/
endef
endif
define Build/Compile
endef
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/
$(CP) $(PKG_BUILD_DIR)/bin/$(TPL) $(STAGING_DIR_IMAGE)/
endef
$(eval $(call BuildPackage/Trusted-Firmware-A))

184
package/boot/tfa-layerscape/Makefile Normal file
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@@ -0,0 +1,184 @@
#
# Copyright 2019 NXP
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=tfa-layerscape
PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/atf
PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
PKG_MIRROR_HASH:=28b731c1c4cc3226ccaef2142c61127f213c03cbd219df556c1d191e95f8470c
PKG_BUILD_DEPENDS:=tfa-layerscape/host
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/trusted-firmware-a.mk
include $(INCLUDE_DIR)/package.mk
HOST_CFLAGS += -Wall -Werror -pedantic -std=c99
define Host/Compile
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/fiptool \
PLAT_FIPTOOL_HELPER_MK="$(HOST_BUILD_DIR)/tools/nxp/plat_fiptool/plat_fiptool.mk" \
CFLAGS="$(HOST_CFLAGS)" \
LDFLAGS="$(HOST_LDFLAGS)" \
HOSTCCFLAGS="$(HOST_CFLAGS)"
$(MAKE) -C \
$(HOST_BUILD_DIR)/tools/nxp/create_pbl \
CFLAGS="$(HOST_CFLAGS)"
endef
define Host/Install
$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/fiptool-layerscape
$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/create_pbl/create_pbl $(STAGING_DIR_HOST)/bin/tfa-create-pbl
$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/create_pbl/byte_swap $(STAGING_DIR_HOST)/bin/tfa-byte-swap
endef
define Trusted-Firmware-A/Default
BUILD_TARGET:=layerscape
BUILD_SUBTARGET:=armv8_64b
DEPENDS:=+layerscape-rcw +u-boot-fsl_$(1)
endef
define Trusted-Firmware-A/ls1012a-frdm
NAME:=NXP LS1012AFRDM
PLAT:=ls1012afrdm
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1012a-rdb
NAME:=NXP LS1012ARDB
PLAT:=ls1012ardb
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1012a-frwy-sdboot
NAME:=NXP LS1012AFRWY
PLAT:=ls1012afrwy
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1028a-rdb
TITLE:=NXP LS1028ARDB
PLAT:=ls1028ardb
BOOT_MODE:=flexspi_nor
endef
define Trusted-Firmware-A/ls1028a-rdb-sdboot
TITLE:=NXP LS1028ARDB SD Boot
PLAT:=ls1028ardb
BOOT_MODE:=sd
endef
define Trusted-Firmware-A/ls1043a-rdb
NAME:=NXP LS1043ARDB
PLAT:=ls1043ardb
BOOT_MODE:=nor
endef
define Trusted-Firmware-A/ls1043a-rdb-sdboot
NAME:=NXP LS1043ARDB SD Boot
PLAT:=ls1043ardb
BOOT_MODE:=sd
endef
define Trusted-Firmware-A/ls1046a-frwy
NAME:=NXP LS1046AFRWY
PLAT:=ls1046afrwy
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1046a-frwy-sdboot
NAME:=NXP LS1046AFRWY SD Boot
PLAT:=ls1046afrwy
BOOT_MODE:=sd
endef
define Trusted-Firmware-A/ls1046a-rdb
NAME:=NXP LS1046ARDB
PLAT:=ls1046ardb
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1046a-rdb-sdboot
NAME:=NXP LS1046ARDB SD Boot
PLAT:=ls1046ardb
BOOT_MODE:=sd
endef
define Trusted-Firmware-A/ls1088a-rdb
NAME:=NXP LS1088ARDB
PLAT:=ls1088ardb
BOOT_MODE:=qspi
endef
define Trusted-Firmware-A/ls1088a-rdb-sdboot
NAME:=NXP LS1088ARDB SD Boot
PLAT:=ls1088ardb
BOOT_MODE:=sd
endef
define Trusted-Firmware-A/ls2088a-rdb
NAME:=NXP LS2088ARDB
PLAT:=ls2088ardb
BOOT_MODE:=nor
endef
define Trusted-Firmware-A/lx2160a-rdb
NAME:=NXP LX2160ARDB
PLAT:=lx2160ardb
BOOT_MODE:=flexspi_nor
endef
define Trusted-Firmware-A/lx2160a-rdb-sdboot
NAME:=NXP LX2160ARDB SD Boot
PLAT:=lx2160ardb
BOOT_MODE:=sd
endef
TFA_TARGETS := \
ls1012a-frdm \
ls1012a-rdb \
ls1012a-frwy-sdboot \
ls1028a-rdb \
ls1028a-rdb-sdboot \
ls1043a-rdb \
ls1043a-rdb-sdboot \
ls1046a-frwy \
ls1046a-frwy-sdboot \
ls1046a-rdb \
ls1046a-rdb-sdboot \
ls1088a-rdb \
ls1088a-rdb-sdboot \
ls2088a-rdb \
lx2160a-rdb \
lx2160a-rdb-sdboot
TFA_MAKE_FLAGS += \
fip pbl \
BOOT_MODE=$(BOOT_MODE) \
RCW=$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-rcw.bin \
BL33=$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-uboot.bin \
FIPTOOL=$(STAGING_DIR_HOST)/bin/fiptool-layerscape \
CREATE_PBL=$(STAGING_DIR_HOST)/bin/tfa-create-pbl \
BYTE_SWAP=$(STAGING_DIR_HOST)/bin/tfa-byte-swap
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2_$(BOOT_MODE).pbl \
$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-bl2.pbl
$(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/fip.bin \
$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-fip.bin
endef
define Package/trusted-firmware-a/install/default
endef
$(eval $(call HostBuild))
$(eval $(call BuildPackage/Trusted-Firmware-A))

106
package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch Normal file
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@@ -0,0 +1,106 @@
--- a/Makefile
+++ b/Makefile
@@ -953,10 +953,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$
ENCTOOLPATH ?= tools/encrypt_fw
ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT}
-# Variables for use with Firmware Image Package
-FIPTOOLPATH ?= tools/fiptool
-FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT}
-
# Variables for use with sptool
SPTOOLPATH ?= tools/sptool
SPTOOL ?= ${SPTOOLPATH}/sptool.py
@@ -1409,13 +1405,6 @@ endif
clean:
@echo " CLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_PLAT})
-ifdef UNIX_MK
- ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
-else
-# Clear the MAKEFLAGS as we do not want
-# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean
-endif
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
@@ -1424,13 +1413,6 @@ realclean distclean:
@echo " REALCLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_BASE})
$(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*)
-ifdef UNIX_MK
- ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
-else
-# Clear the MAKEFLAGS as we do not want
-# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean
-endif
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
@@ -1486,7 +1468,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL}
@${ECHO_BLANK_LINE}
endif
-${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL}
+${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS}
$(eval ${CHECK_FIP_CMD})
${Q}${FIPTOOL} create ${FIP_ARGS} $@
${Q}${FIPTOOL} info $@
@@ -1503,7 +1485,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT
@${ECHO_BLANK_LINE}
endif
-${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL}
+${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS}
$(eval ${CHECK_FWU_FIP_CMD})
${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@
${Q}${FIPTOOL} info $@
@@ -1511,19 +1493,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
-fiptool: ${FIPTOOL}
fip: ${BUILD_PLAT}/${FIP_NAME}
fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
-${FIPTOOL}: FORCE
-ifdef UNIX_MK
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all
-else
-# Clear the MAKEFLAGS as we do not want
-# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
-endif
-
romlib.bin: libraries FORCE
${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -67,7 +67,7 @@ all: ${PROJECT}
${PROJECT}: --openssl ${OBJECTS} Makefile
@echo " HOSTLD $@"
- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}
+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
--- a/tools/nxp/plat_fiptool/plat_fiptool.mk
+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk
@@ -22,11 +22,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C
$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
ifeq (${PLAT_DEF_OID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_OID
+override HOSTCCFLAGS += -DPLAT_DEF_OID
endif
ifeq (${PLAT_DEF_UUID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+override HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
endif

53
package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch Normal file
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@@ -0,0 +1,53 @@
From 8a458876013991fe2f288bbe4694264b16c3b9e9 Mon Sep 17 00:00:00 2001
From: Biwen Li <biwen.li@nxp.com>
Date: Fri, 26 Jul 2019 15:44:10 +0800
Subject: [PATCH 3/3] tools/nxp: fix create_pbl and byte_swap host build
Not compile create_pbl and byte_swap in the process of cross compilation
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
tools/nxp/pbl_ch2.mk | 3 ---
tools/nxp/pbl_ch3.mk | 5 -----
2 files changed, 8 deletions(-)
--- a/tools/nxp/create_pbl/pbl_ch2.mk
+++ b/tools/nxp/create_pbl/pbl_ch2.mk
@@ -19,8 +19,6 @@ ifeq ($(RCW),"")
else
# Generate header for bl2.bin
$(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
- # Compile create_pbl tool
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
# Add bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\
@@ -42,7 +40,6 @@ ifeq ($(RCW),"")
${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
# -a option appends the image for Chassis 3 devices in case of non secure boot
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;
# Swapping of RCW is required for QSPi Chassis 2 devices
--- a/tools/nxp/create_pbl/pbl_ch3.mk
+++ b/tools/nxp/create_pbl/pbl_ch3.mk
@@ -26,9 +26,6 @@ else
# Generate header for bl2.bin
$(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
- # Compile create_pbl tool
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
-
# Add Block Copy command for bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};\
@@ -56,8 +53,6 @@ else #SECURE_BOOT
ifeq ($(RCW),"")
${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
-
# Add Block Copy command and populate boot loc ptrfor bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};

205
package/boot/tfa-layerscape/patches/004-plat-nxp-restore-ls1012afrdm-support.patch Normal file
View File

@@ -0,0 +1,205 @@
From 8c6a66feb721f18c930c7df03d1fbb7304107af6 Mon Sep 17 00:00:00 2001
From: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch>
Date: Thu, 20 Apr 2023 16:21:25 +0200
Subject: [PATCH] tfa-layerscape: Restore ls1012afrdm support
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch>
---
plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c | 34 +++++++
plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 83 +++++++++++++++++++
plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk | 25 +++++
.../soc-ls1012a/ls1012afrdm/platform_def.h | 13 +++
plat/nxp/soc-ls1012a/ls1012afrdm/policy.h | 16 ++++
5 files changed, 180 insertions(+)
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <fsl_mmdc.h>
+
+#include <platform_def.h>
+
+long long init_ddr(void)
+{
+ static const struct fsl_mmdc_info mparam = {
+ .mdctl = U(0x04180000),
+ .mdpdc = U(0x00030035),
+ .mdotc = U(0x12554000),
+ .mdcfg0 = U(0xbabf7954),
+ .mdcfg1 = U(0xdb328f64),
+ .mdcfg2 = U(0x01ff00db),
+ .mdmisc = U(0x00001680),
+ .mdref = U(0x0f3c8000),
+ .mdrwd = U(0x00002000),
+ .mdor = U(0x00bf1023),
+ .mdasp = U(0x0000003f),
+ .mpodtctrl = U(0x0000022a),
+ .mpzqhwctrl = U(0xa1390003),
+ };
+
+ mmdc_init(&mparam, NXP_DDR_ADDR);
+ NOTICE("DDR Init Done\n");
+
+ return NXP_DRAM0_SIZE;
+}
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+#include <policy.h>
+#include <soc.h>
+
+/* DDR Related definition */
+#define PLAT_DEF_DRAM0_SIZE 0x20000000 /* 512 MB */
+
+#define NXP_SYSCLK_FREQ 125000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+#define NXP_SPD_EEPROM0 0x51
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
+#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
+
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 3
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 2
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 1
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2018-2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+BOOT_MODE := qspi
+BOARD := ls1012afrdm
+
+# DDR Compilation Configs
+DDRC_NUM_CS := 1
+
+# On-Board Flash Details
+QSPI_FLASH_SZ := 0x4000000
+
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c
+
+SUPPORTED_BOOT_MODE := qspi
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1012a/soc.mk
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/*
+ * Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x0
+
+#endif /* POLICY_H */

36
package/boot/uboot-armsr/Makefile Normal file
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@@ -0,0 +1,36 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2023.04
PKG_RELEASE:=1
PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=armsr
endef
define U-Boot/qemu_armv7
NAME:=QEMU ARM Virtual Machine 32-bit
BUILD_SUBTARGET:=armv7
BUILD_DEVICES:=generic
UBOOT_CONFIG:=qemu_arm
endef
define U-Boot/qemu_armv8
NAME:=QEMU ARM Virtual Machine 64-bit
BUILD_SUBTARGET:=armv8
BUILD_DEVICES:=generic
UBOOT_CONFIG:=qemu_arm64
endef
UBOOT_TARGETS := \
qemu_armv7 \
qemu_armv8
UBOOT_CUSTOMIZE_CONFIG := \
--enable CMD_EFIDEBUG
$(eval $(call BuildPackage/U-Boot))

62
package/boot/uboot-armsr/patches/001-v2023.07-bootstd-Use-blk-uclass-device-numbers-to-set-efi-bootdev.patch Normal file
View File

@@ -0,0 +1,62 @@
From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Subject: [PATCH v10 7/9] bootstd: Use blk uclass device numbers to set efi
bootdev
Date: Mon, 24 Apr 2023 13:49:50 +1200
Message-ID:
<20230424134946.v10.7.Ia5f5e39c882ac22b5f71c4d576941b34e868eeba@changeid>
From: Mathew McBride <matt@traverse.com.au>
When loading a file from a block device, efiload_read_file
was using the seq_num of the device (e.g "35" of virtio_blk#35)
instead of the block device id (e.g what you get from running
the corresponding device scan command, like "virtio 0")
This cause EFI booting from these devices to fail as an
invalid device number is passed to blk_get_device_part_str:
Scanning bootdev 'virtio-blk#35.bootdev':
distro_efi_read_bootflow_file start (efi,fname=<NULL>)
distro_efi_read_bootflow_file start (efi,fname=<NULL>)
setting bootdev virtio, 35, efi/boot/bootaa64.efi, 00000000beef9a40, 170800
efi_dp_from_name calling blk_get_device_part_str
dev=virtio devnr=35 path=efi/boot/bootaa64.efi
blk_get_device_part_str (virtio,35)
blk_get_device_by_str (virtio, 35)
** Bad device specification virtio 35 **
Using default device tree: dtb/qemu-arm.dtb
No device tree available
0 efi ready virtio 1 virtio-blk#35.bootdev.par efi/boot/bootaa64.efi
** Booting bootflow 'virtio-blk#35.bootdev.part_1' with efi
blk_get_device_part_str (virtio,0:1)
blk_get_device_by_str (virtio, 0)
No UEFI binary known at beef9a40 (image buf=00000000beef9a40,addr=0000000000000000)
Boot failed (err=-22)
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [backport to 2023.04]
---
(no changes since v8)
Changes in v8:
- Add new patch to use blk uclass device numbers to set efi bootdev
boot/bootmeth_efi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -117,7 +117,9 @@ static int efiload_read_file(struct blk_
* this can go away.
*/
media_dev = dev_get_parent(bflow->dev);
- snprintf(devnum_str, sizeof(devnum_str), "%x", dev_seq(media_dev));
+ snprintf(devnum_str, sizeof(devnum_str), "%x:%x",
+ desc ? desc->devnum : dev_seq(media_dev),
+ bflow->part);
strlcpy(dirname, bflow->fname, sizeof(dirname));
last_slash = strrchr(dirname, '/');

182
package/boot/uboot-at91/Makefile Normal file
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@@ -0,0 +1,182 @@
#
# Copyright (C) 2016 Ben Whitten <ben.whitten@gmail.com>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_VERSION:=linux4sam-2022.04
PKG_RELEASE:=3
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/linux4sam/u-boot-at91.git
PKG_MIRROR_HASH:=82229503800d9a624bb8de5f8d7a84cb35fd512a1550c6f1d46958cd47d4807b
PKG_SOURCE_VERSION:=7b59654a486d39dc8e0343e2554699b8a79c7a54
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/kernel.mk
define U-Boot/Default
BUILD_TARGET:=at91
HIDDEN:=1
UBOOT_IMAGE:=u-boot.bin
endef
define U-Boot/at91sam9m10g45ek_nandflash
NAME:=AT91SAM9M10G45-EK board (NandFlash)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=atmel_at91sam9m10g45ek
endef
define U-Boot/at91sam9x5ek_nandflash
NAME:=AT91SAM9X5-EK board (NandFlash)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=atmel_at91sam9g15ek atmel_at91sam9g25ek \
atmel_at91sam9g35ek atmel_at91sam9x25ek \
atmel_at91sam9x35ek
endef
define U-Boot/at91sam9x5ek_mmc
NAME:=AT91SAM9X5-EK board (SDcard)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=atmel_at91sam9g15ek atmel_at91sam9g25ek \
atmel_at91sam9g35ek atmel_at91sam9x25ek \
atmel_at91sam9x35ek
endef
define U-Boot/sam9x60ek_nandflash
NAME:=SAM9X60-EK board (NandFlash)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=microchip_sam9x60ek
endef
define U-Boot/sam9x60ek_mmc
NAME:=SAM9X60-EK board (SDcard)
BUILD_SUBTARGET:=sam9x
BUILD_DEVICES:=microchip_sam9x60ek
endef
define U-Boot/sama5d3_xplained_nandflash
NAME:=SAMA5D3 Xplained board (NandFlash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define U-Boot/sama5d3_xplained_mmc
NAME:=SAMA5D3 Xplained board (SDcard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define U-Boot/sama5d2_icp_mmc
NAME:=SAMA5D2 ICP board (SDCard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-icp
endef
define U-Boot/sama5d2_xplained_spiflash
NAME:=SAMA5D2 Xplained board (SPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-xplained
endef
define U-Boot/sama5d2_xplained_mmc
NAME:=SAMA5D2 Xplained board (SDcard/EMMC)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-xplained
endef
define U-Boot/sama5d4_xplained_spiflash
NAME:=SAMA5D4 Xplained board (SPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d4-xplained
endef
define U-Boot/sama5d4_xplained_mmc
NAME:=SAMA5D4 Xplained board (SDcard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d4-xplained
endef
define U-Boot/sama5d4_xplained_nandflash
NAME:=SAMA5D4 Xplained board (NandFlash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d3-xplained
endef
define U-Boot/sama5d27_som1_ek_mmc
NAME:=SAMA5D27 SOM1 Ek (SDCard0)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define U-Boot/sama5d27_som1_ek_qspiflash
NAME:=SAMA5D27 SOM1 Ek (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-som1-ek
endef
define U-Boot/sama5d27_wlsom1_ek_mmc
NAME:=SAMA5D27 WLSOM1 Ek (SDCard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek
endef
define U-Boot/sama5d27_wlsom1_ek_qspiflash
NAME:=SAMA5D27 WLSOM1 Ek (QSPI Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek
endef
define U-Boot/sama5d2_ptc_ek_nandflash
NAME:=SAMA5D2 PTC Ek (Nand Flash)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-ptc-ek
endef
define U-Boot/sama5d2_ptc_ek_mmc
NAME:=SAMA5D2 PTC Ek (SDCard)
BUILD_SUBTARGET:=sama5
BUILD_DEVICES:=microchip_sama5d2-ptc-ek
endef
define U-Boot/sama7g5ek_mmc1
NAME:=SAMA7G5-EK (SDCard)
BUILD_SUBTARGET:=sama7
BUILD_DEVICES:=microchip_sama7g5-ek
endef
UBOOT_TARGETS := \
at91sam9m10g45ek_nandflash \
at91sam9x5ek_nandflash \
at91sam9x5ek_mmc \
sam9x60ek_nandflash \
sam9x60ek_mmc \
sama5d3_xplained_nandflash \
sama5d3_xplained_mmc \
sama5d2_icp_mmc \
sama5d2_xplained_mmc \
sama5d2_xplained_spiflash \
sama5d4_xplained_mmc \
sama5d4_xplained_spiflash \
sama5d4_xplained_nandflash\
sama5d27_som1_ek_mmc \
sama5d27_som1_ek_qspiflash \
sama5d27_wlsom1_ek_mmc \
sama5d27_wlsom1_ek_qspiflash \
sama5d2_ptc_ek_nandflash \
sama5d2_ptc_ek_mmc \
sama7g5ek_mmc1
define Build/Compile
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
CROSS_COMPILE=$(TARGET_CROSS) \
KCFLAGS="$(filter-out -fstack-protector \
-mfloat-abi=hard, $(TARGET_CFLAGS)) -mfloat-abi=soft" \
$(UBOOT_MAKE_FLAGS)
endef
$(eval $(call BuildPackage/U-Boot))

45
package/boot/uboot-at91/patches/001-fix-Wformat-security.patch Normal file
View File

@@ -0,0 +1,45 @@
From 3b05406c02070df3e7f19399d81ebd35ed6deae5 Mon Sep 17 00:00:00 2001
From: Claudiu Beznea <claudiu.beznea@microchip.com>
Date: Tue, 12 Oct 2021 17:43:28 +0300
Subject: [PATCH] fix -Wformat-security
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
cmd/panic.c | 2 +-
cmd/version.c | 2 +-
drivers/pinctrl/pinctrl-uclass.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
--- a/cmd/panic.c
+++ b/cmd/panic.c
@@ -11,7 +11,7 @@ static int do_panic(struct cmd_tbl *cmdt
{
char *text = (argc < 2) ? "" : argv[1];
- panic(text);
+ panic("%s\n", text);
return CMD_RET_SUCCESS;
}
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -24,7 +24,7 @@ static int do_version(struct cmd_tbl *cm
{
char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
- printf(display_options_get_banner(false, buf, sizeof(buf)));
+ printf("%s", display_options_get_banner(false, buf, sizeof(buf)));
#ifdef CC_VERSION_STRING
puts(CC_VERSION_STRING "\n");
#endif
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -375,7 +375,7 @@ int pinctrl_get_pin_name(struct udevice
if (!ops->get_pin_name)
return -ENOSYS;
- snprintf(buf, size, ops->get_pin_name(dev, selector));
+ snprintf(buf, size, "%s", ops->get_pin_name(dev, selector));
return 0;
}

56
package/boot/uboot-bcm4908/Makefile Normal file
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@@ -0,0 +1,56 @@
# SPDX-License-Identifier: GPL-2.0-or-later
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://git.openwrt.org/project/bcm63xx/u-boot.git
PKG_SOURCE_DATE:=2022-12-08
PKG_SOURCE_VERSION:=4435700d18a791dca0d8d767e5414dfac9df4451
PKG_MIRROR_HASH:=80de483c11938cca9fdd0f35931cce1921c8166d9c1c146da56bf155394842cb
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=bcm4908
UBOOT_IMAGE:=u-boot-nodtb.bin
DEFAULT:=y
endef
define U-Boot/bcm4908
NAME:=Broadcom's BCM4908
UBOOT_CONFIG:=bcm94908
SOC:=bcm4908
endef
define U-Boot/bcm4912
NAME:=Broadcom's BCM4912
UBOOT_CONFIG:=bcm94912
SOC:=bcm4912
endef
UBOOT_TARGETS := \
bcm4908 \
bcm4912
define Build/Prepare
$(call Build/Prepare/Default)
mkdir -p $(PKG_BUILD_DIR)/include/generated/
( cd $(PKG_BUILD_DIR)/board/broadcom/bcmbca/httpd/html/ && \
$(STAGING_DIR_HOST)/bin/xxd -i index.html > ../../../../../include/generated/index.h && \
$(STAGING_DIR_HOST)/bin/xxd -i flashing.html > ../../../../../include/generated/flashing.h && \
$(STAGING_DIR_HOST)/bin/xxd -i fail.html > ../../../../../include/generated/fail.h && \
$(STAGING_DIR_HOST)/bin/xxd -i 404.html > ../../../../../include/generated/404.h )
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/u-boot
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/u-boot/u-boot-$(SOC).bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/u-boot.dtb $(STAGING_DIR_IMAGE)/u-boot/u-boot-$(SOC).dtb
$(INSTALL_BIN) $(PKG_BUILD_DIR)/arch/arm/dts/*.dtb $(STAGING_DIR_IMAGE)/u-boot/
endef
$(eval $(call BuildPackage/U-Boot))

40
package/boot/uboot-bcm4908/patches/100-check-config-allow-to-complete-build-even-with-ad-ho.patch Normal file
View File

@@ -0,0 +1,40 @@
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 26 Sep 2016 13:05:02 +0900
Subject: [PATCH] check-config: allow to complete build even with ad-hoc CONFIG
options
Currently, the check-config.sh terminates the build when unknown
ad-hoc options are detected. I think it is too much because we may
want to patch config headers locally in a build/deployment project.
So, let's relax check-config.sh to just warn even if it detects
options that are not in the whitelist. Instead, this check can be
done at the end of build, along with other checks. It will catch
more attention.
Even with this change, the Buildman tool catches new warnings,
so Tom can give NACK to new ad-hoc options.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
scripts/check-config.sh | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -50,14 +50,13 @@ cat `find ${srctree} -name "Kconfig*"` |
|sort |uniq > ${ok}
comm -23 ${suspects} ${ok} >${new_adhoc}
if [ -s ${new_adhoc} ]; then
- echo >&2 "Error: You must add new CONFIG options using Kconfig"
+ echo >&2 "Warning: You must add new CONFIG options using Kconfig"
echo >&2 "The following new ad-hoc CONFIG options were detected:"
cat >&2 ${new_adhoc}
echo >&2
echo >&2 "Please add these via Kconfig instead. Find a suitable Kconfig"
echo >&2 "file and add a 'config' or 'menuconfig' option."
# Don't delete the temporary files in case they are useful
- exit 1
else
rm ${suspects} ${ok} ${new_adhoc}
fi

50
package/boot/uboot-bcm4908/patches/200-configs-bcm94908-unset-CONFIG_SPL.patch Normal file
View File

@@ -0,0 +1,50 @@
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Fri, 4 Mar 2022 09:21:32 +0100
Subject: [PATCH] configs: bcm94908: unset CONFIG_SPL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Compiling SPL is always tricky as it needs to fit limited resources.
Fortunately in most cases there is no need to replace SPL or TPL while
flashing a new firmware.
Compiling SPL for BCM4908 seems to fail with non-Broadcom toolchain:
aarch64-openwrt-linux-musl-ld.bfd: u-boot-spl section `.u_boot_list' will not fit in region `.sram'
aarch64-openwrt-linux-musl-ld.bfd: section .bss VMA [00000000822b9000,00000000822b93ef] overlaps section .u_boot_list VMA [00000000822b8f60,00000000822b9a87]
aarch64-openwrt-linux-musl-ld.bfd: region `.sram' overflowed by 2696 bytes
It also requires hashtable.h which has to be generated using some
Broadcom's custom perl script that isn't integrated as this point.
For now just disable SPL and use only last-stage U-Boot that must be
shipped with every firmware.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
configs/bcm94908_defconfig | 2 +-
configs/bcm94912_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/configs/bcm94908_defconfig
+++ b/configs/bcm94908_defconfig
@@ -21,7 +21,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
+# CONFIG_SPL is not set
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x11000
--- a/configs/bcm94912_defconfig
+++ b/configs/bcm94912_defconfig
@@ -22,7 +22,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
+# CONFIG_SPL is not set
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000

67
package/boot/uboot-bcm4908/patches/201-Assume-TPL-support-for-ATF-when-compiling-U-Boot-wit.patch Normal file
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@@ -0,0 +1,67 @@
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Fri, 4 Mar 2022 09:23:34 +0100
Subject: [PATCH] Assume TPL support for ATF when compiling U-Boot without TPL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Broadcom's U-Boot behaviour depends on compilation time check whether
TPL was compiled with or without ATF support. There is no proper runtime
check.
When compiling just U-Boot (without SPL & TPL) there is no way to tell
if it's going to work with TPL with or without ATF support.
Modify code to blindly assume ATF support in TPL in such cases. It seems
to be always true for Broadcom and we need some assumption as we don't
deal with compiling SPL or TPL.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
arch/arm/mach-bcmbca/bcm4908/cpu.c | 2 +-
arch/arm/mach-bcmbca/bcm4912/cpu.c | 2 +-
board/broadcom/bcmbca/board.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm/mach-bcmbca/bcm4908/cpu.c
+++ b/arch/arm/mach-bcmbca/bcm4908/cpu.c
@@ -138,7 +138,7 @@ int get_nr_cpus()
return nr_cpus;
}
-#if !defined(CONFIG_TPL_ATF)
+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)
void boot_secondary_cpu(unsigned long vector)
{
uint32_t cpu, nr_cpus = QUAD_CPUS;
--- a/arch/arm/mach-bcmbca/bcm4912/cpu.c
+++ b/arch/arm/mach-bcmbca/bcm4912/cpu.c
@@ -174,7 +174,7 @@ int bcmbca_get_boot_device(void)
return BOOT_DEVICE_NONE;
}
-#if !defined(CONFIG_TPL_ATF)
+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)
void boot_secondary_cpu(unsigned long vector)
{
uint32_t cpu, nr_cpus = 4;
--- a/board/broadcom/bcmbca/board.c
+++ b/board/broadcom/bcmbca/board.c
@@ -103,7 +103,7 @@ void board_spinor_init(void)
int board_init(void)
{
-#if !defined(CONFIG_TPL_ATF)
+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)
unsigned long vector;
#endif
board_sdk_init_e();
@@ -121,7 +121,7 @@ int board_init(void)
printf("$Uboot: "BUILD_TAG" $\n");
#endif
-#if !defined(CONFIG_TPL_ATF)
+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)
#if defined(CONFIG_ARM64)
vector = (unsigned long)&_start;
#else

37
package/boot/uboot-bcm53xx/Makefile Normal file
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@@ -0,0 +1,37 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2024.01
PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
PKG_RELEASE:=$(AUTORELEASE)
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=bcm53xx
BUILD_SUBTARGET:=generic
UBOOT_CONFIG:=bcmns
UBOOT_BOARD:=$(1)
endef
define U-Boot/dir-885l
NAME:=D-Link DIR-885L
BUILD_DEVICES:=dlink_dir-885l
endef
define U-Boot/dir-890l
NAME:=D-Link DIR-890L
BUILD_DEVICES:=dlink_dir-890l
endef
UBOOT_TARGETS := dir-885l dir-890l
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.bin
endef
define Package/u-boot/install/default
endef
$(eval $(call BuildPackage/U-Boot))

32
package/boot/uboot-bmips/Makefile Normal file
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@@ -0,0 +1,32 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2024.04
PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
PKG_RELEASE:=$(AUTORELEASE)
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=bmips
BUILD_SUBTARGET:=bcm6328
UBOOT_CONFIG:=inteno_xg6846_ram
UBOOT_BOARD:=$(1)
endef
define U-Boot/xg6846
NAME:=Inteno XG6846
BUILD_DEVICES:=inteno_xg6846
endef
UBOOT_TARGETS := xg6846
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.bin
endef
define Package/u-boot/install/default
endef
$(eval $(call BuildPackage/U-Boot))

85
package/boot/uboot-d1/Makefile Normal file
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@@ -0,0 +1,85 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2023 OpenWrt.org
#
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2023.01
PKG_RELEASE:=1
PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=d1
BUILD_SUBTARGET:=generic
UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin
UENV:=default
DTS_DIR:=arch/riscv/dts
endef
define U-Boot/dongshan_nezha_stu
NAME:=Dongshan Nezha STU
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=sun20i-d1-dongshan-nezha-stu.dtb
BUILD_DEVICES:=dongshan_nezha_stu
endef
define U-Boot/lichee_rv_dock
NAME:=LicheePi RV (dock)
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=sun20i-d1-lichee-rv-dock.dtb
BUILD_DEVICES:=lichee_rv_dock
endef
define U-Boot/mangopi_mq_pro
NAME:=MangoPi MQ Pro
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=sun20i-d1-mangopi-mq-pro.dtb
BUILD_DEVICES:=mangopi_mq_pro
endef
define U-Boot/nezha
NAME:=Nezha D1
OPENSBI:=generic
DEPENDS:=+opensbi_generic
UBOOT_DTS:=sun20i-d1-nezha.dtb
BUILD_DEVICES:=nezha
endef
UBOOT_TARGETS := \
dongshan_nezha_stu \
lichee_rv_dock \
mangopi_mq_pro \
nezha \
UBOOT_MAKE_FLAGS += \
OPENSBI=$(STAGING_DIR_IMAGE)/fw_dynamic-${OPENSBI}.bin
define Build/Configure
$(call Build/Configure/U-Boot)
sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)
mkimage -C none -A riscv -T script -d uEnv-$(UENV).txt \
$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
endef
define Package/u-boot/install/default
endef
$(eval $(call BuildPackage/U-Boot))

197
package/boot/uboot-d1/patches/0001-ARM-dts-sun8i-A33-Add-iNet-U70B-REV01.patch Normal file
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@@ -0,0 +1,197 @@
From d45e64aad18e5e324425b9efbe6a0ec9e1a343da Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 20 Nov 2021 13:19:13 -0600
Subject: [PATCH 01/90] ARM: dts: sun8i: A33: Add iNet U70B REV01
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 172 ++++++++++++++++++++++
2 files changed, 173 insertions(+)
create mode 100644 arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -644,6 +644,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-inet-d978-rev2.dtb \
+ sun8i-a33-inet-u70b-rev1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+
+/dts-v1/;
+
+#include "sun8i-a33.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
+
+/ {
+ model = "iNet U70B REV01";
+ compatible = "inet-tek,inet-u70b-rev01", "allwinner,sun8i-a33";
+
+ aliases {
+ ethernet0 = &rtl8723cs;
+ };
+
+ panel: panel {
+ compatible = "panel-dpi";
+ backlight = <&backlight>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <&reg_dc1sw>;
+
+ panel-timing {
+ clock-frequency = <51000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <162>;
+ hback-porch = <158>;
+ hsync-len = <20>;
+ vback-porch = <25>;
+ vfront-porch = <10>;
+ vsync-len = <3>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+
+ port {
+ panel_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_panel>;
+ };
+ };
+ };
+
+ speaker_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&dai {
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ accelerometer@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ };
+};
+
+&mmc1 {
+ pinctrl-0 = <&mmc1_pg_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <&reg_dldo1>;
+ vqmmc-supply = <&reg_dldo2>;
+ status = "okay";
+
+ rtl8723cs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+ };
+};
+
+&nfc {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-maximize;
+ };
+};
+
+&r_uart {
+ status = "disabled";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&simplefb_lcd {
+ status = "okay";
+};
+
+&sound {
+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ simple-audio-card,widgets = "Headphone", "Headphone Jack",
+ "Microphone", "Internal Microphone",
+ "Speaker", "Internal Speaker";
+ simple-audio-card,routing = "Headphone Jack", "HP",
+ "Internal Speaker", "Speaker Amp OUTL",
+ "Internal Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HP", /* PHONEOUT ??? */
+ "Speaker Amp INR", "HP", /* PHONEOUT ??? */
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
+ "ADCL", "Left ADC",
+ "ADCR", "Right ADC",
+ "MIC1", "Internal Microphone",
+ "MIC2", "Headset Microphone",
+ "Headset Microphone", "HBIAS",
+ "Internal Microphone", "MBIAS";
+ status = "okay";
+};
+
+&tcon0 {
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_panel: endpoint {
+ remote-endpoint = <&panel_in_tcon0>;
+ };
+};
+
+&touchscreen {
+ reg = <0x40>;
+ compatible = "silead,gsl1680";
+ avdd-supply = <&reg_ldo_io1>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723cs-bt";
+ device-wake-gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
+ enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ host-wake-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ };
+};

46
package/boot/uboot-d1/patches/0002-sunxi-Add-iNet_U70B_rev1_defconfig.patch Normal file
View File

@@ -0,0 +1,46 @@
From ddb1f06d1c7758c538e286c0c7a9c8545d2af6b1 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 20 Nov 2021 13:26:36 -0600
Subject: [PATCH 02/90] sunxi: Add iNet_U70B_rev1_defconfig
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
configs/iNet_U70B_rev1_defconfig | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 configs/iNet_U70B_rev1_defconfig
--- /dev/null
+++ b/configs/iNet_U70B_rev1_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
+# CONFIG_SPL_SERIAL is not set
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=31675
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_NET is not set
+CONFIG_AXP_GPIO=y
+CONFIG_REGULATOR_AXP=y
+CONFIG_REGULATOR_AXP_USB_POWER=y
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_USB_MUSB_HOST=y

85
package/boot/uboot-d1/patches/0003-Adapt-iNet-U70B-REV01-for-development-FEL-serial.patch Normal file
View File

@@ -0,0 +1,85 @@
From ef808412055d1ef6fe77ff130d3f5a9432fef2d7 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Tue, 3 May 2022 22:35:12 -0500
Subject: [PATCH 03/90] Adapt iNet U70B REV01 for development (FEL + serial)
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 11 +++++++++++
configs/iNet_U70B_rev1_defconfig | 14 +++++---------
2 files changed, 16 insertions(+), 9 deletions(-)
--- a/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
@@ -11,6 +11,7 @@
aliases {
ethernet0 = &rtl8723cs;
+ serial0 = &uart0;
};
panel: panel {
@@ -76,6 +77,10 @@
};
};
+&mmc0 {
+ status = "disabled";
+};
+
&mmc1 {
pinctrl-0 = <&mmc1_pg_pins>;
pinctrl-names = "default";
@@ -158,6 +163,12 @@
status = "okay";
};
+&uart0 {
+ pinctrl-0 = <&uart0_pf_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&uart1 {
pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
pinctrl-names = "default";
--- a/configs/iNet_U70B_rev1_defconfig
+++ b/configs/iNet_U70B_rev1_defconfig
@@ -1,12 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
-# CONFIG_SPL_SERIAL is not set
CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=31675
CONFIG_DRAM_ODT_EN=y
+CONFIG_UART0_PORT_F=y
CONFIG_MMC0_CD_PIN="PB4"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
@@ -14,19 +14,15 @@ CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CMD_BIND=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_PWM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_WDT=y
+CONFIG_PREBOOT="fastboot usb 0"
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-# CONFIG_NET is not set
CONFIG_AXP_GPIO=y
CONFIG_REGULATOR_AXP=y
CONFIG_REGULATOR_AXP_USB_POWER=y
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
-# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
-CONFIG_USB_MUSB_HOST=y
+CONFIG_REMOTEPROC_SUN6I_AR100=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_WATCHDOG_AUTOSTART=y

54
package/boot/uboot-d1/patches/0004-ARM-dts-sun6i-mixtile-loftq-Add-USB1-VBUS-regulator.patch Normal file
View File

@@ -0,0 +1,54 @@
From 40a0ec0fdb6a110d69151de5480148772877f267 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 20:39:33 -0500
Subject: [PATCH 04/90] ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.
Update the device tree here because it does not exist in Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
+++ b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
@@ -6,6 +6,9 @@
*/
/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
#include "sun6i-a31.dtsi"
/ {
@@ -19,6 +22,15 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+ };
};
&ehci0 {
@@ -56,3 +68,8 @@
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};

97
package/boot/uboot-d1/patches/0005-power-regulator-Add-a-driver-for-the-AXP-USB-power-s.patch Normal file
View File

@@ -0,0 +1,97 @@
From e07c1d516c1a7842510d22a7cf88666d500a9a9a Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 22 Aug 2021 21:35:45 -0500
Subject: [PATCH 05/90] power: regulator: Add a driver for the AXP USB power
supply
This driver reports the presence/absence of voltage on the PMIC's USB
VBUS pin. This information is used by the USB PHY driver. The
corresponding Linux driver uses the power supply class, which does not
exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/power/regulator/Kconfig | 7 ++++
drivers/power/regulator/Makefile | 1 +
drivers/power/regulator/axp_usb_power.c | 49 +++++++++++++++++++++++++
3 files changed, 57 insertions(+)
create mode 100644 drivers/power/regulator/axp_usb_power.c
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -43,6 +43,13 @@ config REGULATOR_AS3722
but does not yet support change voltages. Currently this must be
done using direct register writes to the PMIC.
+config REGULATOR_AXP_USB_POWER
+ bool "Enable driver for X-Powers AXP PMIC USB power supply"
+ depends on DM_REGULATOR && PMIC_AXP
+ help
+ Enable support for reading the USB power supply status from
+ X-Powers AXP2xx and AXP8xx PMICs.
+
config DM_REGULATOR_BD71837
bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
depends on DM_REGULATOR && DM_PMIC_BD71837
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
+obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
--- /dev/null
+++ b/drivers/power/regulator/axp_usb_power.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm/device.h>
+#include <errno.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
+
+static int axp_usb_power_get_enable(struct udevice *dev)
+{
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS);
+ if (ret < 0)
+ return ret;
+
+ return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT);
+}
+
+static const struct dm_regulator_ops axp_usb_power_ops = {
+ .get_enable = axp_usb_power_get_enable,
+};
+
+static int axp_usb_power_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ uc_plat->type = REGULATOR_TYPE_FIXED;
+
+ return 0;
+}
+
+static const struct udevice_id axp_usb_power_ids[] = {
+ { .compatible = "x-powers,axp202-usb-power-supply" },
+ { .compatible = "x-powers,axp221-usb-power-supply" },
+ { .compatible = "x-powers,axp223-usb-power-supply" },
+ { .compatible = "x-powers,axp813-usb-power-supply" },
+ { }
+};
+
+U_BOOT_DRIVER(axp_usb_power) = {
+ .name = "axp_usb_power",
+ .id = UCLASS_REGULATOR,
+ .of_match = axp_usb_power_ids,
+ .probe = axp_usb_power_probe,
+ .ops = &axp_usb_power_ops,
+};

122
package/boot/uboot-d1/patches/0006-gpio-axp-sunxi-Remove-virtual-VBUS-detection-GPIO.patch Normal file
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@@ -0,0 +1,122 @@
From c750151e1107a8d46ca0f9bd30c1da276b142ec1 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 18:02:54 -0500
Subject: [PATCH 06/90] gpio: axp/sunxi: Remove virtual VBUS detection GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
drivers/gpio/axp_gpio.c | 21 ++++-----------------
drivers/gpio/sunxi_gpio.c | 6 +-----
include/axp209.h | 1 -
include/axp221.h | 1 -
include/axp809.h | 1 -
include/axp818.h | 1 -
7 files changed, 5 insertions(+), 27 deletions(-)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -209,7 +209,6 @@ enum sunxi_gpio_number {
/* Virtual AXP0 GPIOs */
#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_DETECT 4
#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -36,18 +36,11 @@ static int axp_gpio_direction_input(stru
{
u8 reg;
- switch (pin) {
-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
- case SUNXI_GPIO_AXP0_VBUS_DETECT:
- return 0;
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
- }
+ return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
}
static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
@@ -83,12 +76,6 @@ static int axp_gpio_get_value(struct ude
int ret;
switch (pin) {
-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
- case SUNXI_GPIO_AXP0_VBUS_DETECT:
- ret = pmic_bus_read(AXP_POWER_STATUS, &val);
- mask = AXP_POWER_STATUS_VBUS_PRESENT;
- break;
-#endif
#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
/* Only available on later PMICs */
case SUNXI_GPIO_AXP0_VBUS_ENABLE:
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -117,11 +117,7 @@ int sunxi_name_to_gpio(const char *name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
char lookup[8];
- if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
- SUNXI_GPIO_AXP0_VBUS_DETECT);
- name = lookup;
- } else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+ if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
SUNXI_GPIO_AXP0_VBUS_ENABLE);
name = lookup;
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -77,7 +77,6 @@ enum axp209_reg {
#ifdef CONFIG_AXP209_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO2_CTRL 0x93
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,7 +53,6 @@
#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,7 +47,6 @@
#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,7 +61,6 @@
#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f

111
package/boot/uboot-d1/patches/0007-power-regulator-Add-a-driver-for-the-AXP-PMIC-drivev.patch Normal file
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@@ -0,0 +1,111 @@
From 25434a394705d2de92c50981e31347db4074204a Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 21:32:15 -0500
Subject: [PATCH 07/90] power: regulator: Add a driver for the AXP PMIC
drivevbus
The first AXP regulator converted to use the regulator uclass is the
drivevbus switch, since it is used by the USB PHY driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/power/regulator/Kconfig | 14 ++++++
drivers/power/regulator/Makefile | 1 +
drivers/power/regulator/axp_regulator.c | 58 +++++++++++++++++++++++++
3 files changed, 73 insertions(+)
create mode 100644 drivers/power/regulator/axp_regulator.c
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -43,6 +43,20 @@ config REGULATOR_AS3722
but does not yet support change voltages. Currently this must be
done using direct register writes to the PMIC.
+config REGULATOR_AXP
+ bool "Enable driver for X-Powers AXP PMIC regulators"
+ depends on DM_REGULATOR && PMIC_AXP
+ help
+ Enable support for the regulators (DCDCs, LDOs) in the
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
+config SPL_REGULATOR_AXP
+ bool "Enable driver for X-Powers AXP PMIC regulators in SPL"
+ depends on SPL_DM_REGULATOR && SPL_PMIC_AXP
+ help
+ Enable support in SPL for the regulators (DCDCs, LDOs) in the
+ X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+
config REGULATOR_AXP_USB_POWER
bool "Enable driver for X-Powers AXP PMIC USB power supply"
depends on DM_REGULATOR && PMIC_AXP
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
+obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
--- /dev/null
+++ b/drivers/power/regulator/axp_regulator.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <errno.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define AXP_VBUS_IPSOUT 0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS BIT(2)
+#define AXP_MISC_CTRL 0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC BIT(4)
+
+static int axp_drivevbus_get_enable(struct udevice *dev)
+{
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT);
+ if (ret < 0)
+ return ret;
+
+ return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS);
+}
+
+static int axp_drivevbus_set_enable(struct udevice *dev, bool enable)
+{
+ return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT,
+ AXP_VBUS_IPSOUT_DRIVEBUS,
+ enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0);
+}
+
+static const struct dm_regulator_ops axp_drivevbus_ops = {
+ .get_enable = axp_drivevbus_get_enable,
+ .set_enable = axp_drivevbus_set_enable,
+};
+
+static int axp_drivevbus_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
+ int ret;
+
+ uc_plat->type = REGULATOR_TYPE_FIXED;
+
+ if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) {
+ ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL,
+ AXP_MISC_CTRL_N_VBUSEN_FUNC, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(axp_drivevbus) = {
+ .name = "axp_drivevbus",
+ .id = UCLASS_REGULATOR,
+ .probe = axp_drivevbus_probe,
+ .ops = &axp_drivevbus_ops,
+};

41
package/boot/uboot-d1/patches/0008-power-pmic-axp-Probe-the-drivevbus-regulator-from-th.patch Normal file
View File

@@ -0,0 +1,41 @@
From a588c97f146b67bae47099bc419cf10c02eca169 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 21:34:33 -0500
Subject: [PATCH 08/90] power: pmic: axp: Probe the drivevbus regulator from
the DT
Now that some regulator driver exists for this PMIC, add support for
probing regulator drivers from the device tree subnodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/power/pmic/axp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -45,14 +45,24 @@ static struct dm_pmic_ops axp_pmic_ops =
.write = dm_i2c_write,
};
+static const struct pmic_child_info axp_pmic_child_info[] = {
+ { "drivevbus", "axp_drivevbus" },
+ { }
+};
+
static int axp_pmic_bind(struct udevice *dev)
{
+ ofnode regulators_node;
int ret;
ret = dm_scan_fdt_dev(dev);
if (ret)
return ret;
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (ofnode_valid(regulators_node))
+ pmic_bind_children(dev, regulators_node, axp_pmic_child_info);
+
if (CONFIG_IS_ENABLED(SYSRESET)) {
ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset",
dev_ofnode(dev), NULL);

162
package/boot/uboot-d1/patches/0009-phy-sun4i-usb-Control-USB-supplies-via-regulator-ucl.patch Normal file
View File

@@ -0,0 +1,162 @@
From e8fb34342dfb79cd2059431dd1a0f03202a244ca Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 22:11:37 -0500
Subject: [PATCH 09/90] phy: sun4i-usb: Control USB supplies via regulator
uclass
The device tree binding for the PHY provides VBUS supplies as regulator
references. Now that all boards have the appropriate regulator uclass
drivers enabled, the PHY driver can switch to using them. This replaces
direct GPIO usage, which in some cases needed a special DM-incompatible
"virtual" GPIO from the PMIC.
The following boards provided a value for CONFIG_USB0_VBUS_PIN, but are
missing the "usb0_vbus-supply" property in their device tree. None of
them have the MUSB controller enabled in host or OTG mode, so they
should see no impact:
- Ainol_AW1_defconfig / sun7i-a20-ainol-aw1
- Ampe_A76_defconfig / sun5i-a13-ampe-a76
- CHIP_pro_defconfig / sun5i-gr8-chip-pro
- Cubieboard4_defconfig / sun9i-a80-cubieboard4
- Merrii_A80_Optimus_defconfig / sun9i-a80-optimus
- Sunchip_CX-A99_defconfig / sun9i-a80-cx-a99
- Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078
- Yones_Toptech_BS1078_V2_defconfig /
sun6i-a31s-yones-toptech-bs1078-v2
- iNet_3F_defconfig / sun4i-a10-inet-3f
- iNet_3W_defconfig / sun4i-a10-inet-3w
- iNet_86VS_defconfig / sun5i-a13-inet-86vs
- iNet_D978_rev2_defconfig / sun8i-a33-inet-d978-rev2
- icnova-a20-swac_defconfig / sun7i-a20-icnova-swac
- sun8i_a23_evb_defconfig / sun8i-a23-evb
Similarly, the following boards set CONFIG_USB1_VBUS_PIN, but do not
have "usb1_vbus-supply" in their device tree. Neither of them have USB
enabled at all, so again there should be no impact:
- Cubieboard4_defconfig / sun9i-a80-cubieboard4 (also for USB3)
- sun8i_a23_evb_defconfig / sun8i-a23-evb
The following boards use a different pin for USB1 VBUS between their
defconfig and their device tree. Depending on which is correct, they
may be broken:
- Linksprite_pcDuino3_Nano_defconfig (PH11) /
sun7i-a20-pcduino3-nano (PD2)
- icnova-a20-swac_defconfig (PG10) / sun7i-a20-icnova-swac (PH6)
Finally, this board has conflicting pins given for its USB2 VBUS:
- Lamobo_R1_defconfig (PH3) / sun7i-a20-lamobo-r1 (PH12)
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 41 +++++++++++++--------------
1 file changed, 19 insertions(+), 22 deletions(-)
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -97,27 +97,22 @@ struct sun4i_usb_phy_cfg {
};
struct sun4i_usb_phy_info {
- const char *gpio_vbus;
const char *gpio_vbus_det;
const char *gpio_id_det;
} phy_info[] = {
{
- .gpio_vbus = CONFIG_USB0_VBUS_PIN,
.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
.gpio_id_det = CONFIG_USB0_ID_DET,
},
{
- .gpio_vbus = CONFIG_USB1_VBUS_PIN,
.gpio_vbus_det = NULL,
.gpio_id_det = NULL,
},
{
- .gpio_vbus = CONFIG_USB2_VBUS_PIN,
.gpio_vbus_det = NULL,
.gpio_id_det = NULL,
},
{
- .gpio_vbus = CONFIG_USB3_VBUS_PIN,
.gpio_vbus_det = NULL,
.gpio_id_det = NULL,
},
@@ -125,11 +120,11 @@ struct sun4i_usb_phy_info {
struct sun4i_usb_phy_plat {
void __iomem *pmu;
- struct gpio_desc gpio_vbus;
struct gpio_desc gpio_vbus_det;
struct gpio_desc gpio_id_det;
struct clk clocks;
struct reset_ctl resets;
+ struct udevice *vbus;
int id;
};
@@ -218,14 +213,18 @@ static int sun4i_usb_phy_power_on(struct
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
if (initial_usb_scan_delay) {
mdelay(initial_usb_scan_delay);
initial_usb_scan_delay = 0;
}
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 1);
+ if (usb_phy->vbus) {
+ ret = regulator_set_enable(usb_phy->vbus, true);
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
return 0;
}
@@ -234,9 +233,13 @@ static int sun4i_usb_phy_power_off(struc
{
struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+ int ret;
- if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
- dm_gpio_set_value(&usb_phy->gpio_vbus, 0);
+ if (usb_phy->vbus) {
+ ret = regulator_set_enable(usb_phy->vbus, false);
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
return 0;
}
@@ -450,22 +453,16 @@ static int sun4i_usb_phy_probe(struct ud
for (i = 0; i < data->cfg->num_phys; i++) {
struct sun4i_usb_phy_plat *phy = &plat[i];
struct sun4i_usb_phy_info *info = &phy_info[i];
- char name[16];
+ char name[20];
if (data->cfg->missing_phys & BIT(i))
continue;
- ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus);
- if (ret == 0) {
- ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus");
- if (ret)
- return ret;
- ret = dm_gpio_set_dir_flags(&phy->gpio_vbus,
- GPIOD_IS_OUT);
- if (ret)
- return ret;
- ret = dm_gpio_set_value(&phy->gpio_vbus, 0);
- if (ret)
+ snprintf(name, sizeof(name), "usb%d_vbus-supply", i);
+ ret = device_get_supply_regulator(dev, name, &phy->vbus);
+ if (phy->vbus) {
+ ret = regulator_set_enable(phy->vbus, false);
+ if (ret && ret != -ENOSYS)
return ret;
}

58
package/boot/uboot-d1/patches/0010-sunxi-Remove-obsolete-USBx_VBUS_PIN-Kconfig-symbols.patch Normal file
View File

@@ -0,0 +1,58 @@
From 649bb7845e30805c66f62fc5725c4dbf350f21cb Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 22:26:40 -0500
Subject: [PATCH 10/90] sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols
Now that the USB PHY driver uses the device tree to get VBUS supply
regulators, these Kconfig symbols are unused. Remove them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/mach-sunxi/Kconfig | 29 -----------------------------
1 file changed, 29 deletions(-)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -693,13 +693,6 @@ config MMC_SUNXI_SLOT_EXTRA
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
-config USB0_VBUS_PIN
- string "Vbus enable pin for usb0 (otg)"
- default ""
- ---help---
- Set the Vbus enable pin for usb0 (otg). This takes a string in the
- format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
config USB0_VBUS_DET
string "Vbus detect pin for usb0 (otg)"
default ""
@@ -714,28 +707,6 @@ config USB0_ID_DET
Set the ID detect pin for usb0 (otg). This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-config USB1_VBUS_PIN
- string "Vbus enable pin for usb1 (ehci0)"
- default "PH6" if MACH_SUN4I || MACH_SUN7I
- default "PH27" if MACH_SUN6I
- ---help---
- Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
- a string in the format understood by sunxi_name_to_gpio, e.g.
- PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
- string "Vbus enable pin for usb2 (ehci1)"
- default "PH3" if MACH_SUN4I || MACH_SUN7I
- default "PH24" if MACH_SUN6I
- ---help---
- See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
- string "Vbus enable pin for usb3 (ehci2)"
- default ""
- ---help---
- See USB1_VBUS_PIN help text.
-
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40

393
package/boot/uboot-d1/patches/0011-clk-sunxi-Add-support-for-the-D1-CCU.patch Normal file
View File

@@ -0,0 +1,393 @@
From 73d6c82e34e89cfde880d1948b3e0dc714adead8 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 30 Apr 2022 22:34:19 -0500
Subject: [PATCH 11/90] clk: sunxi: Add support for the D1 CCU
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Series-to: sunxi
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi/Kconfig | 6 +
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_d1.c | 82 ++++++++++++
drivers/clk/sunxi/clk_sunxi.c | 5 +
include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
include/dt-bindings/reset/sun20i-d1-ccu.h | 77 +++++++++++
6 files changed, 327 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_d1.c
create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -87,6 +87,12 @@ config CLK_SUN8I_H3
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
+config CLK_SUN20I_D1
+ bool "Clock driver for Allwinner D1"
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner D1 SoC.
+
config CLK_SUN50I_H6
bool "Clock driver for Allwinner H6"
default MACH_SUN50I_H6
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
--- /dev/null
+++ b/drivers/clk/sunxi/clk_d1.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate d1_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
+ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
+ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
+ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
+ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
+ [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_SPI0] = GATE(0x940, BIT(31)),
+ [CLK_SPI1] = GATE(0x944, BIT(31)),
+ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
+ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
+
+ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
+
+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+ [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
+ [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
+
+ [CLK_RISCV] = GATE(0xd04, BIT(31)),
+};
+
+static struct ccu_reset d1_resets[] = {
+ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
+ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
+ [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
+ [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
+ [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
+ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
+
+ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
+
+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
+ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
+ [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
+ [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
+};
+
+const struct ccu_desc d1_ccu_desc = {
+ .gates = d1_gates,
+ .resets = d1_resets,
+ .num_gates = ARRAY_SIZE(d1_gates),
+ .num_resets = ARRAY_SIZE(d1_resets),
+};
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_des
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
+extern const struct ccu_desc d1_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
@@ -183,6 +184,10 @@ static const struct udevice_id sunxi_clk
{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
.data = (ulong)&a80_mmc_clk_desc },
#endif
+#ifdef CONFIG_CLK_SUN20I_D1
+ { .compatible = "allwinner,sun20i-d1-ccu",
+ .data = (ulong)&d1_ccu_desc },
+#endif
#ifdef CONFIG_CLK_SUN50I_A64
{ .compatible = "allwinner,sun50i-a64-ccu",
.data = (ulong)&a64_ccu_desc },
--- /dev/null
+++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+
+#define CLK_PLL_CPUX 0
+#define CLK_PLL_DDR0 1
+#define CLK_PLL_PERIPH0_4X 2
+#define CLK_PLL_PERIPH0_2X 3
+#define CLK_PLL_PERIPH0_800M 4
+#define CLK_PLL_PERIPH0 5
+#define CLK_PLL_PERIPH0_DIV3 6
+#define CLK_PLL_VIDEO0_4X 7
+#define CLK_PLL_VIDEO0_2X 8
+#define CLK_PLL_VIDEO0 9
+#define CLK_PLL_VIDEO1_4X 10
+#define CLK_PLL_VIDEO1_2X 11
+#define CLK_PLL_VIDEO1 12
+#define CLK_PLL_VE 13
+#define CLK_PLL_AUDIO0_4X 14
+#define CLK_PLL_AUDIO0_2X 15
+#define CLK_PLL_AUDIO0 16
+#define CLK_PLL_AUDIO1 17
+#define CLK_PLL_AUDIO1_DIV2 18
+#define CLK_PLL_AUDIO1_DIV5 19
+#define CLK_CPUX 20
+#define CLK_CPUX_AXI 21
+#define CLK_CPUX_APB 22
+#define CLK_PSI_AHB 23
+#define CLK_APB0 24
+#define CLK_APB1 25
+#define CLK_MBUS 26
+#define CLK_DE 27
+#define CLK_BUS_DE 28
+#define CLK_DI 29
+#define CLK_BUS_DI 30
+#define CLK_G2D 31
+#define CLK_BUS_G2D 32
+#define CLK_CE 33
+#define CLK_BUS_CE 34
+#define CLK_VE 35
+#define CLK_BUS_VE 36
+#define CLK_BUS_DMA 37
+#define CLK_BUS_MSGBOX0 38
+#define CLK_BUS_MSGBOX1 39
+#define CLK_BUS_MSGBOX2 40
+#define CLK_BUS_SPINLOCK 41
+#define CLK_BUS_HSTIMER 42
+#define CLK_AVS 43
+#define CLK_BUS_DBG 44
+#define CLK_BUS_PWM 45
+#define CLK_BUS_IOMMU 46
+#define CLK_DRAM 47
+#define CLK_MBUS_DMA 48
+#define CLK_MBUS_VE 49
+#define CLK_MBUS_CE 50
+#define CLK_MBUS_TVIN 51
+#define CLK_MBUS_CSI 52
+#define CLK_MBUS_G2D 53
+#define CLK_MBUS_RISCV 54
+#define CLK_BUS_DRAM 55
+#define CLK_MMC0 56
+#define CLK_MMC1 57
+#define CLK_MMC2 58
+#define CLK_BUS_MMC0 59
+#define CLK_BUS_MMC1 60
+#define CLK_BUS_MMC2 61
+#define CLK_BUS_UART0 62
+#define CLK_BUS_UART1 63
+#define CLK_BUS_UART2 64
+#define CLK_BUS_UART3 65
+#define CLK_BUS_UART4 66
+#define CLK_BUS_UART5 67
+#define CLK_BUS_I2C0 68
+#define CLK_BUS_I2C1 69
+#define CLK_BUS_I2C2 70
+#define CLK_BUS_I2C3 71
+#define CLK_SPI0 72
+#define CLK_SPI1 73
+#define CLK_BUS_SPI0 74
+#define CLK_BUS_SPI1 75
+#define CLK_EMAC_25M 76
+#define CLK_BUS_EMAC 77
+#define CLK_IR_TX 78
+#define CLK_BUS_IR_TX 79
+#define CLK_BUS_GPADC 80
+#define CLK_BUS_THS 81
+#define CLK_I2S0 82
+#define CLK_I2S1 83
+#define CLK_I2S2 84
+#define CLK_I2S2_ASRC 85
+#define CLK_BUS_I2S0 86
+#define CLK_BUS_I2S1 87
+#define CLK_BUS_I2S2 88
+#define CLK_SPDIF_TX 89
+#define CLK_SPDIF_RX 90
+#define CLK_BUS_SPDIF 91
+#define CLK_DMIC 92
+#define CLK_BUS_DMIC 93
+#define CLK_AUDIO_DAC 94
+#define CLK_AUDIO_ADC 95
+#define CLK_BUS_AUDIO 96
+#define CLK_USB_OHCI0 97
+#define CLK_USB_OHCI1 98
+#define CLK_BUS_OHCI0 99
+#define CLK_BUS_OHCI1 100
+#define CLK_BUS_EHCI0 101
+#define CLK_BUS_EHCI1 102
+#define CLK_BUS_OTG 103
+#define CLK_BUS_LRADC 104
+#define CLK_BUS_DPSS_TOP 105
+#define CLK_HDMI_24M 106
+#define CLK_HDMI_CEC_32K 107
+#define CLK_HDMI_CEC 108
+#define CLK_BUS_HDMI 109
+#define CLK_MIPI_DSI 110
+#define CLK_BUS_MIPI_DSI 111
+#define CLK_TCON_LCD0 112
+#define CLK_BUS_TCON_LCD0 113
+#define CLK_TCON_TV 114
+#define CLK_BUS_TCON_TV 115
+#define CLK_TVE 116
+#define CLK_BUS_TVE_TOP 117
+#define CLK_BUS_TVE 118
+#define CLK_TVD 119
+#define CLK_BUS_TVD_TOP 120
+#define CLK_BUS_TVD 121
+#define CLK_LEDC 122
+#define CLK_BUS_LEDC 123
+#define CLK_CSI_TOP 124
+#define CLK_CSI_MCLK 125
+#define CLK_BUS_CSI 126
+#define CLK_TPADC 127
+#define CLK_BUS_TPADC 128
+#define CLK_BUS_TZMA 129
+#define CLK_DSP 130
+#define CLK_BUS_DSP_CFG 131
+#define CLK_RISCV 132
+#define CLK_RISCV_AXI 133
+#define CLK_BUS_RISCV_CFG 134
+#define CLK_FANOUT_24M 135
+#define CLK_FANOUT_12M 136
+#define CLK_FANOUT_16M 137
+#define CLK_FANOUT_25M 138
+#define CLK_FANOUT_32K 139
+#define CLK_FANOUT_27M 140
+#define CLK_FANOUT_PCLK 141
+#define CLK_FANOUT0 142
+#define CLK_FANOUT1 143
+#define CLK_FANOUT2 144
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+
+#define RST_MBUS 0
+#define RST_BUS_DE 1
+#define RST_BUS_DI 2
+#define RST_BUS_G2D 3
+#define RST_BUS_CE 4
+#define RST_BUS_VE 5
+#define RST_BUS_DMA 6
+#define RST_BUS_MSGBOX0 7
+#define RST_BUS_MSGBOX1 8
+#define RST_BUS_MSGBOX2 9
+#define RST_BUS_SPINLOCK 10
+#define RST_BUS_HSTIMER 11
+#define RST_BUS_DBG 12
+#define RST_BUS_PWM 13
+#define RST_BUS_DRAM 14
+#define RST_BUS_MMC0 15
+#define RST_BUS_MMC1 16
+#define RST_BUS_MMC2 17
+#define RST_BUS_UART0 18
+#define RST_BUS_UART1 19
+#define RST_BUS_UART2 20
+#define RST_BUS_UART3 21
+#define RST_BUS_UART4 22
+#define RST_BUS_UART5 23
+#define RST_BUS_I2C0 24
+#define RST_BUS_I2C1 25
+#define RST_BUS_I2C2 26
+#define RST_BUS_I2C3 27
+#define RST_BUS_SPI0 28
+#define RST_BUS_SPI1 29
+#define RST_BUS_EMAC 30
+#define RST_BUS_IR_TX 31
+#define RST_BUS_GPADC 32
+#define RST_BUS_THS 33
+#define RST_BUS_I2S0 34
+#define RST_BUS_I2S1 35
+#define RST_BUS_I2S2 36
+#define RST_BUS_SPDIF 37
+#define RST_BUS_DMIC 38
+#define RST_BUS_AUDIO 39
+#define RST_USB_PHY0 40
+#define RST_USB_PHY1 41
+#define RST_BUS_OHCI0 42
+#define RST_BUS_OHCI1 43
+#define RST_BUS_EHCI0 44
+#define RST_BUS_EHCI1 45
+#define RST_BUS_OTG 46
+#define RST_BUS_LRADC 47
+#define RST_BUS_DPSS_TOP 48
+#define RST_BUS_HDMI_SUB 49
+#define RST_BUS_HDMI_MAIN 50
+#define RST_BUS_MIPI_DSI 51
+#define RST_BUS_TCON_LCD0 52
+#define RST_BUS_TCON_TV 53
+#define RST_BUS_LVDS0 54
+#define RST_BUS_TVE 55
+#define RST_BUS_TVE_TOP 56
+#define RST_BUS_TVD 57
+#define RST_BUS_TVD_TOP 58
+#define RST_BUS_LEDC 59
+#define RST_BUS_CSI 60
+#define RST_BUS_TPADC 61
+#define RST_DSP 62
+#define RST_BUS_DSP_CFG 63
+#define RST_BUS_DSP_DBG 64
+#define RST_BUS_RISCV_CFG 65
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */

227
package/boot/uboot-d1/patches/0012-gpio-axp-Remove-virtual-VBUS-enable-GPIO.patch Normal file
View File

@@ -0,0 +1,227 @@
From cbb281e0ec847b9de41970e470348b3534bb9a9f Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 26 Aug 2021 18:02:54 -0500
Subject: [PATCH 12/90] gpio: axp: Remove virtual VBUS enable GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove
it, along with the rest of the support for AXP virtual GPIOs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/include/asm/arch-sunxi/gpio.h | 8 ---
drivers/gpio/axp_gpio.c | 75 ++++++++------------------
drivers/gpio/sunxi_gpio.c | 8 ---
include/axp221.h | 4 --
include/axp809.h | 4 --
include/axp818.h | 4 --
6 files changed, 21 insertions(+), 82 deletions(-)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -111,7 +111,6 @@ enum sunxi_gpio_number {
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
- SUNXI_GPIO_AXP0_START = 1024,
};
/* SUNXI GPIO number definitions */
@@ -128,8 +127,6 @@ enum sunxi_gpio_number {
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
-#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
-
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
@@ -207,11 +204,6 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
-#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
-
struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
char bank_name[3];
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -15,6 +15,9 @@
#include <dm/root.h>
#include <errno.h>
+#define AXP_GPIO_PREFIX "AXP0-"
+#define AXP_GPIO_COUNT 4
+
static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
static u8 axp_get_gpio_ctrl_reg(unsigned pin)
@@ -46,28 +49,14 @@ static int axp_gpio_direction_input(stru
static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- __maybe_unused int ret;
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_clrbits(AXP_MISC_CTRL,
- AXP_MISC_CTRL_N_VBUSEN_FUNC);
- if (ret)
- return ret;
-
- return axp_gpio_set_value(dev, pin, val);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
@@ -75,25 +64,16 @@ static int axp_gpio_get_value(struct ude
u8 reg, val, mask;
int ret;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
- mask = AXP_VBUS_IPSOUT_DRIVEBUS;
- break;
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- ret = pmic_bus_read(AXP_GPIO_STATE, &val);
- mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
- }
+ ret = pmic_bus_read(AXP_GPIO_STATE, &val);
if (ret)
return ret;
+ mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+
return (val & mask) ? 1 : 0;
}
@@ -101,25 +81,12 @@ static int axp_gpio_set_value(struct ude
{
u8 reg;
- switch (pin) {
-#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
- /* Only available on later PMICs */
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- if (val)
- return pmic_bus_setbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
- else
- return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
- AXP_VBUS_IPSOUT_DRIVEBUS);
-#endif
- default:
- reg = axp_get_gpio_ctrl_reg(pin);
- if (reg == 0)
- return -EINVAL;
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
- return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
- AXP_GPIO_CTRL_OUTPUT_LOW);
- }
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
}
static const struct dm_gpio_ops gpio_axp_ops = {
@@ -134,8 +101,8 @@ static int gpio_axp_probe(struct udevice
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
- uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
- uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
+ uc_priv->bank_name = AXP_GPIO_PREFIX;
+ uc_priv->gpio_count = AXP_GPIO_COUNT;
return 0;
}
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -114,15 +114,7 @@ int sunxi_name_to_gpio(const char *name)
{
unsigned int gpio;
int ret;
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
- char lookup[8];
- if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
- sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
- SUNXI_GPIO_AXP0_VBUS_ENABLE);
- name = lookup;
- }
-#endif
ret = gpio_lookup_name(name, NULL, NULL, &gpio);
return ret ? ret : gpio;
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,10 +53,6 @@
#ifdef CONFIG_AXP221_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,10 +47,6 @@
#ifdef CONFIG_AXP809_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,10 +61,6 @@
#ifdef CONFIG_AXP818_POWER
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_ALDO_IN BIT(0)
-#define AXP_VBUS_IPSOUT 0x30
-#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
-#define AXP_MISC_CTRL 0x8f
-#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */

160
package/boot/uboot-d1/patches/0013-clk-sunxi-Add-a-driver-for-the-legacy-A31-A23-A33-PR.patch Normal file
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@@ -0,0 +1,160 @@
From 5a909f4d4d10f3a7a59b3b75eee502937e166891 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Mon, 2 May 2022 22:00:05 -0500
Subject: [PATCH 13/90] clk: sunxi: Add a driver for the legacy A31/A23/A33
PRCM
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi/Kconfig | 13 ++++-
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_a31_apb0.c | 97 ++++++++++++++++++++++++++++++++
include/clk/sunxi.h | 1 +
4 files changed, 110 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/sunxi/clk_a31_apb0.c
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -38,12 +38,21 @@ config CLK_SUN6I_A31
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
+config CLK_SUN6I_A31_APB0
+ bool "Clock driver for Allwinner A31 generation PRCM (legacy)"
+ default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM
+ MFD binding.
+
config CLK_SUN6I_A31_R
- bool "Clock driver for Allwinner A31 generation PRCM"
+ bool "Clock driver for Allwinner A31 generation PRCM (CCU)"
default SUNXI_GEN_SUN6I
help
This enables common clock driver support for the PRCM
- in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using
+ the new CCU binding.
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_APB0) += clk_a31_apb0.o
obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a31_apb0.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate sun6i_apb0_gates[] = {
+ [0] = GATE(0x028, BIT(0)),
+ [1] = GATE(0x028, BIT(1)),
+ [2] = GATE(0x028, BIT(2)),
+ [3] = GATE(0x028, BIT(3)),
+ [4] = GATE(0x028, BIT(4)),
+ [5] = GATE(0x028, BIT(5)),
+ [6] = GATE(0x028, BIT(6)),
+ [7] = GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset sun6i_apb0_resets[] = {
+ [0] = RESET(0x0b0, BIT(0)),
+ [1] = RESET(0x0b0, BIT(1)),
+ [2] = RESET(0x0b0, BIT(2)),
+ [3] = RESET(0x0b0, BIT(3)),
+ [4] = RESET(0x0b0, BIT(4)),
+ [5] = RESET(0x0b0, BIT(5)),
+ [6] = RESET(0x0b0, BIT(6)),
+ [7] = RESET(0x0b0, BIT(7)),
+};
+
+const struct ccu_desc sun6i_apb0_clk_desc = {
+ .gates = sun6i_apb0_gates,
+ .resets = sun6i_apb0_resets,
+ .num_gates = ARRAY_SIZE(sun6i_apb0_gates),
+ .num_resets = ARRAY_SIZE(sun6i_apb0_resets),
+};
+
+static int sun6i_apb0_of_to_plat(struct udevice *dev)
+{
+ struct ccu_plat *plat = dev_get_plat(dev);
+
+ plat->base = dev_read_addr_ptr(dev->parent);
+ if (!plat->base)
+ return -ENOMEM;
+
+ plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+ if (!plat->desc)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id sun6i_apb0_clk_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-apb0-gates-clk",
+ .data = (ulong)&sun6i_apb0_clk_desc },
+ { .compatible = "allwinner,sun8i-a23-apb0-gates-clk",
+ .data = (ulong)&sun6i_apb0_clk_desc },
+ { }
+};
+
+U_BOOT_DRIVER(sun6i_apb0_clk) = {
+ .name = "sun6i_apb0_clk",
+ .id = UCLASS_CLK,
+ .of_match = sun6i_apb0_clk_ids,
+ .of_to_plat = sun6i_apb0_of_to_plat,
+ .plat_auto = sizeof(struct ccu_plat),
+ .ops = &sunxi_clk_ops,
+};
+
+static const struct udevice_id sun6i_apb0_reset_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-clock-reset",
+ .data = (ulong)&sun6i_apb0_clk_desc },
+ { }
+};
+
+U_BOOT_DRIVER(sun6i_apb0_reset) = {
+ .name = "sun6i_apb0_reset",
+ .id = UCLASS_RESET,
+ .of_match = sun6i_apb0_reset_ids,
+ .of_to_plat = sun6i_apb0_of_to_plat,
+ .plat_auto = sizeof(struct ccu_plat),
+ .ops = &sunxi_reset_ops,
+};
+
+static const struct udevice_id sun6i_prcm_mfd_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-prcm" },
+ { .compatible = "allwinner,sun8i-a23-prcm" },
+ { }
+};
+
+U_BOOT_DRIVER(sun6i_prcm_mfd) = {
+ .name = "sun6i_prcm_mfd",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = sun6i_prcm_mfd_ids,
+};
--- a/include/clk/sunxi.h
+++ b/include/clk/sunxi.h
@@ -86,5 +86,6 @@ struct ccu_plat {
};
extern struct clk_ops sunxi_clk_ops;
+extern struct reset_ops sunxi_reset_ops;
#endif /* _CLK_SUNXI_H */

21
package/boot/uboot-d1/patches/0014-clk-sunxi-Use-the-right-symbol-in-the-Makefile.patch Normal file
View File

@@ -0,0 +1,21 @@
From 3d97f99cb173422ee8a15b7ec1df83ff61e68204 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 30 Oct 2022 14:28:23 -0500
Subject: [PATCH 14/90] clk: sunxi: Use the right symbol in the Makefile
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_ARCH_STM32) += stm32/
obj-$(CONFIG_ARCH_STM32MP) += stm32/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+obj-$(CONFIG_CLK_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o

100
package/boot/uboot-d1/patches/0015-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch Normal file
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@@ -0,0 +1,100 @@
From 9766169812418aee10dbc8d40aca27c1c576f521 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 14 Jul 2022 23:39:46 -0500
Subject: [PATCH 15/90] net: sun8i-emac: Use common syscon setup for R40
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.
This change provides two benefits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Series-to: sunxi
Cover-letter:
net: sun8i-emac: Allwinner D1 Support
D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
However, there are a couple of issues with the driver preventing it
being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
a general cleanup.
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/net/sun8i_emac.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -162,7 +162,7 @@ struct emac_eth_dev {
enum emac_variant variant;
void *mac_reg;
- phys_addr_t sysctl_reg;
+ void *sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
struct clk tx_clk;
@@ -317,18 +317,7 @@ static int sun8i_emac_set_syscon(struct
{
u32 reg;
- if (priv->variant == R40_GMAC) {
- /* Select RGMII for R40 */
- reg = readl(priv->sysctl_reg + 0x164);
- reg |= SC_ETCS_INT_GMII |
- SC_EPIT |
- (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
-
- writel(reg, priv->sysctl_reg + 0x164);
- return 0;
- }
-
- reg = readl(priv->sysctl_reg + 0x30);
+ reg = readl(priv->sysctl_reg);
reg = sun8i_emac_set_syscon_ephy(priv, reg);
@@ -369,7 +358,7 @@ static int sun8i_emac_set_syscon(struct
reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
& SC_ERXDC_MASK;
- writel(reg, priv->sysctl_reg + 0x30);
+ writel(reg, priv->sysctl_reg);
return 0;
}
@@ -792,6 +781,7 @@ static int sun8i_emac_eth_of_to_plat(str
struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
+ phys_addr_t syscon_base;
const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
@@ -837,13 +827,18 @@ static int sun8i_emac_eth_of_to_plat(str
__func__);
return -EINVAL;
}
- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
- offset, reg);
- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+
+ syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
+ if (syscon_base == FDT_ADDR_T_NONE) {
debug("%s: Cannot find syscon base address\n", __func__);
return -EINVAL;
}
+ if (priv->variant == R40_GMAC)
+ priv->sysctl_reg = (void *)syscon_base + 0x164;
+ else
+ priv->sysctl_reg = (void *)syscon_base + 0x30;
+
pdata->phy_interface = -1;
priv->phyaddr = -1;
priv->use_internal_phy = false;

92
package/boot/uboot-d1/patches/0016-sunxi-mmc-ignore-card-detect-in-SPL.patch Normal file
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@@ -0,0 +1,92 @@
From 2cde6c8a7c41c13137298c19b4e104e4f5d6851c Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 13 Jul 2022 17:21:43 +0100
Subject: [PATCH 16/90] sunxi: mmc: ignore card detect in SPL
The sunxi MMC code does not use the DM in the SPL, as we don't have a
device tree available that early, also no space for it.
This also means we cannot access the card-detect GPIO information from
there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
board has to define. This is a burden, also requires extra GPIO code in
the SPL.
As the SPL is the natural successor of the BootROM (from which we are
loaded), we can actually ignore the CD pin completely, as this is what
the BootROM does as well: CD GPIOs are board specific, but the BootROM
is not, so accesses the MMC devices anyway.
Remove the card detect code from the non-DM implementation of the sunxi
MMC driver, to get rid of this unneeded code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/mmc/sunxi_mmc.c | 37 ++-----------------------------------
1 file changed, 2 insertions(+), 35 deletions(-)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -44,22 +44,10 @@ struct sunxi_mmc_priv {
/* support 4 mmc hosts */
struct sunxi_mmc_priv mmc_host[4];
-static int sunxi_mmc_getcd_gpio(int sdc_no)
-{
- switch (sdc_no) {
- case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
- case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
- case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
- case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
- }
- return -EINVAL;
-}
-
static int mmc_resource_init(int sdc_no)
{
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int cd_pin, ret = 0;
debug("init mmc %d resource\n", sdc_no);
@@ -90,16 +78,7 @@ static int mmc_resource_init(int sdc_no)
}
priv->mmc_no = sdc_no;
- cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
- if (cd_pin >= 0) {
- ret = gpio_request(cd_pin, "mmc_cd");
- if (!ret) {
- sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
- ret = gpio_direction_input(cd_pin);
- }
- }
-
- return ret;
+ return 0;
}
#endif
@@ -523,23 +502,11 @@ static int sunxi_mmc_send_cmd_legacy(str
return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
}
-static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
-{
- struct sunxi_mmc_priv *priv = mmc->priv;
- int cd_pin;
-
- cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
- if (cd_pin < 0)
- return 1;
-
- return !gpio_get_value(cd_pin);
-}
-
+/* .get_cd is not needed by the SPL */
static const struct mmc_ops sunxi_mmc_ops = {
.send_cmd = sunxi_mmc_send_cmd_legacy,
.set_ios = sunxi_mmc_set_ios_legacy,
.init = sunxi_mmc_core_init,
- .getcd = sunxi_mmc_getcd_legacy,
};
struct mmc *sunxi_mmc_init(int sdc_no)

177
package/boot/uboot-d1/patches/0017-sunxi-mmc-group-non-DM-specific-functions.patch Normal file
View File

@@ -0,0 +1,177 @@
From 74afc3a4e0ff780eddd859a25de7142e4baeeed5 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 13 Jul 2022 17:21:44 +0100
Subject: [PATCH 17/90] sunxi: mmc: group non-DM specific functions
As the SPL code for sunxi boards does not use the driver model, we have
two mmc_ops structures, one for DM, one for non-DM. The actual hardware
access code is shared, with the respective callback functions using that
common code.
To make this more obvious and easier to read, reorder the functions to
group them: we first have the common code, then the non-DM bits, and
the proper DM implementation at the end.
Also document this structure in the comment at the beginning of the file.
No functional change intended.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/mmc/sunxi_mmc.c | 117 +++++++++++++++++++++-------------------
1 file changed, 61 insertions(+), 56 deletions(-)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -5,6 +5,12 @@
* Aaron <leafy.myeh@allwinnertech.com>
*
* MMC driver for allwinner sunxi platform.
+ *
+ * This driver is used by the (ARM) SPL with the legacy MMC interface, and
+ * by U-Boot proper using the full DM interface. The actual hardware access
+ * code is common, and comes first in this file.
+ * The legacy MMC interface implementation comes next, followed by the
+ * proper DM_MMC implementation at the end.
*/
#include <common.h>
@@ -40,48 +46,6 @@ struct sunxi_mmc_priv {
struct mmc_config cfg;
};
-#if !CONFIG_IS_ENABLED(DM_MMC)
-/* support 4 mmc hosts */
-struct sunxi_mmc_priv mmc_host[4];
-
-static int mmc_resource_init(int sdc_no)
-{
- struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- debug("init mmc %d resource\n", sdc_no);
-
- switch (sdc_no) {
- case 0:
- priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
- priv->mclkreg = &ccm->sd0_clk_cfg;
- break;
- case 1:
- priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
- priv->mclkreg = &ccm->sd1_clk_cfg;
- break;
-#ifdef SUNXI_MMC2_BASE
- case 2:
- priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
- priv->mclkreg = &ccm->sd2_clk_cfg;
- break;
-#endif
-#ifdef SUNXI_MMC3_BASE
- case 3:
- priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
- priv->mclkreg = &ccm->sd3_clk_cfg;
- break;
-#endif
- default:
- printf("Wrong mmc number %d\n", sdc_no);
- return -1;
- }
- priv->mmc_no = sdc_no;
-
- return 0;
-}
-#endif
-
/*
* All A64 and later MMC controllers feature auto-calibration. This would
* normally be detected via the compatible string, but we need something
@@ -269,19 +233,6 @@ static int sunxi_mmc_set_ios_common(stru
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int sunxi_mmc_core_init(struct mmc *mmc)
-{
- struct sunxi_mmc_priv *priv = mmc->priv;
-
- /* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
- udelay(1000);
-
- return 0;
-}
-#endif
-
static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
struct mmc_data *data)
{
@@ -486,7 +437,60 @@ out:
return error;
}
+/* non-DM code here is used by the (ARM) SPL only */
+
#if !CONFIG_IS_ENABLED(DM_MMC)
+/* support 4 mmc hosts */
+struct sunxi_mmc_priv mmc_host[4];
+
+static int mmc_resource_init(int sdc_no)
+{
+ struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ debug("init mmc %d resource\n", sdc_no);
+
+ switch (sdc_no) {
+ case 0:
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+ priv->mclkreg = &ccm->sd0_clk_cfg;
+ break;
+ case 1:
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+ priv->mclkreg = &ccm->sd1_clk_cfg;
+ break;
+#ifdef SUNXI_MMC2_BASE
+ case 2:
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+ priv->mclkreg = &ccm->sd2_clk_cfg;
+ break;
+#endif
+#ifdef SUNXI_MMC3_BASE
+ case 3:
+ priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+ priv->mclkreg = &ccm->sd3_clk_cfg;
+ break;
+#endif
+ default:
+ printf("Wrong mmc number %d\n", sdc_no);
+ return -1;
+ }
+ priv->mmc_no = sdc_no;
+
+ return 0;
+}
+
+static int sunxi_mmc_core_init(struct mmc *mmc)
+{
+ struct sunxi_mmc_priv *priv = mmc->priv;
+
+ /* Reset controller */
+ writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+ udelay(1000);
+
+ return 0;
+}
+
static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
{
struct sunxi_mmc_priv *priv = mmc->priv;
@@ -562,7 +566,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
return mmc_create(cfg, priv);
}
-#else
+
+#else /* CONFIG_DM_MMC code below, as used by U-Boot proper */
static int sunxi_mmc_set_ios(struct udevice *dev)
{

509
package/boot/uboot-d1/patches/0018-sunxi-remove-CONFIG_MMC-_CD_PIN.patch Normal file
View File

@@ -0,0 +1,509 @@
From bcc2e01668041c146d964ed5f77b819dcc35b3e2 Mon Sep 17 00:00:00 2001
From: Zoltan HERPAI <wigyori@uid0.hu>
Date: Tue, 6 Jun 2023 15:07:47 +0000
Subject: [PATCH 18/90] sunxi: remove CONFIG_MMC?_CD_PIN
For legacy reasons we were defining the card detect GPIO for all sunxi
boards in each board's defconfig.
There is actually no need for a card-detect check in the SPL code (which
consequently has been removed already), and also in U-Boot proper we
have DM code to query the CD GPIO name from the device tree.
That means we don't have any user of that information left, so can
remove the definitions from the defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
---
arch/arm/mach-sunxi/Kconfig | 27 --------------------
configs/A10-OLinuXino-Lime_defconfig | 1 -
configs/A10s-OLinuXino-M_defconfig | 2 --
configs/A13-OLinuXino_defconfig | 1 -
configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 -
configs/A20-OLinuXino-Lime_defconfig | 1 -
configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 -
configs/A20-OLinuXino_MICRO_defconfig | 2 --
configs/A20-Olimex-SOM-EVB_defconfig | 2 --
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 -
configs/Bananapi_M2_Ultra_defconfig | 1 -
configs/Bananapi_m2m_defconfig | 1 -
configs/Cubieboard2_defconfig | 1 -
configs/Cubieboard4_defconfig | 1 -
configs/Cubieboard_defconfig | 1 -
configs/Itead_Ibox_A20_defconfig | 1 -
configs/Lamobo_R1_defconfig | 1 -
configs/Mele_M3_defconfig | 1 -
configs/Mele_M5_defconfig | 1 -
configs/Merrii_A80_Optimus_defconfig | 1 -
configs/Orangepi_mini_defconfig | 2 --
configs/Sinlinx_SinA31s_defconfig | 1 -
configs/Sinlinx_SinA33_defconfig | 1 -
configs/Sunchip_CX-A99_defconfig | 1 -
configs/UTOO_P66_defconfig | 1 -
configs/Yones_Toptech_BD1078_defconfig | 2 --
configs/bananapi_m2_zero_defconfig | 1 -
configs/bananapi_m64_defconfig | 1 -
configs/beelink_gs1_defconfig | 1 -
configs/nanopi_m1_plus_defconfig | 1 -
configs/oceanic_5205_5inmfd_defconfig | 1 -
configs/orangepi_3_defconfig | 1 -
configs/orangepi_lite2_defconfig | 1 -
configs/orangepi_one_plus_defconfig | 1 -
configs/orangepi_zero2_defconfig | 1 -
configs/orangepi_zero_plus2_defconfig | 1 -
configs/orangepi_zero_plus2_h3_defconfig | 1 -
configs/parrot_r16_defconfig | 1 -
configs/pine64-lts_defconfig | 1 -
configs/pine_h64_defconfig | 1 -
configs/sopine_baseboard_defconfig | 1 -
configs/tanix_tx6_defconfig | 1 -
42 files changed, 73 deletions(-)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -652,33 +652,6 @@ config MACPWR
Set the pin used to power the MAC. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-config MMC0_CD_PIN
- string "Card detect pin for mmc0"
- default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
- default ""
- ---help---
- Set the card detect pin for mmc0, leave empty to not use cd. This
- takes a string in the format understood by sunxi_name_to_gpio, e.g.
- PH1 for pin 1 of port H.
-
-config MMC1_CD_PIN
- string "Card detect pin for mmc1"
- default ""
- ---help---
- See MMC0_CD_PIN help text.
-
-config MMC2_CD_PIN
- string "Card detect pin for mmc2"
- default ""
- ---help---
- See MMC0_CD_PIN help text.
-
-config MMC3_CD_PIN
- string "Card detect pin for mmc3"
- default ""
- ---help---
- See MMC0_CD_PIN help text.
-
config MMC1_PINS_PH
bool "Pins for mmc1 are on Port H"
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-o
CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
-CONFIG_MMC0_CD_PIN="PG1"
-CONFIG_MMC1_CD_PIN="PG13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
CONFIG_USB0_VBUS_DET="PG1"
CONFIG_USB1_VBUS_PIN="PG11"
CONFIG_AXP_GPIO=y
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC3_CD_PIN="PH0"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_MACPWR="PA17"
-CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH23"
CONFIG_USB2_VBUS_PIN="PH23"
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cu
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cu
CONFIG_SPL=y
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
-CONFIG_MMC0_CD_PIN="PH18"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cu
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-it
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
-CONFIG_MMC0_CD_PIN="PH10"
CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=122
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-op
CONFIG_SPL=y
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
-CONFIG_MMC0_CD_PIN="PH18"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -5,8 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
-CONFIG_MMC0_CD_PIN="PH10"
-CONFIG_MMC3_CD_PIN="PH11"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
-CONFIG_MMC0_CD_PIN="PA4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
-CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=3881915
CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PH17"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PH15"
CONFIG_USB1_VBUS_PIN="PL7"
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
-CONFIG_MMC0_CD_PIN="PG0"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PB04"
CONFIG_USB0_VBUS_DET="PG01"
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yo
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
-CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_MMC1_CD_PIN="PH2"
CONFIG_MMC1_PINS_PH=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB0_VBUS_PIN="PB9"
--- a/configs/bananapi_m2_zero_defconfig
+++ b/configs/bananapi_m2_zero_defconfig
@@ -4,5 +4,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plu
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
-CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-b
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
-CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUPPORT_EMMC_BOOT=y
--- a/configs/beelink_gs1_defconfig
+++ b/configs/beelink_gs1_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-be
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MACPWR="PD6"
-CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
--- a/configs/oceanic_5205_5inmfd_defconfig
+++ b/configs/oceanic_5205_5inmfd_defconfig
@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
-CONFIG_MMC0_CD_PIN=""
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
--- a/configs/orangepi_3_defconfig
+++ b/configs/orangepi_3_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/orangepi_lite2_defconfig
+++ b/configs/orangepi_lite2_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_USB_EHCI_HCD=y
--- a/configs/orangepi_one_plus_defconfig
+++ b/configs/orangepi_one_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_USB_EHCI_HCD=y
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -7,7 +7,6 @@ CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION
CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y
CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y
CONFIG_MACH_SUN50I_H616=y
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/orangepi_zero_plus2_defconfig
+++ b/configs/orangepi_zero_plus2_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
-CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
--- a/configs/orangepi_zero_plus2_h3_defconfig
+++ b/configs/orangepi_zero_plus2_h3_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_DRAM_ODT_EN is not set
-CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
-CONFIG_MMC0_CD_PIN="PD14"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PD10"
CONFIG_USB1_VBUS_PIN="PD12"
--- a/configs/pine64-lts_defconfig
+++ b/configs/pine64-lts_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
-CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MACPWR="PC16"
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
-CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/configs/tanix_tx6_defconfig
+++ b/configs/tanix_tx6_defconfig
@@ -5,6 +5,5 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_DDR3_1333=y
CONFIG_DRAM_CLK=648
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

323
package/boot/uboot-d1/patches/0019-sunxi-mmc-Move-header-to-the-driver-directory.patch Normal file
View File

@@ -0,0 +1,323 @@
From 4c0c00e7131baf410702555342337c178dd0de98 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 30 Oct 2022 16:04:47 -0500
Subject: [PATCH 19/90] sunxi: mmc: Move header to the driver directory
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/include/asm/arch-sunxi/mmc.h | 139 +-------------------------
drivers/mmc/sunxi_mmc.c | 4 +
drivers/mmc/sunxi_mmc.h | 138 +++++++++++++++++++++++++
3 files changed, 146 insertions(+), 135 deletions(-)
create mode 100644 drivers/mmc/sunxi_mmc.h
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -1,139 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Aaron <leafy.myeh@allwinnertech.com>
- *
- * MMC register definition for allwinner sunxi platform.
- */
-#ifndef _SUNXI_MMC_H
-#define _SUNXI_MMC_H
-
-#include <linux/types.h>
-
-struct sunxi_mmc {
- u32 gctrl; /* 0x00 global control */
- u32 clkcr; /* 0x04 clock control */
- u32 timeout; /* 0x08 time out */
- u32 width; /* 0x0c bus width */
- u32 blksz; /* 0x10 block size */
- u32 bytecnt; /* 0x14 byte count */
- u32 cmd; /* 0x18 command */
- u32 arg; /* 0x1c argument */
- u32 resp0; /* 0x20 response 0 */
- u32 resp1; /* 0x24 response 1 */
- u32 resp2; /* 0x28 response 2 */
- u32 resp3; /* 0x2c response 3 */
- u32 imask; /* 0x30 interrupt mask */
- u32 mint; /* 0x34 masked interrupt status */
- u32 rint; /* 0x38 raw interrupt status */
- u32 status; /* 0x3c status */
- u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
- u32 funcsel; /* 0x44 function select */
- u32 cbcr; /* 0x48 CIU byte count */
- u32 bbcr; /* 0x4c BIU byte count */
- u32 dbgc; /* 0x50 debug enable */
- u32 res0; /* 0x54 reserved */
- u32 a12a; /* 0x58 Auto command 12 argument */
- u32 ntsr; /* 0x5c New timing set register */
- u32 res1[8];
- u32 dmac; /* 0x80 internal DMA control */
- u32 dlba; /* 0x84 internal DMA descr list base address */
- u32 idst; /* 0x88 internal DMA status */
- u32 idie; /* 0x8c internal DMA interrupt enable */
- u32 chda; /* 0x90 */
- u32 cbda; /* 0x94 */
- u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
- u32 res3[17];
- u32 samp_dl;
- u32 res4[46];
-#endif
- u32 fifo; /* 0x100 / 0x200 FIFO access address */
-};
-
-#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
-#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
-#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
-
-#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
-#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
-#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
-#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
- SUNXI_MMC_GCTRL_FIFO_RESET|\
- SUNXI_MMC_GCTRL_DMA_RESET)
-#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
-
-#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
-#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
-#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
-#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
-#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
-#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
-#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
-#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
-#define SUNXI_MMC_CMD_START (0x1 << 31)
-
-#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
-#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
-#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
-#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
-#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
-#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
-#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
-#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
-#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
-#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
-#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
-#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
-#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
-#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
- (SUNXI_MMC_RINT_RESP_ERROR | \
- SUNXI_MMC_RINT_RESP_CRC_ERROR | \
- SUNXI_MMC_RINT_DATA_CRC_ERROR | \
- SUNXI_MMC_RINT_RESP_TIMEOUT | \
- SUNXI_MMC_RINT_DATA_TIMEOUT | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
- SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
- SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
- SUNXI_MMC_RINT_START_BIT_ERROR | \
- SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
- (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
- SUNXI_MMC_RINT_DATA_OVER | \
- SUNXI_MMC_RINT_COMMAND_DONE | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
-
-#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
-#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
-#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
-#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
-#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
-
-#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
-
-#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
-#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
-#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
-
-#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
-#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
-
-#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
-#define SUNXI_MMC_COMMON_RESET (1 << 18)
-
-#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+#ifndef _ASM_ARCH_MMC_H_
+#define _ASM_ARCH_MMC_H_
struct mmc *sunxi_mmc_init(int sdc_no);
-#endif /* _SUNXI_MMC_H */
+
+#endif /* _ASM_ARCH_MMC_H_ */
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -25,9 +25,13 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#if !CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/mmc.h>
+#endif
#include <linux/delay.h>
+#include "sunxi_mmc.h"
+
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
#define CCM_MMC_CTRL_MODE_SEL_NEW 0
#endif
--- /dev/null
+++ b/drivers/mmc/sunxi_mmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC register definition for allwinner sunxi platform.
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include <linux/types.h>
+
+struct sunxi_mmc {
+ u32 gctrl; /* 0x00 global control */
+ u32 clkcr; /* 0x04 clock control */
+ u32 timeout; /* 0x08 time out */
+ u32 width; /* 0x0c bus width */
+ u32 blksz; /* 0x10 block size */
+ u32 bytecnt; /* 0x14 byte count */
+ u32 cmd; /* 0x18 command */
+ u32 arg; /* 0x1c argument */
+ u32 resp0; /* 0x20 response 0 */
+ u32 resp1; /* 0x24 response 1 */
+ u32 resp2; /* 0x28 response 2 */
+ u32 resp3; /* 0x2c response 3 */
+ u32 imask; /* 0x30 interrupt mask */
+ u32 mint; /* 0x34 masked interrupt status */
+ u32 rint; /* 0x38 raw interrupt status */
+ u32 status; /* 0x3c status */
+ u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
+ u32 funcsel; /* 0x44 function select */
+ u32 cbcr; /* 0x48 CIU byte count */
+ u32 bbcr; /* 0x4c BIU byte count */
+ u32 dbgc; /* 0x50 debug enable */
+ u32 res0; /* 0x54 reserved */
+ u32 a12a; /* 0x58 Auto command 12 argument */
+ u32 ntsr; /* 0x5c New timing set register */
+ u32 res1[8];
+ u32 dmac; /* 0x80 internal DMA control */
+ u32 dlba; /* 0x84 internal DMA descr list base address */
+ u32 idst; /* 0x88 internal DMA status */
+ u32 idie; /* 0x8c internal DMA interrupt enable */
+ u32 chda; /* 0x90 */
+ u32 cbda; /* 0x94 */
+ u32 res2[26];
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+ u32 res3[17];
+ u32 samp_dl;
+ u32 res4[46];
+#endif
+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
+};
+
+#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
+#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
+#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
+
+#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
+#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
+#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
+#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
+ SUNXI_MMC_GCTRL_FIFO_RESET|\
+ SUNXI_MMC_GCTRL_DMA_RESET)
+#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
+#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
+
+#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
+#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
+#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
+#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
+#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
+#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
+#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
+#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
+#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
+#define SUNXI_MMC_CMD_START (0x1 << 31)
+
+#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
+#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
+#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
+#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
+#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
+#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
+#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
+#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
+#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
+#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
+#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
+#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
+#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
+#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
+#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
+#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
+#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
+#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
+#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
+ (SUNXI_MMC_RINT_RESP_ERROR | \
+ SUNXI_MMC_RINT_RESP_CRC_ERROR | \
+ SUNXI_MMC_RINT_DATA_CRC_ERROR | \
+ SUNXI_MMC_RINT_RESP_TIMEOUT | \
+ SUNXI_MMC_RINT_DATA_TIMEOUT | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
+ SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
+ SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
+ SUNXI_MMC_RINT_START_BIT_ERROR | \
+ SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
+ (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
+ SUNXI_MMC_RINT_DATA_OVER | \
+ SUNXI_MMC_RINT_COMMAND_DONE | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+
+#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
+#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
+#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
+#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
+#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
+#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
+#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
+#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
+
+#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
+
+#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
+#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
+#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
+
+#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
+#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
+
+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
+#define SUNXI_MMC_COMMON_RESET (1 << 18)
+
+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+
+#endif /* _SUNXI_MMC_H */

72
package/boot/uboot-d1/patches/0020-pinctrl-sunxi-Add-support-for-the-D1.patch Normal file
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@@ -0,0 +1,72 @@
From fdf871a6089ee2f56439880b69d33a7d0d707d15 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 28 Aug 2021 22:24:28 -0500
Subject: [PATCH 20/90] pinctrl: sunxi: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/pinctrl/sunxi/Kconfig | 5 +++++
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 31 +++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -89,6 +89,11 @@ config PINCTRL_SUN9I_A80_R
default MACH_SUN9I
select PINCTRL_SUNXI
+config PINCTRL_SUN20I_D1
+ bool "Support for the Allwinner D1 PIO"
+ default TARGET_SUN20I_D1
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN50I_A64
bool "Support for the Allwinner A64 PIO"
default MACH_SUN50I
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -588,6 +588,31 @@ static const struct sunxi_pinctrl_desc _
.num_banks = 3,
};
+static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+ { "emac", 8 }, /* PE0-PE15 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 4 }, /* PB10-PB11 */
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC2-PC7 */
+ { "spi0", 2 }, /* PC2-PC7 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 6 }, /* PB8-PB9 */
+#endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 7 }, /* PB0-PB1 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
+ .functions = sun20i_d1_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 7,
+};
+
static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
{ "emac", 4 }, /* PD8-PD23 */
{ "gpio_in", 0 },
@@ -849,6 +874,12 @@ static const struct udevice_id sunxi_pin
.data = (ulong)&sun9i_a80_r_pinctrl_desc,
},
#endif
+#ifdef CONFIG_PINCTRL_SUN20I_D1
+ {
+ .compatible = "allwinner,sun20i-d1-pinctrl",
+ .data = (ulong)&sun20i_d1_pinctrl_desc,
+ },
+#endif
#ifdef CONFIG_PINCTRL_SUN50I_A64
{
.compatible = "allwinner,sun50i-a64-pinctrl",

34
package/boot/uboot-d1/patches/0021-serial-ns16550-Enable-clocks-during-probe.patch Normal file
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@@ -0,0 +1,34 @@
From 8fde85b609273f8389178d4c0d066390a0e0773d Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 30 Oct 2022 14:56:10 -0500
Subject: [PATCH 21/90] serial: ns16550: Enable clocks during probe
If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/serial/ns16550.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -506,6 +506,7 @@ int ns16550_serial_probe(struct udevice
struct ns16550_plat *plat = dev_get_plat(dev);
struct ns16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
+ struct clk_bulk clk_bulk;
fdt_addr_t addr;
int ret;
@@ -524,6 +525,10 @@ int ns16550_serial_probe(struct udevice
if (!ret)
reset_deassert_bulk(&reset_bulk);
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret)
+ clk_enable_bulk(&clk_bulk);
+
com_port->plat = dev_get_plat(dev);
ns16550_init(com_port, -1);

28
package/boot/uboot-d1/patches/0022-fdt-Fix-bounds-check-in-devfdt_get_addr_index.patch Normal file
View File

@@ -0,0 +1,28 @@
From 0e4edc3a01f179337bb0bd0d31855dbce338a23e Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 30 Oct 2022 14:53:45 -0500
Subject: [PATCH 22/90] fdt: Fix bounds check in devfdt_get_addr_index
reg must contain enough cells for the entire next address/size pair
after skipping `index` pairs. The previous code allows an out-of-bounds
read when na + ns > 1.
Series-to: Simon Glass <sjg@chromium.org>
Fixes: 69b41388ba45 ("dm: core: Add a new api to get indexed device address")
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/core/fdtaddr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -43,7 +43,7 @@ fdt_addr_t devfdt_get_addr_index(const s
}
reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
- if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
+ if (!reg || (len < ((index + 1) * sizeof(fdt32_t) * (na + ns)))) {
debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
}

25
package/boot/uboot-d1/patches/0023-Kconfig-Remove-an-impossible-condition.patch Normal file
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@@ -0,0 +1,25 @@
From 2d85df851c590b454749ac989a778bb226637bfc Mon Sep 17 00:00:00 2001
From: Zoltan HERPAI <wigyori@uid0.hu>
Date: Tue, 6 Jun 2023 15:08:39 +0000
Subject: [PATCH 23/90] Kconfig: Remove an impossible condition
ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
is impossible to satisfy.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
---
Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/Kconfig
+++ b/Kconfig
@@ -459,7 +459,7 @@ config BUILD_TARGET
default "u-boot-with-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
- ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+ RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL

33
package/boot/uboot-d1/patches/0024-binman-Prevent-entries-in-a-section-from-overlapping.patch Normal file
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@@ -0,0 +1,33 @@
From b7150f7dd885012868c94b29ac4fe6152c065a95 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 9 Oct 2021 10:43:56 -0500
Subject: [PATCH 24/90] binman: Prevent entries in a section from overlapping
Currently, if the "offset" property is given for an entry, the section's
running offset is completely ignored. This causes entries to overlap if
the provided offset is less than the size of the entries earlier in the
section. Avoid the overlap by only using the provided offset when it is
greater than the running offset.
The motivation for this change is the rule used by SPL to find U-Boot on
sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
tools/binman/entry.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -483,7 +483,9 @@ class Entry(object):
if self.offset_unset:
self.Raise('No offset set with offset-unset: should another '
'entry provide this correct offset?')
- self.offset = tools.align(offset, self.align)
+ elif self.offset > offset:
+ offset = self.offset
+ self.offset = tools.align(offset, self.align)
needed = self.pad_before + self.contents_size + self.pad_after
needed = tools.align(needed, self.align_size)
size = self.size

192
package/boot/uboot-d1/patches/0025-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch Normal file
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@@ -0,0 +1,192 @@
From b641ca5f4d272b83ef77ebcf5c75678cf139c69a Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 17 Apr 2021 13:33:54 -0500
Subject: [PATCH 25/90] sunxi: binman: Enable SPL FIT loading for 32-bit SoCs
Now that Crust (SCP firmware) has support for H3, we need a FIT image to
load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0
hotplug. Let's first enable FIT support before adding extra firmware.
Update the binman description to work on either 32-bit or 64-bit SoCs:
- Make BL31 optional, since it is not used on 32-bit SoCs (though BL32
may be used in the future).
- Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on
some boards is still only 24 KiB large even with FIT support enabled.
CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616.
FIT unlocks more features (signatures, multiple DTBs, etc.), so enable
it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs
SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere.
Cover-letter:
sunxi: SPL FIT support for 32-bit sunxi SoCs
This series makes the necessary changes so 32-bit sunxi SoCs can load
additional device trees or firmware from SPL along with U-Boot proper.
There was no existing binman entry property that put the FIT at the
right offset. The minimum offset is 32k, but this matches neither the
SPL size (which is no more than 24k on some SoCs) nor the FIT alignment
(which is 512 bytes in practice due to SPL size constraints). So instead
of adding a new property, I fixed what is arguably a bug in the offset
property -- though this strategy will not work if someone is
intentionally creating overlapping entries.
END
Series-to: sunxi
Series-to: sjg
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/Kconfig | 1 +
arch/arm/dts/sunxi-u-boot.dtsi | 46 ++++++++++++++++++++++------------
common/spl/Kconfig | 9 +++----
3 files changed, 35 insertions(+), 21 deletions(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1135,6 +1135,7 @@ config ARCH_SUNXI
imply SPL_GPIO
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_LOAD_FIT
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,13 +1,19 @@
#include <config.h>
-#ifdef CONFIG_MACH_SUN50I_H6
-#define BL31_ADDR 0x104000
-#define SCP_ADDR 0x114000
-#elif defined(CONFIG_MACH_SUN50I_H616)
-#define BL31_ADDR 0x40000000
+#ifdef CONFIG_ARM64
+#define ARCH "arm64"
#else
-#define BL31_ADDR 0x44000
-#define SCP_ADDR 0x50000
+#define ARCH "arm"
+#endif
+
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+#define BL31_ADDR 0x00044000
+#define SCP_ADDR 0x00050000
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#define BL31_ADDR 0x00104000
+#define SCP_ADDR 0x00114000
+#elif defined(CONFIG_MACH_SUN50I_H616)
+#define BL31_ADDR 0x40000000
#endif
/ {
@@ -34,30 +40,33 @@
filename = "spl/sunxi-spl.bin";
};
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_SPL_LOAD_FIT
fit {
- description = "Configuration to load ATF before U-Boot";
+ description = "Configuration to load U-Boot and firmware";
+ offset = <32768>;
#address-cells = <1>;
fit,fdt-list = "of-list";
images {
uboot {
- description = "U-Boot (64-bit)";
+ description = "U-Boot";
type = "standalone";
os = "u-boot";
- arch = "arm64";
+ arch = ARCH;
compression = "none";
load = <CONFIG_TEXT_BASE>;
+ entry = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
};
};
+#ifdef BL31_ADDR
atf {
description = "ARM Trusted Firmware";
type = "firmware";
os = "arm-trusted-firmware";
- arch = "arm64";
+ arch = ARCH;
compression = "none";
load = <BL31_ADDR>;
entry = <BL31_ADDR>;
@@ -67,6 +76,7 @@
missing-msg = "atf-bl31-sunxi";
};
};
+#endif
#ifdef SCP_ADDR
scp {
@@ -95,19 +105,23 @@
@config-SEQ {
description = "NAME";
+#ifdef BL31_ADDR
firmware = "atf";
-#ifndef SCP_ADDR
- loadables = "uboot";
#else
- loadables = "scp", "uboot";
+ firmware = "uboot";
+#endif
+ loadables =
+#ifdef SCP_ADDR
+ "scp",
#endif
+ "uboot";
fdt = "fdt-SEQ";
};
};
};
#else
u-boot-img {
- offset = <CONFIG_SPL_PAD_TO>;
+ offset = <32768>;
};
#endif
};
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -76,12 +76,12 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
config SPL_MAX_SIZE
hex "Maximum size of the SPL image, excluding BSS"
+ default 0x37fa0 if MACH_SUN50I_H616
default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
+ default 0x25fa0 if MACH_SUN50I_H6
default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
- default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
- default 0xbfa0 if MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
default 0x10000 if ASPEED_AST2600
@@ -97,7 +97,7 @@ config SPL_PAD_TO
default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
default 0x10000 if ARCH_KEYSTONE
- default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616
+ default 0x0 if ARCH_SUNXI
default 0x0 if ARCH_MTMIPS
default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE
default SPL_MAX_SIZE
@@ -575,8 +575,7 @@ config SPL_MD5
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
- default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
- default y if ARCH_IMX8M || ARCH_IMX9
+ default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI
help
Enable this to reduce the size of the FIT image loading code
in SPL, if space for the SPL binary is very tight.

51
package/boot/uboot-d1/patches/0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch Normal file
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@@ -0,0 +1,51 @@
From ca1e6f4491981432c3e88441131c8e25067da95e Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 9 Oct 2021 22:00:22 -0500
Subject: [PATCH 26/90] sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
power itself off anyway. Instead, have it turn FIQs back on and continue
servicing SGIs from other cores.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/cpu/armv7/sunxi/psci.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -38,6 +38,15 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
+static inline u32 __secure cp15_read_mpidr(void)
+{
+ u32 val;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+ return val;
+}
+
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
{
psci_cpu_off_common();
- /* Ask CPU0 via SGI15 to pull the rug... */
- writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
- dsb();
+ if (cp15_read_mpidr() & 3) {
+ /* Ask CPU0 via SGI15 to pull the rug... */
+ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+ dsb();
+ } else {
+ /* Unmask FIQs to service SGI15. */
+ asm volatile ("cpsie f");
+ }
/* Wait to be turned off */
while (1)

295
package/boot/uboot-d1/patches/0027-clk-sunxi-Add-NAND-clocks-and-resets.patch Normal file
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@@ -0,0 +1,295 @@
From 2f48dfc23d612f6f1798ff761854fd3141d0671f Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 15 May 2022 21:29:22 -0500
Subject: [PATCH 27/90] clk: sunxi: Add NAND clocks and resets
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi/clk_a10.c | 2 ++
drivers/clk/sunxi/clk_a10s.c | 2 ++
drivers/clk/sunxi/clk_a23.c | 3 +++
drivers/clk/sunxi/clk_a31.c | 6 ++++++
drivers/clk/sunxi/clk_a64.c | 3 +++
drivers/clk/sunxi/clk_a80.c | 8 ++++++++
drivers/clk/sunxi/clk_a83t.c | 3 +++
drivers/clk/sunxi/clk_h3.c | 3 +++
drivers/clk/sunxi/clk_h6.c | 6 ++++++
drivers/clk/sunxi/clk_h616.c | 6 ++++++
drivers/clk/sunxi/clk_r40.c | 3 +++
11 files changed, 45 insertions(+)
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] =
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
+ [CLK_AHB_NAND] = GATE(0x060, BIT(13)),
[CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] =
[CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
[CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[]
[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_AHB_NAND] = GATE(0x060, BIT(13)),
[CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[]
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
[CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] =
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] =
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] =
[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
+ [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)),
+ [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)),
[CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] =
[CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
[CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
+ [CLK_NAND0] = GATE(0x080, BIT(31)),
+ [CLK_NAND1] = GATE(0x084, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
[RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
[RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
+ [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)),
+ [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)),
[RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
[RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
[RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gat
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
@@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gat
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -14,12 +14,18 @@
#include <linux/bitops.h>
static const struct ccu_clk_gate a80_gates[] = {
+ [CLK_NAND0_0] = GATE(0x400, BIT(31)),
+ [CLK_NAND0_1] = GATE(0x404, BIT(31)),
+ [CLK_NAND1_0] = GATE(0x408, BIT(31)),
+ [CLK_NAND1_1] = GATE(0x40c, BIT(31)),
[CLK_SPI0] = GATE(0x430, BIT(31)),
[CLK_SPI1] = GATE(0x434, BIT(31)),
[CLK_SPI2] = GATE(0x438, BIT(31)),
[CLK_SPI3] = GATE(0x43c, BIT(31)),
[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
+ [CLK_BUS_NAND0] = GATE(0x580, BIT(12)),
+ [CLK_BUS_NAND1] = GATE(0x580, BIT(13)),
[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
@@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gat
static const struct ccu_reset a80_resets[] = {
[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
+ [RST_BUS_NAND0] = RESET(0x5a0, BIT(12)),
+ [RST_BUS_NAND1] = RESET(0x5a0, BIT(13)),
[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a83t_gates[]
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
@@ -36,6 +37,7 @@ static struct ccu_clk_gate a83t_gates[]
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -54,6 +56,7 @@ static struct ccu_reset a83t_resets[] =
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] =
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
@@ -44,6 +45,7 @@ static struct ccu_clk_gate h3_gates[] =
[CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -66,6 +68,7 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -18,6 +18,10 @@ static struct ccu_clk_gate h6_gates[] =
[CLK_APB1] = GATE_DUMMY,
+ [CLK_NAND0] = GATE(0x810, BIT(31)),
+ [CLK_NAND1] = GATE(0x814, BIT(31)),
+ [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
@@ -58,6 +62,8 @@ static struct ccu_clk_gate h6_gates[] =
};
static struct ccu_reset h6_resets[] = {
+ [RST_BUS_NAND] = RESET(0x82c, BIT(16)),
+
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -17,6 +17,10 @@ static struct ccu_clk_gate h616_gates[]
[CLK_APB1] = GATE_DUMMY,
+ [CLK_NAND0] = GATE(0x810, BIT(31)),
+ [CLK_NAND1] = GATE(0x814, BIT(31)),
+ [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
@@ -67,6 +71,8 @@ static struct ccu_clk_gate h616_gates[]
};
static struct ccu_reset h616_resets[] = {
+ [RST_BUS_NAND] = RESET(0x82c, BIT(16)),
+
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -18,6 +18,7 @@ static struct ccu_clk_gate r40_gates[] =
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
+ [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
@@ -48,6 +49,7 @@ static struct ccu_clk_gate r40_gates[] =
[CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
[CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
+ [CLK_NAND] = GATE(0x080, BIT(31)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
@@ -70,6 +72,7 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
+ [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),

120
package/boot/uboot-d1/patches/0028-pinctrl-sunxi-Add-NAND-pinmuxes.patch Normal file
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@@ -0,0 +1,120 @@
From 7be2405244565973cff0a40196bbed08df90f6a3 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Mon, 16 May 2022 00:31:36 -0500
Subject: [PATCH 28/90] pinctrl: sunxi: Add NAND pinmuxes
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -269,6 +269,7 @@ static const struct sunxi_pinctrl_functi
#endif
{ "mmc2", 3 }, /* PC6-PC15 */
{ "mmc3", 2 }, /* PI4-PI9 */
+ { "nand0", 2 }, /* PC0-PC24 */
{ "spi0", 3 }, /* PC0-PC2, PC23 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 4 }, /* PF2-PF4 */
@@ -293,6 +294,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG3-PG8 */
{ "mmc2", 3 }, /* PC6-PC15 */
+ { "nand0", 2 }, /* PC0-PC19 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 4 }, /* PF2-PF4 */
@@ -319,6 +321,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC6-PC15, PC24 */
{ "mmc3", 4 }, /* PC6-PC15, PC24 */
+ { "nand0", 2 }, /* PC0-PC26 */
{ "spi0", 3 }, /* PC0-PC2, PC27 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -363,6 +366,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc1", 4 }, /* PG0-PG5 */
#endif
{ "mmc2", 3 }, /* PC5-PC15, PC24 */
+ { "nand0", 2 }, /* PC0-PC24 */
{ "spi0", 3 }, /* PC0-PC2, PC23 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 4 }, /* PF2-PF4 */
@@ -386,6 +390,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC5-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -424,6 +429,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC5-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -450,6 +456,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC5-PC16 */
+ { "nand0", 2 }, /* PC0-PC18 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -491,6 +498,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC5-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -557,6 +565,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC6-PC16 */
+ { "nand0", 2 }, /* PC0-PC18 */
{ "spi0", 3 }, /* PC0-PC2, PC19 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 4 }, /* PF2-PF4 */
@@ -622,6 +631,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC1-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "pwm", 2 }, /* PD22 */
{ "spi0", 4 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -664,6 +674,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC1-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 3 }, /* PC0-PC3 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -690,6 +701,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC1-PC14 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 4 }, /* PC0-PC7 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */
@@ -728,6 +740,7 @@ static const struct sunxi_pinctrl_functi
{ "mmc0", 2 }, /* PF0-PF5 */
{ "mmc1", 2 }, /* PG0-PG5 */
{ "mmc2", 3 }, /* PC0-PC16 */
+ { "nand0", 2 }, /* PC0-PC16 */
{ "spi0", 4 }, /* PC0-PC7, PC15-PC16 */
#if IS_ENABLED(CONFIG_UART0_PORT_F)
{ "uart0", 3 }, /* PF2-PF4 */

32
package/boot/uboot-d1/patches/0029-mtd-nand-sunxi-Remove-an-unnecessary-check.patch Normal file
View File

@@ -0,0 +1,32 @@
From 8e793af8598a8429c9dc0f096c72a92adb360a57 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 15 May 2022 21:51:47 -0500
Subject: [PATCH 29/90] mtd: nand: sunxi: Remove an unnecessary check
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/mtd/nand/raw/sunxi_nand.c | 10 ----------
1 file changed, 10 deletions(-)
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -1767,16 +1767,6 @@ static int sunxi_nand_chips_init(int nod
int ret, i = 0;
for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
- nand_node = fdt_next_subnode(blob, nand_node))
- i++;
-
- if (i > 8) {
- dev_err(nfc->dev, "too many NAND chips: %d (max = 8)\n", i);
- return -EINVAL;
- }
-
- i = 0;
- for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
nand_node = fdt_next_subnode(blob, nand_node)) {
ret = sunxi_nand_chip_init(nand_node, nfc, i++);
if (ret)

203
package/boot/uboot-d1/patches/0030-mtd-nand-sunxi-Convert-from-fdtdec-to-ofnode.patch Normal file
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@@ -0,0 +1,203 @@
From 61b63cbb3526e19a0e299f95a3435a237c7c4b4b Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 15 May 2022 21:54:25 -0500
Subject: [PATCH 30/90] mtd: nand: sunxi: Convert from fdtdec to ofnode
As a first step toward converting this driver to the driver model, use
the ofnode abstraction to replace direct references to the FDT blob.
Using ofnode_read_u32_index removes an extra pair of loops and makes the
allwinner,rb property optional, matching the devicetree binding.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/mtd/nand/raw/sunxi_nand.c | 73 +++++++++++--------------------
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
3 files changed, 26 insertions(+), 49 deletions(-)
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -25,11 +25,10 @@
*/
#include <common.h>
-#include <fdtdec.h>
+#include <dm.h>
#include <malloc.h>
#include <memalign.h>
#include <nand.h>
-#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
@@ -45,8 +44,6 @@
#include <asm/gpio.h>
#include <asm/arch/clock.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define NFC_REG_CTL 0x0000
#define NFC_REG_ST 0x0004
#define NFC_REG_INT 0x0008
@@ -1605,19 +1602,18 @@ static int sunxi_nand_ecc_init(struct mt
return 0;
}
-static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
+static int sunxi_nand_chip_init(ofnode np, struct sunxi_nfc *nfc, int devnum)
{
const struct nand_sdr_timings *timings;
- const void *blob = gd->fdt_blob;
struct sunxi_nand_chip *chip;
struct mtd_info *mtd;
struct nand_chip *nand;
int nsels;
int ret;
int i;
- u32 cs[8], rb[8];
+ u32 tmp;
- if (!fdt_getprop(blob, node, "reg", &nsels))
+ if (!ofnode_get_property(np, "reg", &nsels))
return -EINVAL;
nsels /= sizeof(u32);
@@ -1638,25 +1634,12 @@ static int sunxi_nand_chip_init(int node
chip->selected = -1;
for (i = 0; i < nsels; i++) {
- cs[i] = -1;
- rb[i] = -1;
- }
-
- ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
- if (ret) {
- dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
- return ret;
- }
-
- ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
- nsels);
- if (ret) {
- dev_err(nfc->dev, "could not retrieve reg property: %d\n", ret);
- return ret;
- }
-
- for (i = 0; i < nsels; i++) {
- int tmp = cs[i];
+ ret = ofnode_read_u32_index(np, "reg", i, &tmp);
+ if (ret) {
+ dev_err(nfc->dev, "could not retrieve reg property: %d\n",
+ ret);
+ return ret;
+ }
if (tmp > NFC_MAX_CS) {
dev_err(nfc->dev,
@@ -1671,15 +1654,14 @@ static int sunxi_nand_chip_init(int node
chip->sels[i].cs = tmp;
- tmp = rb[i];
- if (tmp >= 0 && tmp < 2) {
+ if (!ofnode_read_u32_index(np, "allwinner,rb", i, &tmp) &&
+ tmp < 2) {
chip->sels[i].rb.type = RB_NATIVE;
chip->sels[i].rb.info.nativeid = tmp;
} else {
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
- "rb-gpios", i,
- &chip->sels[i].rb.info.gpio,
- GPIOD_IS_IN);
+ ret = gpio_request_by_name_nodev(np, "rb-gpios", i,
+ &chip->sels[i].rb.info.gpio,
+ GPIOD_IS_IN);
if (ret)
chip->sels[i].rb.type = RB_GPIO;
else
@@ -1711,7 +1693,7 @@ static int sunxi_nand_chip_init(int node
* in the DT.
*/
nand->ecc.mode = NAND_ECC_HW;
- nand->flash_node = offset_to_ofnode(node);
+ nand->flash_node = np;
nand->select_chip = sunxi_nfc_select_chip;
nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
nand->read_buf = sunxi_nfc_read_buf;
@@ -1760,15 +1742,13 @@ static int sunxi_nand_chip_init(int node
return 0;
}
-static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
+static int sunxi_nand_chips_init(ofnode node, struct sunxi_nfc *nfc)
{
- const void *blob = gd->fdt_blob;
- int nand_node;
+ ofnode nand_np;
int ret, i = 0;
- for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
- nand_node = fdt_next_subnode(blob, nand_node)) {
- ret = sunxi_nand_chip_init(nand_node, nfc, i++);
+ ofnode_for_each_subnode(nand_np, node) {
+ ret = sunxi_nand_chip_init(nand_np, nfc, i++);
if (ret)
return ret;
}
@@ -1794,10 +1774,9 @@ static void sunxi_nand_chips_cleanup(str
void sunxi_nand_init(void)
{
- const void *blob = gd->fdt_blob;
struct sunxi_nfc *nfc;
- fdt_addr_t regs;
- int node;
+ phys_addr_t regs;
+ ofnode node;
int ret;
nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
@@ -1808,18 +1787,18 @@ void sunxi_nand_init(void)
init_waitqueue_head(&nfc->controller.wq);
INIT_LIST_HEAD(&nfc->chips);
- node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
- if (node < 0) {
+ node = ofnode_by_compatible(ofnode_null(), "allwinner,sun4i-a10-nand");
+ if (!ofnode_valid(node)) {
pr_err("unable to find nfc node in device tree\n");
goto err;
}
- if (!fdtdec_get_is_enabled(blob, node)) {
+ if (!ofnode_is_enabled(node)) {
pr_err("nfc disabled in device tree\n");
goto err;
}
- regs = fdtdec_get_addr(blob, node, "reg");
+ regs = ofnode_get_addr(node);
if (regs == FDT_ADDR_T_NONE) {
pr_err("unable to find nfc address in device tree\n");
goto err;
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -187,7 +187,6 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
- COMPAT_SUNXI_NAND, /* SUNXI NAND controller */
COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */
COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */
COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* SoCFPGA hps2fpga bridge */
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -64,7 +64,6 @@ static const char * const compat_names[C
COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
- COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),

172
package/boot/uboot-d1/patches/0031-mtd-nand-sunxi-Convert-to-the-driver-model.patch Normal file
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@@ -0,0 +1,172 @@
From 3411a9a1be9a8d8fef236a81edbce2a1a8218a32 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Mon, 16 May 2022 00:16:48 -0500
Subject: [PATCH 31/90] mtd: nand: sunxi: Convert to the driver model
Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
board/sunxi/board.c | 5 +-
drivers/mtd/nand/raw/sunxi_nand.c | 81 ++++++++++++++++++-------------
2 files changed, 49 insertions(+), 37 deletions(-)
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -311,7 +311,7 @@ int dram_init(void)
return 0;
}
-#if defined(CONFIG_NAND_SUNXI)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
static void nand_pinmux_setup(void)
{
unsigned int pin;
@@ -347,9 +347,6 @@ void board_nand_init(void)
{
nand_pinmux_setup();
nand_clock_setup();
-#ifndef CONFIG_SPL_BUILD
- sunxi_nand_init();
-#endif
}
#endif /* CONFIG_NAND_SUNXI */
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -24,11 +24,13 @@
* GNU General Public License for more details.
*/
+#include <clk.h>
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <memalign.h>
#include <nand.h>
+#include <reset.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
@@ -260,7 +262,7 @@ static inline struct sunxi_nand_chip *to
* NAND Controller structure: stores sunxi NAND controller information
*
* @controller: base controller structure
- * @dev: parent device (used to print error messages)
+ * @dev: DM device (used to print error messages)
* @regs: NAND controller registers
* @ahb_clk: NAND Controller AHB clock
* @mod_clk: NAND Controller mod clock
@@ -273,7 +275,7 @@ static inline struct sunxi_nand_chip *to
*/
struct sunxi_nfc {
struct nand_hw_control controller;
- struct device *dev;
+ struct udevice *dev;
void __iomem *regs;
struct clk *ahb_clk;
struct clk *mod_clk;
@@ -1772,54 +1774,67 @@ static void sunxi_nand_chips_cleanup(str
}
#endif /* __UBOOT__ */
-void sunxi_nand_init(void)
+static int sunxi_nand_probe(struct udevice *dev)
{
- struct sunxi_nfc *nfc;
- phys_addr_t regs;
- ofnode node;
+ struct sunxi_nfc *nfc = dev_get_priv(dev);
+ struct reset_ctl_bulk rst_bulk;
+ struct clk_bulk clk_bulk;
int ret;
- nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
- if (!nfc)
- return;
-
+ nfc->dev = dev;
spin_lock_init(&nfc->controller.lock);
init_waitqueue_head(&nfc->controller.wq);
INIT_LIST_HEAD(&nfc->chips);
- node = ofnode_by_compatible(ofnode_null(), "allwinner,sun4i-a10-nand");
- if (!ofnode_valid(node)) {
- pr_err("unable to find nfc node in device tree\n");
- goto err;
- }
-
- if (!ofnode_is_enabled(node)) {
- pr_err("nfc disabled in device tree\n");
- goto err;
- }
-
- regs = ofnode_get_addr(node);
- if (regs == FDT_ADDR_T_NONE) {
- pr_err("unable to find nfc address in device tree\n");
- goto err;
- }
+ nfc->regs = dev_read_addr_ptr(dev);
+ if (!nfc->regs)
+ return -EINVAL;
- nfc->regs = (void *)regs;
+ ret = reset_get_bulk(dev, &rst_bulk);
+ if (!ret)
+ reset_deassert_bulk(&rst_bulk);
+
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret)
+ clk_enable_bulk(&clk_bulk);
ret = sunxi_nfc_rst(nfc);
if (ret)
- goto err;
+ return ret;
- ret = sunxi_nand_chips_init(node, nfc);
+ ret = sunxi_nand_chips_init(dev_ofnode(dev), nfc);
if (ret) {
- dev_err(nfc->dev, "failed to init nand chips\n");
- goto err;
+ dev_err(dev, "failed to init nand chips\n");
+ return ret;
}
- return;
+ return 0;
+}
-err:
- kfree(nfc);
+static const struct udevice_id sunxi_nand_ids[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-nand",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(sunxi_nand) = {
+ .name = "sunxi_nand",
+ .id = UCLASS_MTD,
+ .of_match = sunxi_nand_ids,
+ .probe = sunxi_nand_probe,
+ .priv_auto = sizeof(struct sunxi_nfc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(sunxi_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize sunxi NAND controller: %d\n", ret);
}
MODULE_LICENSE("GPL v2");

31
package/boot/uboot-d1/patches/0032-sunxi-DT-H6-Add-USB3-to-Pine-H64-DTS.patch Normal file
View File

@@ -0,0 +1,31 @@
From 6fdd7e8d2758f69f5c8e3cb2a0f06da47c1f2cb4 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 17 Apr 2021 14:21:45 -0500
Subject: [PATCH 32/90] sunxi: DT: H6: Add USB3 to Pine H64 DTS
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun50i-h6-pine-h64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -89,6 +89,10 @@
status = "okay";
};
+&dwc3 {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -332,3 +336,7 @@
usb3_vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
+
+&usb3phy {
+ status = "okay";
+};

441
package/boot/uboot-d1/patches/0033-tools-mkimage-Add-Allwinner-TOC1-support.patch Normal file
View File

@@ -0,0 +1,441 @@
From ff0e952a3a380ba191375d5f68609cdbe026d535 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 7 Aug 2021 19:55:20 -0500
Subject: [PATCH 33/90] tools: mkimage: Add Allwinner TOC1 support
TOC1 is an container format used by Allwinner's boot0 that can hold
multiple images. It supports encryption and signatures, but that
functionality is not implemented, only the basic "non-secure" subset.
A config file is used to provide the list of data files to include. Its
path is passed as the argument to "-d". It contains sections of the
following form:
[name]
file = /path/to/file
addr = 0x12345678
Specific well-known names, such as "dtb", "opensbi", and "u-boot", are
used by the bootloader to distinguish the items inside the image.
Cover-letter:
tools: mkimage: Add Allwinner TOC1 support
The SPL port for the Allwinner D1 RISC-V SoC will probably take a while
longer than porting U-Boot proper, as none of the relevant drivers are
set up for DM in SPL. In the meantime, we are using[1][2] a fork[3] of
Allwinner's boot0 loader, which they also call "spl" in their BSP. boot0
uses this TOC1 image format.
The vendor tools for generating TOC1 images require a binary config file
generated by their FEX compiler. Instead of trying to support that, I
made up a simple human-readable config file format. I didn't see any
existing platform-agnostic parser for multi-image containers in mkimage.
I am sending this as RFC because it is only of temporary/limited use.
It only works with one specific fork of boot0 which was modified to
"behave" (the the original vendor version monkey-patches a custom header
inside the U-Boot image during boot). So it will be obsolete once U-Boot
SPL is ported. And it is Yet Another Image Format. On the other hand, it
does work, and it is currently being used.
[1]: https://linux-sunxi.org/Allwinner_Nezha#U-Boot
[2]: https://fedoraproject.org/wiki/Architectures/RISC-V/Allwinner
[3]: https://github.com/smaeul/sun20i_d1_spl
END
Series-prefix: RFC
Series-to: sunxi
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
boot/image.c | 1 +
include/image.h | 1 +
include/sunxi_image.h | 26 ++++
tools/Makefile | 1 +
tools/sunxi_toc1.c | 318 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 347 insertions(+)
create mode 100644 tools/sunxi_toc1.c
--- a/boot/image.c
+++ b/boot/image.c
@@ -180,6 +180,7 @@ static const table_entry_t uimage_type[]
{ IH_TYPE_COPRO, "copro", "Coprocessor Image"},
{ IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" },
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" },
+ { IH_TYPE_SUNXI_TOC1, "sunxi_toc1", "Allwinner TOC1 Boot Image" },
{ -1, "", "", },
};
--- a/include/image.h
+++ b/include/image.h
@@ -229,6 +229,7 @@ enum image_type_t {
IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
+ IH_TYPE_SUNXI_TOC1, /* Allwinner TOC1 Boot Image */
IH_TYPE_COUNT, /* Number of image types */
};
--- a/include/sunxi_image.h
+++ b/include/sunxi_image.h
@@ -116,4 +116,30 @@ struct __packed toc0_item_info {
#define TOC0_ITEM_INFO_NAME_KEY 0x00010303
#define TOC0_ITEM_INFO_END "IIE;"
+struct __packed toc1_main_info {
+ uint8_t name[16];
+ __le32 magic;
+ __le32 checksum;
+ __le32 serial;
+ __le32 status;
+ __le32 num_items;
+ __le32 length;
+ __le32 major_version;
+ __le32 minor_version;
+ __le32 reserved[3];
+ uint8_t end[4];
+};
+
+struct __packed toc1_item_info {
+ uint8_t name[64];
+ __le32 offset;
+ __le32 length;
+ __le32 encryption;
+ __le32 type;
+ __le32 load_addr;
+ __le32 index;
+ __le32 reserved[69];
+ uint8_t end[4];
+};
+
#endif
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -132,6 +132,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
sunxi_egon.o \
+ sunxi_toc1.o \
lib/crc16-ccitt.o \
lib/hash-checksum.o \
lib/sha1.o \
--- /dev/null
+++ b/tools/sunxi_toc1.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Arm Ltd.
+ * (C) Copyright 2020-2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <image.h>
+#include <sunxi_image.h>
+
+#include "imagetool.h"
+#include "mkimage.h"
+
+#define SECTOR_SIZE 512
+
+struct item_desc {
+ const char *name;
+ const char *file;
+ unsigned long addr;
+ long length;
+};
+
+static uint32_t toc1_header_length(uint32_t num_items)
+{
+ return ALIGN(sizeof(struct toc1_main_info) +
+ sizeof(struct toc1_item_info) * num_items, SECTOR_SIZE);
+}
+
+static int toc1_parse_cfg(const char *file, struct item_desc **desc,
+ uint32_t *main_length, uint32_t *num_items)
+{
+ struct item_desc *descs = NULL;
+ int ret = EXIT_FAILURE;
+ FILE *cfg, *fp = NULL;
+ uint32_t ndescs = 0;
+ char *line = NULL;
+ size_t len = 0;
+
+ *desc = NULL;
+ *main_length = 0;
+ *num_items = 0;
+
+ cfg = fopen(file, "r");
+ if (!cfg)
+ return ret;
+
+ while (getline(&line, &len, cfg) > 0) {
+ char *end, *s;
+
+ if (line[0] == '[') {
+ s = line + 1;
+ end = strchr(s, ']');
+ if (!end || end[1] != '\n')
+ goto err;
+ end[0] = '\0';
+
+ ndescs++;
+ descs = reallocarray(descs, ndescs, sizeof(*descs));
+ if (!descs)
+ goto err;
+
+ descs[ndescs - 1].name = strdup(s);
+ } else if (line[0] != '#' && line[0] != '\n') {
+ s = strchr(line, '=');
+ if (!s)
+ goto err;
+ while ((++s)[0] == ' ')
+ ;
+ end = strchr(s, '\n');
+ if (!end)
+ goto err;
+ end[0] = '\0';
+
+ if (!strncmp(line, "file", strlen("file"))) {
+ fp = fopen(s, "rb");
+ if (!fp)
+ goto err;
+ if (fseek(fp, 0, SEEK_END) < 0)
+ goto err;
+ descs[ndescs - 1].file = strdup(s);
+ descs[ndescs - 1].length = ftell(fp);
+ *main_length += ALIGN(descs[ndescs - 1].length,
+ SECTOR_SIZE);
+ fclose(fp);
+ fp = NULL;
+ } else if (!strncmp(line, "addr", strlen("addr"))) {
+ descs[ndescs - 1].addr = strtoul(s, NULL, 0);
+ } else {
+ goto err;
+ }
+ }
+ }
+
+ *desc = descs;
+ *main_length += toc1_header_length(ndescs);
+ *num_items = ndescs;
+
+ ret = EXIT_SUCCESS;
+
+err:
+ if (fp)
+ fclose(fp);
+ if (ret)
+ free(descs);
+ free(line);
+ fclose(cfg);
+
+ return ret;
+}
+
+static int toc1_create(uint8_t *buf, uint32_t len,
+ const struct item_desc *desc, uint32_t num_items)
+{
+ struct toc1_main_info *main = (void *)buf;
+ struct toc1_item_info *item = (void *)(main + 1);
+ uint32_t item_offset, item_length;
+ uint32_t *buf32 = (void *)buf;
+ int ret = EXIT_FAILURE;
+ uint32_t checksum = 0;
+ FILE *fp = NULL;
+ int i;
+
+ /* Create the main TOC1 header. */
+ main->magic = cpu_to_le32(TOC0_MAIN_INFO_MAGIC);
+ main->checksum = cpu_to_le32(BROM_STAMP_VALUE);
+ main->num_items = cpu_to_le32(num_items);
+ memcpy(main->end, TOC0_MAIN_INFO_END, sizeof(main->end));
+
+ item_offset = 0;
+ item_length = toc1_header_length(num_items);
+
+ for (i = 0; i < num_items; ++i, ++item, ++desc) {
+ item_offset = item_offset + item_length;
+ item_length = desc->length;
+
+ /* Create the item header. */
+ memcpy(item->name, desc->name,
+ strnlen(desc->name, sizeof(item->name)));
+ item->offset = cpu_to_le32(item_offset);
+ item->length = cpu_to_le32(item_length);
+ item->load_addr = cpu_to_le32(desc->addr);
+ memcpy(item->end, TOC0_ITEM_INFO_END, sizeof(item->end));
+
+ /* Read in the data. */
+ fp = fopen(desc->file, "rb");
+ if (!fp)
+ goto err;
+ if (!fread(buf + item_offset, item_length, 1, fp))
+ goto err;
+ fclose(fp);
+ fp = NULL;
+
+ /* Pad the sectors with 0xff to be flash-friendly. */
+ item_offset = item_offset + item_length;
+ item_length = ALIGN(item_offset, SECTOR_SIZE) - item_offset;
+ memset(buf + item_offset, 0xff, item_length);
+ }
+
+ /* Fill in the total padded file length. */
+ item_offset = item_offset + item_length;
+ main->length = cpu_to_le32(item_offset);
+
+ /* Verify enough space was provided when creating the image. */
+ assert(len >= item_offset);
+
+ /* Calculate the checksum. Yes, it's that simple. */
+ for (i = 0; i < item_offset / 4; ++i)
+ checksum += le32_to_cpu(buf32[i]);
+ main->checksum = cpu_to_le32(checksum);
+
+ ret = EXIT_SUCCESS;
+
+err:
+ if (fp)
+ fclose(fp);
+
+ return ret;
+}
+
+static int toc1_verify(const uint8_t *buf, uint32_t len)
+{
+ const struct toc1_main_info *main = (void *)buf;
+ const struct toc1_item_info *item = (void *)(main + 1);
+ uint32_t checksum = BROM_STAMP_VALUE;
+ uint32_t main_length, num_items;
+ uint32_t *buf32 = (void *)buf;
+ int ret = EXIT_FAILURE;
+ int i;
+
+ num_items = le32_to_cpu(main->num_items);
+ main_length = le32_to_cpu(main->length);
+
+ if (len < main_length || main_length < toc1_header_length(num_items))
+ goto err;
+
+ /* Verify the main header. */
+ if (le32_to_cpu(main->magic) != TOC0_MAIN_INFO_MAGIC)
+ goto err;
+ /* Verify the checksum without modifying the buffer. */
+ for (i = 0; i < main_length / 4; ++i)
+ checksum += le32_to_cpu(buf32[i]);
+ if (checksum != 2 * le32_to_cpu(main->checksum))
+ goto err;
+ /* The length must be at least 512 byte aligned. */
+ if (main_length % SECTOR_SIZE)
+ goto err;
+ if (memcmp(main->end, TOC0_MAIN_INFO_END, sizeof(main->end)))
+ goto err;
+
+ /* Verify each item header. */
+ for (i = 0; i < num_items; ++i, ++item)
+ if (memcmp(item->end, TOC0_ITEM_INFO_END, sizeof(item->end)))
+ goto err;
+
+ ret = EXIT_SUCCESS;
+
+err:
+ return ret;
+}
+
+static int toc1_check_params(struct image_tool_params *params)
+{
+ if (!params->dflag)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int toc1_verify_header(unsigned char *buf, int image_size,
+ struct image_tool_params *params)
+{
+ return toc1_verify(buf, image_size);
+}
+
+static void toc1_print_header(const void *buf)
+{
+ const struct toc1_main_info *main = buf;
+ const struct toc1_item_info *item = (void *)(main + 1);
+ uint32_t head_length, main_length, num_items;
+ uint32_t item_offset, item_length, item_addr;
+ int i;
+
+ num_items = le32_to_cpu(main->num_items);
+ head_length = sizeof(*main) + num_items * sizeof(*item);
+ main_length = le32_to_cpu(main->length);
+
+ printf("Allwinner TOC1 Image\n"
+ "Size: %d bytes\n"
+ "Contents: %d items\n"
+ " 00000000:%08x Headers\n",
+ main_length, num_items, head_length);
+
+ for (i = 0; i < num_items; ++i, ++item) {
+ item_offset = le32_to_cpu(item->offset);
+ item_length = le32_to_cpu(item->length);
+ item_addr = le32_to_cpu(item->load_addr);
+
+ printf(" %08x:%08x => %08x %s\n",
+ item_offset, item_length, item_addr, item->name);
+ }
+}
+
+static void toc1_set_header(void *buf, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ /* Image is already written below. */
+}
+
+static int toc1_check_image_type(uint8_t type)
+{
+ return type == IH_TYPE_SUNXI_TOC1 ? 0 : 1;
+}
+
+static int toc1_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ uint32_t main_length, num_items;
+ struct item_desc *desc;
+ int ret;
+
+ /* This "header" contains the entire image. */
+ params->skipcpy = 1;
+
+ ret = toc1_parse_cfg(params->datafile, &desc, &main_length, &num_items);
+ if (ret)
+ exit(ret);
+
+ tparams->header_size = main_length;
+ tparams->hdr = calloc(tparams->header_size, 1);
+ if (!tparams->hdr)
+ exit(ret);
+
+ ret = toc1_create(tparams->hdr, tparams->header_size, desc, num_items);
+ if (ret)
+ exit(ret);
+
+ return 0;
+}
+
+U_BOOT_IMAGE_TYPE(
+ sunxi_toc1,
+ "Allwinner TOC1 Boot Image support",
+ 0,
+ NULL,
+ toc1_check_params,
+ toc1_verify_header,
+ toc1_print_header,
+ toc1_set_header,
+ NULL,
+ toc1_check_image_type,
+ NULL,
+ toc1_vrec_header
+);

33
package/boot/uboot-d1/patches/0034-phy-sun4i-usb-Do-not-drive-VBUS-with-external-VBUS-p.patch Normal file
View File

@@ -0,0 +1,33 @@
From 79f7d883d980beea9989d06f9fba4fcc0430176a Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Thu, 14 Jul 2022 22:14:38 -0500
Subject: [PATCH 34/90] phy: sun4i-usb: Do not drive VBUS with external VBUS
present
It is possible to use host-side USB with externally-provided VBUS. For
example, some USB OTG cables have an extra power input which powers
both the board and the USB peripheral.
To support this setup, skip enabling the VBUS switch/regulator if VBUS
voltage is already present. This behavior matches the Linux PHY driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -220,6 +220,12 @@ static int sun4i_usb_phy_power_on(struct
initial_usb_scan_delay = 0;
}
+ /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
+ if (phy->id == 0 && sun4i_usb_phy_vbus_detect(phy)) {
+ dev_warn(phy->dev, "External vbus detected, not enabling our own vbus\n");
+ return 0;
+ }
+
if (usb_phy->vbus) {
ret = regulator_set_enable(usb_phy->vbus, true);
if (ret && ret != -ENOSYS)

163
package/boot/uboot-d1/patches/0035-mtd-nand-sunxi-Pass-the-device-to-the-init-function.patch Normal file
View File

@@ -0,0 +1,163 @@
From 4bc5cec5361dd6a2ae3bd044c79a4b5227bb9627 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Mon, 16 May 2022 00:47:32 -0500
Subject: [PATCH 35/90] mtd: nand: sunxi: Pass the device to the init function
This more closely matches the U-Boot driver to the Linux version.
Series-to: sunxi
Cover-letter:
mtd: nand: sunxi: Convert to devicetree and the driver model
This series converts the sunxi NAND driver to get its resources (clocks,
resets, pins) from the devicetree, and probe using the driver model.
In addition to the immediate cleanup, this allows backporting more
patches (bugfixes, newer SoC support) from the Linux driver.
END
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/mtd/nand/raw/sunxi_nand.c | 39 ++++++++++++++++---------------
1 file changed, 20 insertions(+), 19 deletions(-)
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -1604,7 +1604,8 @@ static int sunxi_nand_ecc_init(struct mt
return 0;
}
-static int sunxi_nand_chip_init(ofnode np, struct sunxi_nfc *nfc, int devnum)
+static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc,
+ ofnode np, int devnum)
{
const struct nand_sdr_timings *timings;
struct sunxi_nand_chip *chip;
@@ -1620,7 +1621,7 @@ static int sunxi_nand_chip_init(ofnode n
nsels /= sizeof(u32);
if (!nsels || nsels > 8) {
- dev_err(nfc->dev, "invalid reg property size\n");
+ dev_err(dev, "invalid reg property size\n");
return -EINVAL;
}
@@ -1628,7 +1629,7 @@ static int sunxi_nand_chip_init(ofnode n
(nsels * sizeof(struct sunxi_nand_chip_sel)),
GFP_KERNEL);
if (!chip) {
- dev_err(nfc->dev, "could not allocate chip\n");
+ dev_err(dev, "could not allocate chip\n");
return -ENOMEM;
}
@@ -1638,19 +1639,19 @@ static int sunxi_nand_chip_init(ofnode n
for (i = 0; i < nsels; i++) {
ret = ofnode_read_u32_index(np, "reg", i, &tmp);
if (ret) {
- dev_err(nfc->dev, "could not retrieve reg property: %d\n",
+ dev_err(dev, "could not retrieve reg property: %d\n",
ret);
return ret;
}
if (tmp > NFC_MAX_CS) {
- dev_err(nfc->dev,
+ dev_err(dev,
"invalid reg value: %u (max CS = 7)\n", tmp);
return -EINVAL;
}
if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
- dev_err(nfc->dev, "CS %d already assigned\n", tmp);
+ dev_err(dev, "CS %d already assigned\n", tmp);
return -EINVAL;
}
@@ -1661,9 +1662,9 @@ static int sunxi_nand_chip_init(ofnode n
chip->sels[i].rb.type = RB_NATIVE;
chip->sels[i].rb.info.nativeid = tmp;
} else {
- ret = gpio_request_by_name_nodev(np, "rb-gpios", i,
- &chip->sels[i].rb.info.gpio,
- GPIOD_IS_IN);
+ ret = gpio_request_by_name(dev, "rb-gpios", i,
+ &chip->sels[i].rb.info.gpio,
+ GPIOD_IS_IN);
if (ret)
chip->sels[i].rb.type = RB_GPIO;
else
@@ -1674,7 +1675,7 @@ static int sunxi_nand_chip_init(ofnode n
timings = onfi_async_timing_mode_to_sdr_timings(0);
if (IS_ERR(timings)) {
ret = PTR_ERR(timings);
- dev_err(nfc->dev,
+ dev_err(dev,
"could not retrieve timings for ONFI mode 0: %d\n",
ret);
return ret;
@@ -1682,7 +1683,7 @@ static int sunxi_nand_chip_init(ofnode n
ret = sunxi_nand_chip_set_timings(nfc, chip, timings);
if (ret) {
- dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
+ dev_err(dev, "could not configure chip timings: %d\n", ret);
return ret;
}
@@ -1717,25 +1718,25 @@ static int sunxi_nand_chip_init(ofnode n
ret = sunxi_nand_chip_init_timings(nfc, chip);
if (ret) {
- dev_err(nfc->dev, "could not configure chip timings: %d\n", ret);
+ dev_err(dev, "could not configure chip timings: %d\n", ret);
return ret;
}
ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
if (ret) {
- dev_err(nfc->dev, "ECC init failed: %d\n", ret);
+ dev_err(dev, "ECC init failed: %d\n", ret);
return ret;
}
ret = nand_scan_tail(mtd);
if (ret) {
- dev_err(nfc->dev, "nand_scan_tail failed: %d\n", ret);
+ dev_err(dev, "nand_scan_tail failed: %d\n", ret);
return ret;
}
ret = nand_register(devnum, mtd);
if (ret) {
- dev_err(nfc->dev, "failed to register mtd device: %d\n", ret);
+ dev_err(dev, "failed to register mtd device: %d\n", ret);
return ret;
}
@@ -1744,13 +1745,13 @@ static int sunxi_nand_chip_init(ofnode n
return 0;
}
-static int sunxi_nand_chips_init(ofnode node, struct sunxi_nfc *nfc)
+static int sunxi_nand_chips_init(struct udevice *dev, struct sunxi_nfc *nfc)
{
ofnode nand_np;
int ret, i = 0;
- ofnode_for_each_subnode(nand_np, node) {
- ret = sunxi_nand_chip_init(nand_np, nfc, i++);
+ dev_for_each_subnode(nand_np, dev) {
+ ret = sunxi_nand_chip_init(dev, nfc, nand_np, i++);
if (ret)
return ret;
}
@@ -1802,7 +1803,7 @@ static int sunxi_nand_probe(struct udevi
if (ret)
return ret;
- ret = sunxi_nand_chips_init(dev_ofnode(dev), nfc);
+ ret = sunxi_nand_chips_init(dev, nfc);
if (ret) {
dev_err(dev, "failed to init nand chips\n");
return ret;

120
package/boot/uboot-d1/patches/0036-sunxi-Enable-PHY_SUN4I_USB-by-default-for-new-SoCs.patch Normal file
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@@ -0,0 +1,120 @@
From b13140a914199dcdd80331fef6f33d47f008f1b4 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Fri, 5 Aug 2022 23:40:22 -0500
Subject: [PATCH 36/90] sunxi: Enable PHY_SUN4I_USB by default for new SoCs
With one exception (sun9i), all sunxi SoCs released to date use variants
of the same USB PHY. Instead of requiring each new SoC to duplicate the
PHY driver selection, enable it by default.
Series-to: Andre Przywara <andre.przywara@arm.com>
Series-to: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/mach-sunxi/Kconfig | 11 -----------
drivers/phy/allwinner/Kconfig | 3 ++-
2 files changed, 2 insertions(+), 12 deletions(-)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -162,7 +162,6 @@ endif
config MACH_SUNXI_H3_H5
bool
- select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
@@ -191,7 +190,6 @@ config MACH_SUNIV
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7A
- select PHY_SUN4I_USB
select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
@@ -202,7 +200,6 @@ config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select CPU_V7A
select DRAM_SUN4I
- select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
imply SPL_SYS_I2C_LEGACY
@@ -216,7 +213,6 @@ config MACH_SUN6I
select ARCH_SUPPORT_PSCI
select SPL_ARMV7_SET_CORTEX_SMPEN
select DRAM_SUN6I
- select PHY_SUN4I_USB
select SPL_I2C
select SUN6I_PRCM
select SUNXI_GEN_SUN6I
@@ -232,7 +228,6 @@ config MACH_SUN7I
select ARCH_SUPPORT_PSCI
select SPL_ARMV7_SET_CORTEX_SMPEN
select DRAM_SUN4I
- select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -246,7 +241,6 @@ config MACH_SUN8I_A23
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A23
- select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
@@ -260,7 +254,6 @@ config MACH_SUN8I_A33
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select DRAM_SUN8I_A33
- select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
@@ -271,7 +264,6 @@ config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7A
select DRAM_SUN8I_A83T
- select PHY_SUN4I_USB
select SPL_I2C
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
@@ -299,7 +291,6 @@ config MACH_SUN8I_R40
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
- select PHY_SUN4I_USB
imply SPL_SYS_I2C_LEGACY
config MACH_SUN8I_V3S
@@ -327,7 +318,6 @@ config MACH_SUN9I
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
- select PHY_SUN4I_USB
select SUN6I_PRCM
select SUNXI_DE2
select SUNXI_GEN_SUN6I
@@ -350,7 +340,6 @@ config MACH_SUN50I_H5
config MACH_SUN50I_H6
bool "sun50i (Allwinner H6)"
select ARM64
- select PHY_SUN4I_USB
select DRAM_SUN50I_H6
select SUN50I_GEN_H6
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -3,7 +3,8 @@
#
config PHY_SUN4I_USB
bool "Allwinner Sun4I USB PHY driver"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI && !MACH_SUN9I
+ default y
select DM_REGULATOR
select PHY
help

183
package/boot/uboot-d1/patches/0037-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch Normal file
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@@ -0,0 +1,183 @@
From d11c5971f60d482c05f807c24f3ccd37cf7d0f70 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 9 Oct 2021 17:12:57 -0500
Subject: [PATCH 37/90] sunxi: psci: Add support for H3 CPU 0 hotplug
Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
written, resuming CPU 0 requires using the "Super Standby" code path in
the BROM instead of the hotplug path. This path requires jumping to an
eGON image in SRAM.
Add support to the build system to generate this eGON image and include
it in the FIT, and add code to direct the BROM to its location in SRAM.
Since the Super Standby code path in the BROM initializes the CPU and
AHB1 clocks to 24 MHz, those registers need to be restored after control
passes back to U-Boot. Furthermore, because the BROM lowers the AHB1
clock divider to /1 before switching to the lower-frequency parent,
PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at
600 MHz. Otherwise, this locks up the SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Makefile | 17 +++++++++++++++++
arch/arm/cpu/armv7/sunxi/psci.c | 31 +++++++++++++++++++++++++++++++
arch/arm/dts/sunxi-u-boot.dtsi | 23 ++++++++++++++++++++++-
include/configs/sun8i.h | 4 ++++
4 files changed, 74 insertions(+), 1 deletion(-)
--- a/Makefile
+++ b/Makefile
@@ -1013,6 +1013,23 @@ INPUTS-y += u-boot.img
endif
endif
+ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
+INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
+
+MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
+
+u-boot-resume.img: u-boot-resume.bin
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-resume.bin := -O binary
+
+u-boot-resume.bin: u-boot-resume.o
+ $(call if_changed,objcopy)
+
+u-boot-resume.S: u-boot
+ @sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
+endif
+
INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <asm/cache.h>
+#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h>
#include <asm/arch/prcm.h>
@@ -141,6 +142,13 @@ static void __secure sunxi_set_entry_add
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+ /* Redirect CPU 0 to the secure monitor via the resume shim. */
+ writel(0x16aaefe8, &cpucfg->super_standy_flag);
+ writel(0xaa16efe8, &cpucfg->super_standy_flag);
+ writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
}
#endif
@@ -255,9 +263,12 @@ out:
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
u32 context_id)
{
+ struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = (mpidr & 0x3);
+ u32 cpu_clk;
+ u32 bus_clk;
/* store target PC and context id */
psci_save(cpu, pc, context_id);
@@ -274,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_un
/* Lock CPU (Disable external debug access) */
clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+ /* Save registers that will be clobbered by the BROM. */
+ cpu_clk = readl(&ccu->cpu_axi_cfg);
+ bus_clk = readl(&ccu->ahb1_apb1_div);
+
+ /* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
+ setbits_le32(&ccu->pll6_cfg, BIT(25));
+ }
+
/* Power up target CPU */
sunxi_cpu_set_power(cpu, true);
/* De-assert reset on target CPU */
writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+ /* Spin until the BROM has clobbered the clock registers. */
+ while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
+
+ /* Restore the registers and turn off PLL_PERIPH0 bypass. */
+ writel(cpu_clk, &ccu->cpu_axi_cfg);
+ writel(bus_clk, &ccu->ahb1_apb1_div);
+
+ clrbits_le32(&ccu->pll6_cfg, BIT(25));
+ }
+
/* Unlock CPU (Disable external debug access) */
setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -6,7 +6,11 @@
#define ARCH "arm"
#endif
-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+#if defined(CONFIG_MACH_SUN8I_H3)
+#ifdef CONFIG_ARMV7_PSCI
+#define RESUME_ADDR SUNXI_RESUME_BASE
+#endif
+#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
#define BL31_ADDR 0x00044000
#define SCP_ADDR 0x00050000
#elif defined(CONFIG_MACH_SUN50I_H6)
@@ -78,6 +82,20 @@
};
#endif
+#ifdef RESUME_ADDR
+ resume {
+ description = "Super Standby resume image";
+ type = "standalone";
+ arch = ARCH;
+ compression = "none";
+ load = <RESUME_ADDR>;
+
+ blob-ext {
+ filename = "u-boot-resume.img";
+ };
+ };
+#endif
+
#ifdef SCP_ADDR
scp {
description = "SCP firmware";
@@ -111,6 +129,9 @@
firmware = "uboot";
#endif
loadables =
+#ifdef RESUME_ADDR
+ "resume",
+#endif
#ifdef SCP_ADDR
"scp",
#endif
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -8,6 +8,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define SUNXI_RESUME_BASE (CONFIG_ARMV7_SECURE_BASE + \
+ CONFIG_ARMV7_SECURE_MAX_SIZE)
+#define SUNXI_RESUME_SIZE 1024
+
#include <configs/sunxi-common.h>
#endif /* __CONFIG_H */

155
package/boot/uboot-d1/patches/0038-remoteproc-Add-a-driver-for-the-Allwinner-AR100.patch Normal file
View File

@@ -0,0 +1,155 @@
From 7585a12ffec6e42c62222d8ee4085413b3a197f7 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 9 Oct 2021 14:58:27 -0500
Subject: [PATCH 38/90] remoteproc: Add a driver for the Allwinner AR100
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/remoteproc/Kconfig | 9 ++
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/sun6i_ar100_rproc.c | 111 +++++++++++++++++++++++++
3 files changed, 121 insertions(+)
create mode 100644 drivers/remoteproc/sun6i_ar100_rproc.c
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -41,6 +41,15 @@ config REMOTEPROC_STM32_COPRO
Say 'y' here to add support for STM32 Cortex-M4 coprocessors via the
remoteproc framework.
+config REMOTEPROC_SUN6I_AR100
+ bool "Support for Allwinner AR100 SCP"
+ select REMOTEPROC
+ depends on ARCH_SUNXI
+ help
+ Say 'y' here to support Allwinner's AR100 System Control Processor
+ (SCP), found in various sun6i/sun8i/sun50i family SoCs, through the
+ remoteproc framework.
+
config REMOTEPROC_TI_K3_ARM64
bool "Support for TI's K3 based ARM64 remoteproc driver"
select REMOTEPROC
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc
obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
+obj-$(CONFIG_REMOTEPROC_SUN6I_AR100) += sun6i_ar100_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
--- /dev/null
+++ b/drivers/remoteproc/sun6i_ar100_rproc.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dm.h>
+#include <errno.h>
+#include <remoteproc.h>
+#include <asm/io.h>
+
+#define SUNXI_SCP_MAGIC 0xb4400012
+
+#define OR1K_VEC_FIRST 0x01
+#define OR1K_VEC_LAST 0x0e
+#define OR1K_VEC_ADDR(n) (0x100 * (n))
+
+struct sun6i_ar100_rproc_priv {
+ void *cfg_base;
+ ulong sram_base;
+};
+
+static int sun6i_ar100_rproc_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
+
+ /* Check for a valid SCP firmware. */
+ if (readl_relaxed(addr) != SUNXI_SCP_MAGIC)
+ return -ENOENT;
+
+ /* Program exception vectors to the firmware entry point. */
+ for (u32 i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
+ ulong vector = priv->sram_base + OR1K_VEC_ADDR(i);
+ ulong offset = addr - vector;
+
+ writel_relaxed(offset >> 2, vector);
+ }
+
+ return 0;
+}
+
+static int sun6i_ar100_rproc_start(struct udevice *dev)
+{
+ struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
+
+ setbits_le32(priv->cfg_base, BIT(0));
+
+ return 0;
+}
+
+static int sun6i_ar100_rproc_stop(struct udevice *dev)
+{
+ struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
+
+ clrbits_le32(priv->cfg_base, BIT(0));
+
+ return 0;
+}
+
+static int sun6i_ar100_rproc_reset(struct udevice *dev)
+{
+ int ret;
+
+ ret = sun6i_ar100_rproc_stop(dev);
+ if (ret)
+ return ret;
+
+ return sun6i_ar100_rproc_start(dev);
+}
+
+static int sun6i_ar100_rproc_is_running(struct udevice *dev)
+{
+ struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
+
+ return !(readl_relaxed(priv->cfg_base) & BIT(0));
+}
+
+static const struct dm_rproc_ops sun6i_ar100_rproc_ops = {
+ .load = sun6i_ar100_rproc_load,
+ .start = sun6i_ar100_rproc_start,
+ .stop = sun6i_ar100_rproc_stop,
+ .reset = sun6i_ar100_rproc_reset,
+ .is_running = sun6i_ar100_rproc_is_running,
+};
+
+static int sun6i_ar100_rproc_probe(struct udevice *dev)
+{
+ struct sun6i_ar100_rproc_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args sram_handle;
+ int ret;
+
+ priv->cfg_base = dev_read_addr_ptr(dev);
+
+ ret = dev_read_phandle_with_args(dev, "sram", NULL, 0, 0, &sram_handle);
+ if (ret)
+ return ret;
+
+ priv->sram_base = ofnode_get_addr(sram_handle.node);
+
+ return 0;
+}
+
+static const struct udevice_id sun6i_ar100_rproc_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-ar100" },
+ { }
+};
+
+U_BOOT_DRIVER(sun6i_ar100_rproc) = {
+ .name = "sun6i_ar100_rproc",
+ .id = UCLASS_REMOTEPROC,
+ .of_match = sun6i_ar100_rproc_ids,
+ .probe = sun6i_ar100_rproc_probe,
+ .priv_auto = sizeof(struct sun6i_ar100_rproc_priv),
+ .ops = &sun6i_ar100_rproc_ops,
+};

40
package/boot/uboot-d1/patches/0039-arm-dts-sunxi-h3-Add-nodes-for-AR100-remoteproc.patch Normal file
View File

@@ -0,0 +1,40 @@
From 2fdd94449c2668b4ff69326ff8d5daabdf2c9f00 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 9 Oct 2021 15:04:16 -0500
Subject: [PATCH 39/90] arm: dts: sunxi: h3: Add nodes for AR100 remoteproc
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun8i-h3.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -170,6 +170,14 @@
#size-cells = <1>;
ranges;
+ sram_a2: sram@40000 {
+ compatible = "mmio-sram";
+ reg = <0x00040000 0xc000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00040000 0xc000>;
+ };
+
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0x80000>;
@@ -239,6 +247,12 @@
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <0>;
};
+
+ remoteproc@1f01c00 {
+ compatible = "allwinner,sun6i-a31-ar100";
+ reg = <0x01f01c00 0x400>;
+ sram = <&sram_a2>;
+ };
};
thermal-zones {

63
package/boot/uboot-d1/patches/0040-sunxi-Enable-support-for-SCP-firmware-on-H3.patch Normal file
View File

@@ -0,0 +1,63 @@
From aefe751d6f23c9d526bca447c6c28da97e45e528 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 17 Apr 2021 13:33:54 -0500
Subject: [PATCH 40/90] sunxi: Enable support for SCP firmware on H3
Now that issues with the BROM have been sorted out, we can implement
PSCI system suspend on H3 by delegating to SCP firmware. Let's start by
including the firmware in the FIT image and starting the coprocessor if
valid firmware is loaded.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sunxi-u-boot.dtsi | 1 +
board/sunxi/board.c | 8 ++++++++
include/configs/sun8i.h | 3 +++
3 files changed, 12 insertions(+)
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -9,6 +9,7 @@
#if defined(CONFIG_MACH_SUN8I_H3)
#ifdef CONFIG_ARMV7_PSCI
#define RESUME_ADDR SUNXI_RESUME_BASE
+#define SCP_ADDR SUNXI_SCP_BASE
#endif
#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
#define BL31_ADDR 0x00044000
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -19,6 +19,7 @@
#include <init.h>
#include <log.h>
#include <mmc.h>
+#include <remoteproc.h>
#include <axp_pmic.h>
#include <generic-phy.h>
#include <phy-sun4i-usb.h>
@@ -867,6 +868,13 @@ int board_late_init(void)
usb_ether_init();
#endif
+#ifdef CONFIG_REMOTEPROC_SUN6I_AR100
+ if (!rproc_load(0, SUNXI_SCP_BASE, SUNXI_SCP_MAX_SIZE)) {
+ puts("Starting SCP...\n");
+ rproc_start(0);
+ }
+#endif
+
return 0;
}
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -12,6 +12,9 @@
CONFIG_ARMV7_SECURE_MAX_SIZE)
#define SUNXI_RESUME_SIZE 1024
+#define SUNXI_SCP_BASE (SUNXI_RESUME_BASE + SUNXI_RESUME_SIZE)
+#define SUNXI_SCP_MAX_SIZE (16 * 1024)
+
#include <configs/sunxi-common.h>
#endif /* __CONFIG_H */

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