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domenico
2025-06-24 12:51:15 +02:00
commit 27c9d80f51
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662
package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch Normal file
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@@ -0,0 +1,662 @@
arm: kirkwood: add ZyXEL NSA310 device
This patch add ZyXEL NSA310 1-Bay Media Server
The ZyXEL NSA310 device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1200Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Realtek
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 5 Status LED (green/red)
- 1 Copy/Sync button
- 1 Reset button
- 2 SATA II port (1 internal and 1 external eSata)
- 2 USB 2.0 ports (1 front and 1 back)
- Smart fan
Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
NOTE: this patch is ready for upstream, LEDE-specific parts are in
another patch
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -53,6 +53,9 @@ config TARGET_GOFLEXHOME
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310
+ bool "Zyxel NSA310 Board"
+
config TARGET_NSA310S
bool "Zyxel NSA310S"
@@ -86,6 +89,7 @@ source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
--- /dev/null
+++ b/board/zyxel/nsa310/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NSA310
+
+config SYS_BOARD
+ default "nsa310"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310"
+
+endif
--- /dev/null
+++ b/board/zyxel/nsa310/MAINTAINERS
@@ -0,0 +1,6 @@
+NSA310 BOARD
+M: Alberto Bursi <alberto.bursi@outlook.it>
+S: Maintained
+F: board/zyxel/nsa310/
+F: include/configs/nsa310.h
+F: configs/nsa310_defconfig
--- /dev/null
+++ b/board/zyxel/nsa310/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310.o
--- /dev/null
+++ b/board/zyxel/nsa310/kwbimage.cfg
@@ -0,0 +1,166 @@
+#
+# Copyright (C) 2013 Rafal Kazmierowski
+#
+# Based on guruplug.c originally written by
+# Siddarth Gore <gores@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+#BOOT_FROM uart
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43010c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000c # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db
+DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low)
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI
+DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+++ b/board/zyxel/nsa310/nsa310.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2013 Rafal Kazmierowski
+ *
+ * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
+ * originally written by
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
+ NSA310_OE_LOW, NSA310_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ /* (all LEDs & power off active high) */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA, /* PCF8563 RTC chip */
+ MPP9_TW_SCK, /* connected to TWSI */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* SATA2 LED (green) */
+ MPP13_GPIO, /* SATA2 LED (red) */
+ MPP14_GPIO, /* MCU DATA pin (in) */
+ MPP15_GPIO, /* USB LED (green) */
+ MPP16_GPIO, /* MCU CLK pin (out) */
+ MPP17_GPIO, /* MCU ACT pin (out) */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO, /* USB LED (red)-Power*/
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO, /* SYS LED (green) */
+ MPP29_GPIO, /* SYS LED (red) */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* Reset button */
+ MPP37_GPIO, /* Copy button */
+ MPP38_GPIO, /* VID B0 */
+ MPP39_GPIO, /* COPY LED (green) */
+ MPP40_GPIO, /* COPY LED (red) */
+ MPP41_GPIO, /* SATA1 LED (green) */
+ MPP42_GPIO, /* SATA1 LED (red) */
+ MPP43_GPIO, /* HTP pin */
+ MPP44_GPIO, /* Buzzer */
+ MPP45_GPIO, /* VID B1 */
+ MPP46_GPIO, /* Power button */
+ MPP47_GPIO, /* Power resume data */
+ MPP48_GPIO, /* Power off */
+ MPP49_GPIO, /* Power resume clock */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config,NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1318 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /* Set RGMII delay */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int val)
+{
+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ u32 dout0 = readl(&gpio0->dout);
+ u32 blen0 = readl(&gpio0->blink_en);
+
+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 dout1 = readl(&gpio1->dout);
+ u32 blen1 = readl(&gpio1->blink_en);
+
+ switch (val) {
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
+ writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_START:
+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_LOADED:
+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
+ break;
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
+ case -BOOTSTAGE_ID_NET_LOADED:
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
+ break;
+ default:
+ if (val < 0) {
+ /* error */
+ printf("Error occured, error code = %d\n", -val);
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
+ writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
+ }
+ break;
+ }
+}
+#endif
--- /dev/null
+++ b/board/zyxel/nsa310/nsa310.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2013 Rafal Kazmierowski
+ *
+ * Based on Peter Schildmann <linux@schildmann.info>
+ * and guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __NSA310_H
+#define __NSA310_H
+
+/* GPIO's */
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_RED_LED (1 << 29)
+#define SATA1_GREEN_LED (1ULL << 41)
+#define SATA1_RED_LED (1ULL << 42)
+#define SATA2_GREEN_LED (1 << 12)
+#define SATA2_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_RED_LED (1 << 21)
+#define COPY_GREEN_LED (1ULL << 39)
+#define COPY_RED_LED (1ULL << 40)
+
+#define NSA310_OE_LOW (0)
+#define NSA310_VAL_LOW (SYS_GREEN_LED)
+#define NSA310_OE_HIGH (((COPY_GREEN_LED | COPY_RED_LED | \
+ SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL)
+#define NSA310_VAL_HIGH (0)
+
+/* PHY related */
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __NSA310_H */
--- /dev/null
+++ b/configs/nsa310_defconfig
@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_NSA310=y
+CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="NSA310> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_FDT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_ENV=y
+CONFIG_CMD_NAND=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0xC0000
+CONFIG_CMD_UBI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_SYS_LONGHELP=y
--- /dev/null
+++ b/include/configs/nsa310.h
@@ -0,0 +1,103 @@
+/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_NSA310_H
+#define _CONFIG_NSA310_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KW88F6281 /* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Misc Configuration Options
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_PREBOOT
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x1
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+
+/*
+ * Date Time
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310_H */

649
package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch Normal file
View File

@@ -0,0 +1,649 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -68,6 +68,9 @@ config TARGET_SBx81LIFXCAT
config TARGET_DB_88F6281_BP
bool "Marvell DB-88F6281-BP"
+config TARGET_NSA325
+ bool "Zyxel NSA325 board"
+
endchoice
config SYS_SOC
@@ -91,6 +94,7 @@ source "board/Seagate/goflexhome/Kconfig
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
+source "board/zyxel/nsa325/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
source "board/Marvell/db-88f6281-bp/Kconfig"
--- /dev/null
+++ b/board/zyxel/nsa325/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NSA325
+
+config SYS_BOARD
+ default "nsa325"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa325"
+
+endif
--- /dev/null
+++ b/board/zyxel/nsa325/MAINTAINERS
@@ -0,0 +1,6 @@
+NSA325 BOARD
+M: Alberto Bursi <alberto.bursi@outlook.it>
+S: Maintained
+F: board/zyxel/nsa325/
+F: include/configs/nsa325.h
+F: configs/nsa325_defconfig
--- /dev/null
+++ b/board/zyxel/nsa325/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa325.o
+
--- /dev/null
+++ b/board/zyxel/nsa325/kwbimage.cfg
@@ -0,0 +1,78 @@
+# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
+#
+# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+#BOOT_FROM uart
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization
+DATA 0xFFD01400 0x4301503E # DDR Configuration register
+DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low
+DATA 0xFFD01408 0x33137777 # DDR Timing (Low)
+DATA 0xFFD0140C 0x16000C55 # DDR Timing (High)
+DATA 0xFFD01410 0x04000000 # DDR Address Control
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+DATA 0xFFD01418 0x00000000 # DDR Operation
+DATA 0xFFD0141C 0x00000672 # DDR Mode
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+DATA 0xFFD01424 0x0000F14F # DDR Controller Control High
+DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing
+DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb
+DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+
+DATA 0xFFD015D0 0x00000630
+DATA 0xFFD015D4 0x00000046
+DATA 0xFFD015D8 0x00000008
+DATA 0xFFD015DC 0x00000000
+DATA 0xFFD015E0 0x00000023
+DATA 0xFFD015E4 0x00203C18
+DATA 0xFFD01620 0x00384800
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x00066666
+
+#Disable nsa325 hardware watchdog to allow successful kwbooting
+DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
+DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
+
+# End of Header extension
+DATA 0x0 0x0
+
--- /dev/null
+++ b/board/zyxel/nsa325/nsa325.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on nsa320.c originall written by
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.c originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include "nsa325.h"
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
+ NSA325_OE_LOW, NSA325_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ /* (all LEDs & power off active high) */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA, /* PCF8563 RTC chip */
+ MPP9_TW_SCK, /* connected to TWSI */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* HDD2 LED (green) */
+ MPP13_GPIO, /* HDD2 LED (red) */
+ MPP14_GPIO, /* MCU DATA pin (in) */
+ MPP15_GPIO, /* USB LED (green) */
+ MPP16_GPIO, /* MCU CLK pin (out) */
+ MPP17_GPIO, /* MCU ACT pin (out) */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO, /* USB power */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO, /* SYS LED (green) */
+ MPP29_GPIO, /* SYS LED (orange) */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* reset button */
+ MPP37_GPIO, /* copy button */
+ MPP38_GPIO, /* VID B0 */
+ MPP39_GPIO, /* COPY LED (green) */
+ MPP40_GPIO, /* COPY LED (red) */
+ MPP41_GPIO, /* HDD1 LED (green) */
+ MPP42_GPIO, /* HDD1 LED (red) */
+ MPP43_GPIO, /* HTP pin */
+ MPP44_GPIO, /* buzzer */
+ MPP45_GPIO, /* VID B1 */
+ MPP46_GPIO, /* power button */
+ MPP47_GPIO, /* HDD2 power */
+ MPP48_GPIO, /* power off */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* This disables the hardware watchdog in the mcu on this board. */
+ kw_gpio_set_valid(14, 1);
+ kw_gpio_direction_output(14, 0);
+ kw_gpio_set_value(14, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1318 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /* Set RGMII delay */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
+ /* and has an MCU attached to the LED[2] via tristate interrupt */
+ reg = 0;
+
+ /* switch to LED register page */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
+
+ /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
+ miiphy_write(name, devadr, 0x4, 0x1e1);
+ miiphy_write(name, devadr, 0x9, 0x300);
+ /* Downshift */
+ miiphy_write(name, devadr, 0x10, 0x3860);
+ miiphy_write(name, devadr, 0x0, 0x9140);
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
+
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int val)
+{
+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ u32 dout0 = readl(&gpio0->dout);
+ u32 blen0 = readl(&gpio0->blink_en);
+
+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 dout1 = readl(&gpio1->dout);
+ u32 blen1 = readl(&gpio1->blink_en);
+
+ switch (val) {
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
+ writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_START:
+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
+ break;
+ case BOOTSTAGE_ID_NET_LOADED:
+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
+ break;
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
+ case -BOOTSTAGE_ID_NET_LOADED:
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
+ break;
+ default:
+ if (val < 0) {
+ /* error */
+ printf("Error occured, error code = %d\n", -val);
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
+ writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
+ }
+ break;
+ }
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO button status */
+/*
+un-pressed:
+ gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
+ gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear )
+ gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
+pressed
+ gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
+ gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear )
+ gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
+*/
+
+static int
+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "power") == 0) {
+ kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
+ kw_gpio_direction_input(BTN_POWER);
+ return !kw_gpio_get_value(BTN_POWER);
+ }
+ else if (strcmp(argv[1], "reset") == 0)
+ return kw_gpio_get_value(BTN_RESET);
+ else if (strcmp(argv[1], "copy") == 0)
+ return kw_gpio_get_value(BTN_COPY);
+ else
+ return -1;
+}
+
+
+U_BOOT_CMD(button, 2, 0, do_read_button,
+ "Return GPIO button status 0=off 1=on",
+ "- button power|reset|copy: test buttons states\n"
+);
+
+#endif
+
--- /dev/null
+++ b/board/zyxel/nsa325/nsa325.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ *
+ * Based on nsa320.h originall written by
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __NSA325_H
+#define __NSA325_H
+
+/* low GPIO's */
+#define HDD2_GREEN_LED (1 << 12)
+#define HDD2_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \
+ USB_GREEN_LED | USB_POWER | \
+ SYS_GREEN_LED | SYS_ORANGE_LED))
+#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define COPY_GREEN_LED (1 << 7)
+#define COPY_RED_LED (1 << 8)
+#define HDD1_GREEN_LED (1 << 9)
+#define HDD1_RED_LED (1 << 10)
+#define HDD2_POWER (1 << 15)
+#define WATCHDOG_SIGNAL (1 << 14)
+
+#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \
+ HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
+#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#define BTN_POWER 46
+#define BTN_RESET 36
+#define BTN_COPY 37
+
+#endif /* __NSA325_H */
--- /dev/null
+++ b/configs/nsa325_defconfig
@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_NSA325=y
+CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="NSA325> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_CMD_FDT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_ENV=y
+CONFIG_CMD_NAND=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0xC0000
+CONFIG_CMD_UBI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_SYS_LONGHELP=y
--- /dev/null
+++ b/include/configs/nsa325.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
+ *
+ * Based on
+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
+ * Based on
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
+ *
+ * Based on guruplug.h originally written by
+ * Siddarth Gore <gores@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_NSA325_H
+#define _CONFIG_NSA325_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Misc Configuration Options
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_PREBOOT
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x1
+#define CONFIG_NETCONSOLE
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+
+/*
+ * Date Time
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
+
+#endif /* _CONFIG_NSA325_H */

1520
package/boot/uboot-kirkwood/patches/010-pogoplug_v4.patch Normal file
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File diff suppressed because it is too large Load Diff

57
package/boot/uboot-kirkwood/patches/110-dockstar.patch Normal file
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@@ -0,0 +1,57 @@
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -17,6 +17,7 @@
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_MVFS
/*
* mv-common.h should be defined after CMD configs since it used them
@@ -37,19 +38,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x1100000 ${initrd}; " \
- "bootm 0x800000 0x1100000"
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=console=ttyS0,115200\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "initrd=/boot/uInitrd\0" \
- "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_OFFSET=0xE0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
CONFIG_BOOTDELAY=3
@@ -23,7 +23,7 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

51
package/boot/uboot-kirkwood/patches/120-iconnect.patch Normal file
View File

@@ -0,0 +1,51 @@
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -44,17 +44,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part rootfs; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
"bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet driver configuration
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_OFFSET=0xE0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" Iomega iConnect"
CONFIG_BOOTDELAY=3
@@ -16,13 +16,14 @@ CONFIG_SYS_PROMPT="iconnect => "
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

40
package/boot/uboot-kirkwood/patches/130-ib62x0.patch Normal file
View File

@@ -0,0 +1,40 @@
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -39,21 +39,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/zImage\0" \
- "fdt=/boot/ib62x0.dtb\0" \
- "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet driver configuration
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -26,7 +26,7 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

48
package/boot/uboot-kirkwood/patches/140-pogoplug_e02.patch Normal file
View File

@@ -0,0 +1,48 @@
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -42,17 +42,17 @@
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs $(bootargs_console); " \
- "run bootcmd_usb; " \
- "bootm 0x00800000 0x01100000"
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part ubi; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
- "32M(rootfs),-(data)\0"\
- "mtdids=nand0=orion_nand\0"\
- "bootargs_console=console=ttyS0,115200\0" \
- "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
- "ext2load usb 0:1 0x01100000 /uInitrd\0"
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_OFFSET=0xE0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nPogo E02"
CONFIG_BOOTDELAY=3
@@ -23,6 +23,7 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

35
package/boot/uboot-kirkwood/patches/150-goflexhome.patch Normal file
View File

@@ -0,0 +1,35 @@
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -60,17 +60,15 @@
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:root; " \
- "ubifsload 0x800000 ${kernel}; " \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
"bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/uImage\0" \
- "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -28,7 +28,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),255m(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

928
package/boot/uboot-kirkwood/patches/151-arm-kirkwood-add-CheckPoint-L-50-device.patch Normal file
View File

@@ -0,0 +1,928 @@
From 742f780f62ace452b83e2463f1f1afdda4b724ea Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Sun, 26 Jan 2020 07:27:24 +0100
Subject: [PATCH] arm: kirkwood: add CheckPoint L-50 device
This patch adds support for the Check Point L-50 from 600/1100 series
routers.
Specification:
-CPU: Marvell Kirkwood 88F6821 1200MHz
-RAM: 512MB
-Flash: NAND 512MB
-WiFi: mPCIe card based on Atheros AR9287 b/g/n
-WAN: 1 Gigabit Port (Marvell 88E1116R PHY)
-LAN: 9 Gigabit Ports (2x Marvell 88E6171(5+4))
-USB: 2x USB2.0
-Express card slot
-SD card slot
-Serial console: RJ-45 115200 8n1
-Unsupported DSL
Known limitations:
- In board is used two switches in chain. Second Marvell is not used
in u-Boot.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/kirkwood-l-50.dts | 439 +++++++++++++++++++++++++++++
arch/arm/mach-kirkwood/Kconfig | 4 +
board/checkpoint/l-50/Kconfig | 12 +
board/checkpoint/l-50/MAINTAINERS | 6 +
board/checkpoint/l-50/Makefile | 11 +
board/checkpoint/l-50/kwbimage.cfg | 36 +++
board/checkpoint/l-50/l-50.c | 172 +++++++++++
board/checkpoint/l-50/l-50.h | 29 ++
configs/l-50_defconfig | 59 ++++
include/configs/l-50.h | 59 ++++
11 files changed, 828 insertions(+)
create mode 100644 arch/arm/dts/kirkwood-l-50.dts
create mode 100644 board/checkpoint/l-50/Kconfig
create mode 100644 board/checkpoint/l-50/MAINTAINERS
create mode 100644 board/checkpoint/l-50/Makefile
create mode 100644 board/checkpoint/l-50/kwbimage.cfg
create mode 100644 board/checkpoint/l-50/l-50.c
create mode 100644 board/checkpoint/l-50/l-50.h
create mode 100644 configs/l-50_defconfig
create mode 100644 include/configs/l-50.h
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_KIRKWOOD) += \
kirkwood-iconnect.dtb \
kirkwood-is2.dtb \
kirkwood-km_kirkwood.dtb \
+ kirkwood-l-50.dtb \
kirkwood-lsxhl.dtb \
kirkwood-lschlv2.dtb \
kirkwood-net2big.dtb \
--- /dev/null
+++ b/arch/arm/dts/kirkwood-l-50.dts
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Check Point L-50 Board Description
+ * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Check Point L-50";
+ compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
+ pinctrl-names = "default";
+
+ pmx_sysrst: pmx-sysrst {
+ marvell,pins = "mpp6";
+ marvell,function = "sysrst";
+ };
+
+ pmx_button29: pmx_button29 {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_led38: pmx_led38 {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio_cd: pmx-sdio-cd {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ mvsdio@90000 {
+ status = "okay";
+ cd-gpios = <&gpio1 14 9>;
+ };
+
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ gpio2: gpio-expander@20{
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1505q";
+ reg = <0x20>;
+
+ gpio-controller;
+ };
+
+ /* Three GPIOs from 0x21 exp. are undescribed in dts:
+ * 1: DSL module reset (active low)
+ * 5: mPCIE reset (active low)
+ * 6: Express card reset (active low)
+ */
+ gpio3: gpio-expander@21{
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1505q";
+ reg = <0x21>;
+
+ gpio-controller;
+ };
+
+ rtc@30 {
+ compatible = "s35390a";
+ reg = <0x30>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "l-50:green:status";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ status_red {
+ label = "l-50:red:status";
+ gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi {
+ label = "l-50:green:wifi";
+ gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ internet_green {
+ label = "l-50:green:internet";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ };
+
+ internet_red {
+ label = "l-50:red:internet";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ usb1_green {
+ label = "l-50:green:usb1";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "usbport";
+ trigger-sources = <&hub_port3>;
+ };
+
+ usb1_red {
+ label = "l-50:red:usb1";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2_green {
+ label = "l-50:green:usb2";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "usbport";
+ trigger-sources = <&hub_port1>;
+ };
+
+ usb2_red {
+ label = "l-50:red:usb2";
+ gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usb2_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ usb1_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ mpcie_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "mpcie_pwr";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ express_card_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "express_card_pwr";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ factory_defaults {
+ label = "factory_defaults";
+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy8: ethernet-phy@8 {
+ reg = <0x08>;
+ };
+
+ switch0: switch@10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan5";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan6";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan7";
+ };
+
+ switch0port5: port@5 {
+ reg = <5>;
+ phy-mode = "rgmii-txid";
+ link = <&switch1port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ phy-mode = "rgmii-id";
+ ethernet = <&eth1port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ switch@11 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11>;
+ dsa,member = <0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "dmz";
+ };
+
+ switch1port5: port@5 {
+ reg = <5>;
+ phy-mode = "rgmii-txid";
+ link = <&switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "dsl";
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&eth0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <&ethphy8>;
+ };
+};
+
+&eth1 {
+ status = "okay";
+ ethernet1-port@0 {
+ speed = <1000>;
+ duplex = <1>;
+ phy-handle = <&switch0>;
+ };
+};
+
+&nand {
+ status = "okay";
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x000c0000>;
+ };
+
+ partition@a0000 {
+ label = "bootldr-env";
+ reg = <0x000c0000 0x00040000>;
+ };
+
+ partition@100000 {
+ label = "kernel-1";
+ reg = <0x00100000 0x00800000>;
+ };
+
+ partition@900000 {
+ label = "rootfs-1";
+ reg = <0x00900000 0x07100000>;
+ };
+
+ partition@7a00000 {
+ label = "kernel-2";
+ reg = <0x07a00000 0x00800000>;
+ };
+
+ partition@8200000 {
+ label = "rootfs-2";
+ reg = <0x08200000 0x07100000>;
+ };
+
+ partition@f300000 {
+ label = "default_sw";
+ reg = <0x0f300000 0x07900000>;
+ };
+
+ partition@16c00000 {
+ label = "logs";
+ reg = <0x16c00000 0x01800000>;
+ };
+
+ partition@18400000 {
+ label = "preset_cfg";
+ reg = <0x18400000 0x00100000>;
+ };
+
+ partition@18500000 {
+ label = "adsl";
+ reg = <0x18500000 0x00100000>;
+ };
+
+ partition@18600000 {
+ label = "storage";
+ reg = <0x18600000 0x07a00000>;
+ };
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&sata_phy0 {
+ status = "disabled";
+};
+
+&sata_phy1 {
+ status = "disabled";
+};
+
+&usb0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #trigger-source-cells = <0>;
+
+ hub_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ hub_port3: port@3 {
+ reg = <3>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -74,6 +74,9 @@ config TARGET_DB_88F6281_BP
config TARGET_NSA325
bool "Zyxel NSA325 board"
+config TARGET_L50
+ bool "Check Point L-50"
+
endchoice
config SYS_SOC
@@ -102,5 +105,6 @@ source "board/zyxel/nsa325/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
source "board/Marvell/db-88f6281-bp/Kconfig"
+source "board/checkpoint/l-50/Kconfig"
endif
--- /dev/null
+++ b/board/checkpoint/l-50/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_L50
+
+config SYS_BOARD
+ default "l-50"
+
+config SYS_VENDOR
+ default "checkpoint"
+
+config SYS_CONFIG_NAME
+ default "l-50"
+
+endif
--- /dev/null
+++ b/board/checkpoint/l-50/MAINTAINERS
@@ -0,0 +1,6 @@
+L50 BOARD
+M: Pawel Dembicki <paweldembicki@gmail.com>
+S: Maintained
+F: board/checkpoint/l-50/
+F: include/configs/l-50.h
+F: configs/l-50_defconfig
--- /dev/null
+++ b/board/checkpoint/l-50/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020
+# Pawel Dembicki <paweldembicki@gmail.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y := l-50.o
--- /dev/null
+++ b/board/checkpoint/l-50/kwbimage.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Values taken from original bootloader source.
+# Based on:
+# dramregs_seattle_400rd_A.txt from uboot_src_CP600_1100.
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+DATA 0xFFD100e0 0x1b1b1b9b
+DATA 0xFFD01400 0x43000c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x000000cc
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000C52
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147C 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x0FFFFFF5
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00120012
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E40F
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
--- /dev/null
+++ b/board/checkpoint/l-50/l-50.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020
+ * Pawel Dembicki <paweldembicki@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include "l-50.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ mvebu_config_gpio(L50_OE_VAL_LOW, L50_OE_VAL_HIGH,
+ L50_OE_LOW, L50_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_AUDIO_SPDIFI, /* value from stock u-boot */
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_TDM_SPI_CS0,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_TDM_CODEC_INTn,
+ MPP44_GPIO,
+ MPP45_TDM_PCLK,
+ MPP46_GPIO,
+ MPP47_TDM_DRX,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+void board_gpio_expander_init(void)
+{
+ struct udevice *dev0, *dev1;
+ uchar data_buffer;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, L50_GPIO0_I2C_ADDRESS, 1, &dev0);
+ if (ret) {
+ debug("%s: Cannot find I2C GPIO expander chip 0x02%X\n",
+ __func__, L50_GPIO0_I2C_ADDRESS);
+ return;
+ }
+
+ ret = i2c_get_chip_for_busnum(0, L50_GPIO1_I2C_ADDRESS, 1, &dev1);
+ if (ret) {
+ debug("%s: Cannot find I2C GPIO expander chip 0x02%X\n",
+ __func__, L50_GPIO1_I2C_ADDRESS);
+ return;
+ }
+
+ /* Set IO as output */
+ data_buffer = 0x0;
+ dm_i2c_write(dev0, 1, &data_buffer, 1);
+ dm_i2c_write(dev1, 1, &data_buffer, 1);
+
+ /* Set all leds off, reset asserted, pwr off */
+ data_buffer = 0xbf;
+ dm_i2c_write(dev0, 0, &data_buffer, 1);
+ data_buffer = 0x1c;
+ dm_i2c_write(dev1, 0, &data_buffer, 1);
+
+ mdelay(100);
+
+ /* Set pwr on */
+ data_buffer = 0xa5;
+ dm_i2c_write(dev1, 0, &data_buffer, 1);
+
+ mdelay(100);
+
+ /* Set reset deasserted, status red led enabled*/
+ data_buffer = 0xff;
+ dm_i2c_write(dev0, 0, &data_buffer, 1);
+ data_buffer = 0xe3;
+ dm_i2c_write(dev1, 0, &data_buffer, 1);
+}
+
+int board_init(void)
+{
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ board_gpio_expander_init();
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ u16 devadr;
+ char *name = "ethernet-controller@72000";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Err..(%s) could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /*
+ * Fix PHY led configuration
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 3);
+ miiphy_write(name, devadr, 0x10, 0x1177);
+ miiphy_write(name, devadr, 0x11, 0x4417);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+++ b/board/checkpoint/l-50/l-50.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Pawel Dembicki <paweldembicki@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __L50_H
+#define __L50_H
+
+/* GPIO configuration */
+#define L50_OE_LOW 0x30000000
+#define L50_OE_HIGH 0x0000004c
+#define L50_OE_VAL_LOW 0x00000000
+#define L50_OE_VAL_HIGH 0x00000000
+
+/* Expander GPIO addresses */
+
+#define L50_GPIO0_I2C_ADDRESS 0x20
+#define L50_GPIO1_I2C_ADDRESS 0x21
+
+/* PHY register */
+#define MV88E1116_PGADR_REG 22
+
+#endif /* __L50_H */
--- /dev/null
+++ b/configs/l-50_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_L50=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0xC0000
+CONFIG_IDENT_STRING="\nCheck Point L-50"
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_BOOTDELAY=1
+CONFIG_CONSOLE_MUX=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+#CONFIG_CMD_IDE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xc0000@0x0(u-boot)ro,0x40000@0xc0000(bootldr-env),0x7900000@0x100000(ubi),0x800000@0x7a00000(kernel-2),0x7100000@0x8200000(rootfs-2),0x7900000@0xf300000(default_sw),0x1800000@0x16c00000(logs),0x100000@0x18400000(preset_cfg),0x100000@0x18500000(adsl),-@0x18600000(storage)"
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-l-50"
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_DM_ETH=y
+#CONFIG_MVSATA_IDE=y
+CONFIG_MMC=y
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=6
+CONFIG_MV88E61XX_PHY_PORTS=0x01f
+CONFIG_MV88E61XX_FIXED_PORTS=0
+#CONFIG_DM_RTC=y
+#CONFIG_RTC_MV=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+++ b/include/configs/l-50.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Pawel Dembicki <paweldembicki@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_L50_H
+#define _CONFIG_L50_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KW88F6281 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+#define CONFIG_MV88E61XX_CPU_PORT_RX_DELAY
+#define CONFIG_MV88E61XX_CPU_PORT_TX_DELAY
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=console=ttyS0,115200\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
+#endif /* _CONFIG_L50_H */

54
package/boot/uboot-kirkwood/patches/160-nsa310s.patch Normal file
View File

@@ -0,0 +1,54 @@
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NSA310S=y
CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_OFFSET=0xC0000
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
@@ -25,7 +25,7 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xc0000@0x0(uboot),0x80000@0xc0000(uboot_env),-@0x140000(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -30,22 +30,17 @@
/* default environment variables */
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part ubi; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=console=ttyS0,115200\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/zImage\0" \
- "fdt=/boot/nsa310s.dtb\0" \
- "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/* Ethernet driver configuration */
#ifdef CONFIG_CMD_NET

39
package/boot/uboot-kirkwood/patches/170-sheevaplug.patch Normal file
View File

@@ -0,0 +1,39 @@
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -45,15 +45,17 @@
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids="CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=\0"
/*
* Ethernet Driver configuration
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -30,7 +30,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(uboot),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y

639
package/boot/uboot-kirkwood/patches/180-netgear-stora.patch Normal file
View File

@@ -0,0 +1,639 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -44,6 +44,9 @@ config TARGET_NET2BIG_V2
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
+config TARGET_NETGEAR_MS2110
+ bool "Netgear MS2110 Board"
+
config TARGET_IB62X0
bool "ib62x0 Board"
@@ -95,6 +98,7 @@ source "board/iomega/iconnect/Kconfig"
source "board/keymile/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
+source "board/Marvell/netgear_ms2110/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NETGEAR_MS2110
+
+config SYS_BOARD
+ default "netgear_ms2110"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "netgear_ms2110"
+
+endif
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/kwbimage.cfg
@@ -0,0 +1,167 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000099 # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 0, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x03FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x04000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x03FFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR_MS2110 BOARD
+M: bodhi <mibodhi@gmail.com>
+S: Maintained
+F: board/Marvell/netgear_ms2110
+F: include/configs/netgear_ms2110.h
+F: configs/netgear_ms2110_defconfig
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2014 bodhi <mibodhi@gmail.com>
+#
+# Based on
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := netgear_ms2110.o
+
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/netgear_ms2110.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2014-2017 bodhi <mibodhi@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "netgear_ms2110.h"
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NETGEAR_MS2110_OE_VAL_LOW,
+ NETGEAR_MS2110_OE_VAL_HIGH,
+ NETGEAR_MS2110_OE_LOW, NETGEAR_MS2110_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GE1_13,
+ MPP34_SATA1_ACTn,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_TDM_PCLK,
+ MPP46_TDM_FS,
+ MPP47_TDM_DRX,
+ MPP48_TDM_DTX,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_NETGEAR_MS2110;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
--- /dev/null
+++ b/board/Marvell/netgear_ms2110/netgear_ms2110.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __NETGEAR_MS2110_H
+#define __NETGEAR_MS2110_H
+
+#define NETGEAR_MS2110_OE_LOW (~(1 << 7))
+#define NETGEAR_MS2110_OE_HIGH (~(1 << 2 | 1 << 12))
+#define NETGEAR_MS2110_OE_VAL_LOW (0)
+#define NETGEAR_MS2110_OE_VAL_HIGH (1 << 12)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __NETGEAR_MS2110_H */
--- /dev/null
+++ b/configs/netgear_ms2110_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_TARGET_NETGEAR_MS2110=y
+CONFIG_IDENT_STRING="\nNetgear Stora MS2110"
+CONFIG_SYS_PROMPT="Stora> "
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_TEXT_BASE=0x600000
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_IDE=y
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_USB=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(ubi)"
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_NAND=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_ADDR=0xe0000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_CMD_UBI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_MVSATA_IDE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
--- /dev/null
+++ b/include/configs/netgear_ms2110.h
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2014-2017 bodhi <mibodhi@gmail.com>
+ * (C) Copyright 2020 Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_NGMS2110_H
+#define _CONFIG_NGMS2110_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_NETGEAR_MS2110 /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */
+#define CONFIG_CMD_ENV
+#define CONFIG_PREBOOT
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* #define CONFIG_CMD_AUTOSCRIPT */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+//#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
+//#define CONFIG_SYS_PROMPT "Netgear Stora> "
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * Default environment variables
+*/
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part ubi; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "arcNumber=2743\0" \
+ "console=console=ttyS0,115200\0" \
+ "ethact=egiga0\0" \
+ "ethaddr=52:3b:20:9c:11:51\0" \
+ "ipaddr=192.168.0.231\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "serverip=192.168.0.220\0" \
+ "bootargs_root=\0"
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable first port */
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
+#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x0A
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+
+/*
+ * SATA
+ */
+
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif
+
+/*
+ * Date Time
+ * */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_DNS
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NGMS2110_H */

387
package/boot/uboot-kirkwood/patches/190-dns-320l.patch Normal file
View File

@@ -0,0 +1,387 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -28,6 +28,9 @@ config TARGET_POGO_E02
config TARGET_POGOPLUGV4
bool "Pogoplug V4 Board"
+config TARGET_DNS320L
+ bool "dns320l Board"
+
config TARGET_DNS325
bool "dns325 Board"
@@ -93,6 +96,7 @@ source "board/Marvell/sheevaplug/Kconfig
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/cloudengines/pogoplugv4/Kconfig"
+source "board/d-link/dns320l/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
source "board/keymile/Kconfig"
--- /dev/null
+++ b/board/d-link/dns320l/dns320l.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include "dns320l.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(DNS320L_OE_VAL_LOW, DNS320L_OE_VAL_HIGH,
+ DNS320L_OE_LOW, DNS320L_OE_HIGH);
+
+ /* (all LEDs & power off active high) */
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn, /* sata1(left) status led */
+ MPP21_SATA0_ACTn, /* sata0(right) status led */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ kw_gpio_set_value(DNS320L_GPIO_SATA_EN , 1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 phyaddr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* read PHY dev address */
+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+ printf("could not read PHY dev address\n");
+ return;
+ }
+
+ /* set RGMII delay */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* reset PHY */
+ if (miiphy_reset(name, phyaddr))
+ return;
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+++ b/board/d-link/dns320l/dns320l.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __DNS320L_H
+#define __DNS320L_H
+
+/* GPIO configuration */
+#define DNS320L_GPIO_SATA_EN 24
+#define HDD_L_GREEN_LED (1 << 22)
+#define HDD_R_GREEN_LED (1 << 23)
+#define USB_BLUE_LED (1 << 25)
+#define USB_ORANGE_LED (1 << 26)
+
+#define DNS320L_OE_LOW (~(HDD_L_GREEN_LED | HDD_R_GREEN_LED | \
+ USB_BLUE_LED | USB_ORANGE_LED))
+#define DNS320L_OE_VAL_LOW (0)
+
+/* high GPIO's */
+#define WATCHDOG_SIGNAL (1 << 14)
+
+#define DNS320L_OE_HIGH (~(WATCHDOG_SIGNAL))
+#define DNS320L_OE_VAL_HIGH ((WATCHDOG_SIGNAL))
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
+
+#endif /* __DNS320L_H */
--- /dev/null
+++ b/board/d-link/dns320l/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+
+if TARGET_DNS320L
+
+config SYS_BOARD
+ default "dns320l"
+
+config SYS_VENDOR
+ default "d-link"
+
+config SYS_CONFIG_NAME
+ default "dns320l"
+
+endif
--- /dev/null
+++ b/board/d-link/dns320l/kwbimage.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
--- /dev/null
+++ b/board/d-link/dns320l/MAINTAINERS
@@ -0,0 +1,8 @@
+NSA310S BOARD
+M: Gerald Kerma <dreagle@doukki.net>
+M: Tony Dinh <mibodhi@gmail.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
+S: Maintained
+F: board/d-link/dns320l/
+F: include/configs/dns320l.h
+F: configs/dns320l_defconfig
--- /dev/null
+++ b/board/d-link/dns320l/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+
+obj-y := dns320l.o
--- /dev/null
+++ b/configs/dns320l_defconfig
@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x600000
+CONFIG_TARGET_DNS320L=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="dns320l => "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_IDE=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000@0x0(uboot),0x20000@0x100000(ubootenv),0x6de0000@0x120000(ubi),0xa00000@0x6f00000(mini),0x500000@0x7900000(config),0x200000@0x7e00000(my-dlink)"
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_MVSATA_IDE=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MVGBE=y
+CONFIG_MII=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_OF_LIBFDT=y
+CONFIG_NET_RANDOM_ETHADDR=y
--- /dev/null
+++ b/include/configs/dns320l.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ */
+
+#ifndef _CONFIG_DNS320L_H
+#define _CONFIG_DNS320L_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6192 1 /* SOC Name */
+#define CONFIG_KW88F6702 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* compression configuration */
+#define CONFIG_BZIP2
+
+/* commands configuration */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
+ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 1
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_IDE */
+
+/*
+ * Enable GPI0 support
+*/
+#define CONFIG_KIRKWOOD_GPIO
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_DNS320L_H */

216
package/boot/uboot-kirkwood/patches/200-openwrt-config.patch Normal file
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@@ -0,0 +1,216 @@
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -111,4 +111,7 @@ source "board/alliedtelesis/SBx81LIFXCAT
source "board/Marvell/db-88f6281-bp/Kconfig"
source "board/checkpoint/l-50/Kconfig"
+config SECOND_STAGE
+ bool "OpenWrt second stage hack"
+
endif
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -60,4 +60,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_DOCKSTAR_H */
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -77,4 +77,6 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_IB62x0_H */
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -67,4 +67,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_ICONNECT_H */
--- a/include/configs/l-50.h
+++ b/include/configs/l-50.h
@@ -12,6 +12,8 @@
#ifndef _CONFIG_L50_H
#define _CONFIG_L50_H
+#include "openwrt-kirkwood-common.h"
+
/*
* High Level Configuration Options (easy to change)
*/
--- /dev/null
+++ b/include/configs/openwrt-kirkwood-common.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OPENWRT_KIRKWOOD_COMMON_H
+#define __OPENWRT_KIRKWOOD_COMMON_H
+
+/* Ethernet */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_IPADDR 192.168.1.1
+#endif
+
+/* second stage loader */
+#if defined(CONFIG_SECOND_STAGE)
+#undef CONFIG_ENV_IS_IN_NAND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* Various */
+#define CONFIG_BZIP2
+
+/* Unnecessary */
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#endif /* __OPENWRT_KIRKWOOD_COMMON_H */
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -66,4 +66,6 @@
* File system
*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_POGO_E02_H */
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -85,4 +85,6 @@
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_GOFLEXHOME_H */
--- a/include/configs/nsa310.h
+++ b/include/configs/nsa310.h
@@ -100,4 +100,6 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_NSA310_H */
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -38,3 +38,8 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -49,3 +49,8 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -43,4 +43,7 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -39,4 +39,8 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/l-50_defconfig
+++ b/configs/l-50_defconfig
@@ -57,3 +57,8 @@ CONFIG_SYS_I2C_MVTWSI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/nsa310_defconfig
+++ b/configs/nsa310_defconfig
@@ -43,6 +43,9 @@ CONFIG_CMD_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
CONFIG_LZO=y
CONFIG_SYS_LONGHELP=y
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -39,3 +39,8 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -40,5 +40,8 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -63,4 +63,6 @@
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
+#include "openwrt-kirkwood-common.h"
+
#endif /* _CONFIG_NSA310S_H */
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -49,4 +49,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_LZMA=y
+CONFIG_LZO=y

29
package/boot/uboot-kirkwood/patches/201-blackarmor-nas220.patch Normal file
View File

@@ -0,0 +1,29 @@
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -54,17 +54,22 @@
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTCOMMAND \
+ "ubi part ubi; " \
+ "ubi read 0x800000 kernel; " \
+ "bootm 0x800000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=console=ttyS0,115200\0" \
"mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\
"0x010000@0xa0000(env),"\
- "0x500000@0xc0000(uimage),"\
- "0x1a40000@0x5c0000(rootfs)\0" \
+ "0x1e80000@0xc0000(ubi)\0"\
"mtdids=nand0=orion_nand\0"\
"autostart=no\0"\
- "autoload=no\0"
+ "autoload=no\0"\
+ "ipaddr=10.4.50.165\0"\
+ "serverip=10.4.50.5\0"\
+ "bootdelay=3"
/*
* Ethernet Driver configuration

48
package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch Normal file
View File

@@ -0,0 +1,48 @@
From 940e9a5828480e4185c9a276ad7f35a4069a2393 Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Thu, 23 Jan 2020 22:04:15 +0100
Subject: [PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
Clock delay in RGMII is required for some boards.
This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and
CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting
proper bits in PORT_REG_PHYS_CTRL register.
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/net/phy/mv88e61xx.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -94,6 +94,8 @@
#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
#define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15)
+#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14)
#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
@@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(st
PORT_REG_PHYS_CTRL_SPD1000;
}
- if (port == CONFIG_MV88E61XX_CPU_PORT)
+ if (port == CONFIG_MV88E61XX_CPU_PORT) {
val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
PORT_REG_PHYS_CTRL_LINK_FORCE;
+#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY)
+ val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;
+#endif
+#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY)
+ val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;
+#endif
+ }
return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
val);

62
package/boot/uboot-kirkwood/patches/702-phy-mv88e61xx-add-support-for-MV88E6171.patch Normal file
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@@ -0,0 +1,62 @@
From 7ffab66a99831ce5e3037b608d73565c9d1abd20 Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Thu, 23 Jan 2020 22:09:51 +0100
Subject: [PATCH 2/2] phy: mv88e61xx: add support for MV88E6171
This patch add MV88E6171 id to driver data.
Tested on Checkpoint L-50 board.
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
drivers/net/phy/mv88e61xx.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -180,6 +180,7 @@
#define PORT_SWITCH_ID_6071 0x0710
#define PORT_SWITCH_ID_6096 0x0980
#define PORT_SWITCH_ID_6097 0x0990
+#define PORT_SWITCH_ID_6171 0x1710
#define PORT_SWITCH_ID_6172 0x1720
#define PORT_SWITCH_ID_6176 0x1760
#define PORT_SWITCH_ID_6220 0x2200
@@ -997,6 +998,7 @@ static int mv88e61xx_probe(struct phy_de
switch (priv->id) {
case PORT_SWITCH_ID_6096:
case PORT_SWITCH_ID_6097:
+ case PORT_SWITCH_ID_6171:
case PORT_SWITCH_ID_6172:
case PORT_SWITCH_ID_6176:
case PORT_SWITCH_ID_6240:
@@ -1152,6 +1154,17 @@ static struct phy_driver mv88e61xx_drive
.shutdown = &genphy_shutdown,
};
+static struct phy_driver mv88e617x_driver = {
+ .name = "Marvell MV88E617x",
+ .uid = 0x01410e70,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .probe = mv88e61xx_probe,
+ .config = mv88e61xx_phy_config,
+ .startup = mv88e61xx_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver mv88e609x_driver = {
.name = "Marvell MV88E609x",
.uid = 0x1410c89,
@@ -1177,6 +1190,7 @@ static struct phy_driver mv88e6071_drive
int phy_mv88e61xx_init(void)
{
phy_register(&mv88e61xx_driver);
+ phy_register(&mv88e617x_driver);
phy_register(&mv88e609x_driver);
phy_register(&mv88e6071_driver);