Initial commit

target/linux/ath79/files/drivers/mtd/nand/raw/nand_rb4xx.c

@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * NAND driver for the MikroTik RouterBoard 4xx series
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
+ * Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>
+ *
+ * This file was based on the driver for Linux 2.6.22 published by
+ * MikroTik for their RouterBoard 4xx series devices.
+ *
+ * N.B. driver probe reports "DMA mask not set" warnings which are
+ * an artifact of using a platform_driver as an MFD device child.
+ * See conversation here https://lkml.org/lkml/2020/4/28/675
+ */
+#include <linux/platform_device.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/version.h>
+
+#include <mfd/rb4xx-cpld.h>
+
+struct rb4xx_nand {
+	struct rb4xx_cpld *cpld;
+	struct device *dev;
+
+	struct nand_chip chip;
+	struct gpio_desc *ale;
+	struct gpio_desc *cle;
+	struct gpio_desc *nce;
+	struct gpio_desc *rdy;
+};
+
+static int rb4xx_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb4xx_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb4xx_nand_ecclayout_ops = {
+	.ecc = rb4xx_ooblayout_ecc,
+	.free = rb4xx_ooblayout_free,
+};
+
+static u8 rb4xx_nand_read_byte(struct nand_chip *chip)
+{
+	struct rb4xx_nand *nand = chip->priv;
+	struct rb4xx_cpld *cpld = nand->cpld;
+	u8 data;
+	int ret;
+
+	ret = cpld->read_nand(cpld, &data, 1);
+	if (unlikely(ret))
+		return 0xff;
+
+	return data;
+}
+
+static void rb4xx_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
+{
+	struct rb4xx_nand *nand = chip->priv;
+	struct rb4xx_cpld *cpld = nand->cpld;
+
+	cpld->write_nand(cpld, buf, len);
+}
+
+static void rb4xx_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
+{
+	struct rb4xx_nand *nand = chip->priv;
+	struct rb4xx_cpld *cpld = nand->cpld;
+
+	cpld->read_nand(cpld, buf, len);
+}
+
+static void rb4xx_nand_cmd_ctrl(struct nand_chip *chip, int dat,
+				unsigned int ctrl)
+{
+	struct rb4xx_nand *nand = chip->priv;
+	struct rb4xx_cpld *cpld = nand->cpld;
+	u8 data = dat;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		gpiod_set_value_cansleep(nand->cle, !!(ctrl & NAND_CLE));
+		gpiod_set_value_cansleep(nand->ale, !!(ctrl & NAND_ALE));
+		gpiod_set_value_cansleep(nand->nce,  !(ctrl & NAND_NCE));
+	}
+
+	if (dat != NAND_CMD_NONE)
+		cpld->write_nand(cpld, &data, 1);
+}
+
+static int rb4xx_nand_dev_ready(struct nand_chip *chip)
+{
+	struct rb4xx_nand *nand = chip->priv;
+
+	return gpiod_get_value_cansleep(nand->rdy);
+}
+
+static int rb4xx_nand_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device *parent = dev->parent;
+	struct rb4xx_nand *nand;
+	struct mtd_info *mtd;
+	int ret;
+
+	if (!parent)
+		return -ENODEV;
+
+	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
+	if (!nand)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, nand);
+	nand->cpld	= dev_get_drvdata(parent);
+	nand->dev	= dev;
+
+	nand->ale = devm_gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);
+	if (IS_ERR(nand->ale))
+		dev_err(dev, "missing gpio ALE: %ld\n", PTR_ERR(nand->ale));
+
+	nand->cle = devm_gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);
+	if (IS_ERR(nand->cle))
+		dev_err(dev, "missing gpio CLE: %ld\n", PTR_ERR(nand->cle));
+
+	nand->nce = devm_gpiod_get_index(dev, NULL, 2, GPIOD_OUT_LOW);
+	if (IS_ERR(nand->nce))
+		dev_err(dev, "missing gpio nCE: %ld\n", PTR_ERR(nand->nce));
+
+	nand->rdy = devm_gpiod_get_index(dev, NULL, 3, GPIOD_IN);
+	if (IS_ERR(nand->rdy))
+		dev_err(dev, "missing gpio RDY: %ld\n", PTR_ERR(nand->rdy));
+
+	if (IS_ERR(nand->ale) || IS_ERR(nand->cle) ||
+	    IS_ERR(nand->nce) || IS_ERR(nand->rdy))
+		return -ENOENT;
+
+	gpiod_set_consumer_name(nand->ale, "mikrotik:nand:ALE");
+	gpiod_set_consumer_name(nand->cle, "mikrotik:nand:CLE");
+	gpiod_set_consumer_name(nand->nce, "mikrotik:nand:nCE");
+	gpiod_set_consumer_name(nand->rdy, "mikrotik:nand:RDY");
+
+	mtd = nand_to_mtd(&nand->chip);
+	mtd->priv	= nand;
+	mtd->owner	= THIS_MODULE;
+	mtd->dev.parent	= dev;
+	mtd_set_of_node(mtd, dev->of_node);
+
+	if (mtd->writesize == 512)
+		mtd_set_ooblayout(mtd, &rb4xx_nand_ecclayout_ops);
+
+	nand->chip.ecc.engine_type	= NAND_ECC_ENGINE_TYPE_SOFT;
+	nand->chip.ecc.algo		= NAND_ECC_ALGO_HAMMING;
+	nand->chip.options		= NAND_NO_SUBPAGE_WRITE;
+	nand->chip.priv			= nand;
+
+	nand->chip.legacy.read_byte	= rb4xx_nand_read_byte;
+	nand->chip.legacy.write_buf	= rb4xx_nand_write_buf;
+	nand->chip.legacy.read_buf	= rb4xx_nand_read_buf;
+	nand->chip.legacy.cmd_ctrl	= rb4xx_nand_cmd_ctrl;
+	nand->chip.legacy.dev_ready	= rb4xx_nand_dev_ready;
+	nand->chip.legacy.chip_delay	= 25;
+
+	ret = nand_scan(&nand->chip, 1);
+	if (ret)
+		return -ENXIO;
+
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret) {
+		mtd_device_unregister(nand_to_mtd(&nand->chip));
+		nand_cleanup(&nand->chip);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rb4xx_nand_remove(struct platform_device *pdev)
+{
+	struct rb4xx_nand *nand = platform_get_drvdata(pdev);
+
+	mtd_device_unregister(nand_to_mtd(&nand->chip));
+	nand_cleanup(&nand->chip);
+
+	return 0;
+}
+
+static const struct platform_device_id rb4xx_nand_id_table[] = {
+	{ "mikrotik,rb4xx-nand", },
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, rb4xx_nand_id_table);
+
+static struct platform_driver rb4xx_nand_driver = {
+	.probe = rb4xx_nand_probe,
+	.remove = rb4xx_nand_remove,
+	.id_table = rb4xx_nand_id_table,
+	.driver = {
+		.name = "rb4xx-nand",
+	},
+};
+
+module_platform_driver(rb4xx_nand_driver);
+
+MODULE_DESCRIPTION("Mikrotik RB4xx NAND driver");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
+MODULE_AUTHOR("Christopher Hill <ch6574@gmail.com");
+MODULE_LICENSE("GPL v2");

target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c

@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  MikroTik RB91x NAND flash driver
+ *
+ *  Main part is copied from original driver written by Gabor Juhos.
+ *
+ *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+/*
+ * WARNING: to speed up NAND reading/writing we are working with SoC GPIO
+ * controller registers directly -- not through standard GPIO API.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/version.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+/* Bit masks for NAND data lines in ath79 gpio 32-bit register */
+#define RB91X_NAND_NRW_BIT BIT(12)
+#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \
+			    | BIT(13) | BIT(14) | BIT(15))
+#define RB91X_NAND_LOW_DATA_MASK	0x1f
+#define RB91X_NAND_HIGH_DATA_MASK	0xe0
+#define RB91X_NAND_HIGH_DATA_SHIFT	8
+
+enum rb91x_nand_gpios {
+	RB91X_NAND_READ,/* Read */
+	RB91X_NAND_RDY, /* NAND Ready */
+	RB91X_NAND_NCE, /* Chip Enable. Active low */
+	RB91X_NAND_CLE, /* Command Latch Enable */
+	RB91X_NAND_ALE, /* Address Latch Enable */
+	RB91X_NAND_NRW, /* Read/Write. Active low */
+	RB91X_NAND_NLE, /* Latch Enable. Active low */
+	RB91X_NAND_PDIS, /* Reset Key Poll Disable. Active high */
+
+	RB91X_NAND_GPIOS,
+};
+
+struct rb91x_nand_drvdata {
+	struct nand_chip chip;
+	struct device *dev;
+	struct gpio_desc **gpio;
+	void __iomem *ath79_gpio_base;
+};
+
+static inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,
+					 int lock)
+{
+	gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);
+}
+
+static inline void rb91x_nand_rst_key_poll_disable(struct rb91x_nand_drvdata *drvdata,
+						   int disable)
+{
+	gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_PDIS], disable);
+}
+
+static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
+			       struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 8;
+		oobregion->length = 3;
+		return 0;
+	case 1:
+		oobregion->offset = 13;
+		oobregion->length = 3;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
+				struct mtd_oob_region *oobregion)
+{
+	switch (section) {
+	case 0:
+		oobregion->offset = 0;
+		oobregion->length = 4;
+		return 0;
+	case 1:
+		oobregion->offset = 4;
+		oobregion->length = 1;
+		return 0;
+	case 2:
+		oobregion->offset = 6;
+		oobregion->length = 2;
+		return 0;
+	case 3:
+		oobregion->offset = 11;
+		oobregion->length = 2;
+		return 0;
+	default:
+		return -ERANGE;
+	}
+}
+
+static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
+	.ecc = rb91x_ooblayout_ecc,
+	.free = rb91x_ooblayout_free,
+};
+
+static void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,
+			     const u8 *buf,
+			     unsigned len)
+{
+	void __iomem *base = drvdata->ath79_gpio_base;
+	u32 oe_reg;
+	u32 out_reg;
+	u32 out;
+	unsigned i;
+
+	rb91x_nand_latch_lock(drvdata, 1);
+	rb91x_nand_rst_key_poll_disable(drvdata, 1);
+
+	oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
+	out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
+
+	/* Set data lines to output mode */
+	__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),
+		     base + AR71XX_GPIO_REG_OE);
+
+	out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);
+	for (i = 0; i != len; i++) {
+		u32 data;
+
+		data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
+			RB91X_NAND_HIGH_DATA_SHIFT;
+		data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
+		data |= out;
+		__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
+
+		/* Deactivate WE line */
+		data |= RB91X_NAND_NRW_BIT;
+		__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
+		/* Flush write */
+		__raw_readl(base + AR71XX_GPIO_REG_OUT);
+	}
+
+	/* Restore registers */
+	__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
+	__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
+	/* Flush write */
+	__raw_readl(base + AR71XX_GPIO_REG_OUT);
+
+	rb91x_nand_rst_key_poll_disable(drvdata, 0);
+	rb91x_nand_latch_lock(drvdata, 0);
+}
+
+static void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,
+			    u8 *read_buf,
+			    unsigned len)
+{
+	void __iomem *base = drvdata->ath79_gpio_base;
+	u32 oe_reg;
+	u32 out_reg;
+	unsigned i;
+
+	/* Enable read mode */
+	gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);
+
+	rb91x_nand_latch_lock(drvdata, 1);
+	rb91x_nand_rst_key_poll_disable(drvdata, 1);
+
+	/* Save registers */
+	oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
+	out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
+
+	/* Set data lines to input mode */
+	__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
+		     base + AR71XX_GPIO_REG_OE);
+
+	for (i = 0; i < len; i++) {
+		u32 in;
+		u8 data;
+
+		/* Activate RE line */
+		__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);
+		/* Flush write */
+		__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
+
+		/* Read input lines */
+		in = __raw_readl(base + AR71XX_GPIO_REG_IN);
+
+		/* Deactivate RE line */
+		__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);
+
+		data = (in & RB91X_NAND_LOW_DATA_MASK);
+		data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
+			RB91X_NAND_HIGH_DATA_MASK;
+
+		read_buf[i] = data;
+	}
+
+	/* Restore  registers */
+	__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
+	__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
+	/* Flush write */
+	__raw_readl(base + AR71XX_GPIO_REG_OUT);
+
+	rb91x_nand_rst_key_poll_disable(drvdata, 0);
+	rb91x_nand_latch_lock(drvdata, 0);
+
+	/* Disable read mode */
+	gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);
+}
+
+static int rb91x_nand_dev_ready(struct nand_chip *chip)
+{
+	struct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);
+
+	return gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);
+}
+
+static void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
+				unsigned int ctrl)
+{
+	struct rb91x_nand_drvdata *drvdata = chip->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],
+					(ctrl & NAND_CLE) ? 1 : 0);
+		gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],
+					(ctrl & NAND_ALE) ? 1 : 0);
+		gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],
+					(ctrl & NAND_NCE) ? 1 : 0);
+	}
+
+	if (cmd != NAND_CMD_NONE) {
+		u8 t = cmd;
+
+		rb91x_nand_write(drvdata, &t, 1);
+	}
+}
+
+static u8 rb91x_nand_read_byte(struct nand_chip *chip)
+{
+	u8 data = 0xff;
+
+	rb91x_nand_read(chip->priv, &data, 1);
+
+	return data;
+}
+
+static void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
+{
+	rb91x_nand_read(chip->priv, buf, len);
+}
+
+static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
+{
+	rb91x_nand_write(chip->priv, buf, len);
+}
+
+static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
+{
+	mtd_device_unregister(nand_to_mtd(&drvdata->chip));
+	nand_cleanup(&drvdata->chip);
+}
+
+static int rb91x_nand_probe(struct platform_device *pdev)
+{
+	struct rb91x_nand_drvdata *drvdata;
+	struct mtd_info *mtd;
+	int r;
+	struct device *dev = &pdev->dev;
+	struct gpio_descs *gpios;
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, drvdata);
+
+	gpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);
+	if (IS_ERR(gpios)) {
+		if (PTR_ERR(gpios) != -EPROBE_DEFER) {
+			dev_err(dev, "failed to get gpios: %ld\n",
+				PTR_ERR(gpios));
+		}
+		return PTR_ERR(gpios);
+	}
+
+	if (gpios->ndescs != RB91X_NAND_GPIOS) {
+		dev_err(dev, "expected %d gpios\n", RB91X_NAND_GPIOS);
+		return -EINVAL;
+	}
+
+	drvdata->gpio = gpios->desc;
+
+	gpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);
+
+	drvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+
+	drvdata->dev = dev;
+
+	drvdata->chip.priv = drvdata;
+
+	drvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;
+	drvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;
+	drvdata->chip.legacy.read_byte = rb91x_nand_read_byte;
+	drvdata->chip.legacy.write_buf = rb91x_nand_write_buf;
+	drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
+
+	drvdata->chip.legacy.chip_delay = 25;
+	drvdata->chip.ecc.engine_type      = NAND_ECC_ENGINE_TYPE_SOFT;
+	drvdata->chip.ecc.algo             = NAND_ECC_ALGO_HAMMING;
+	drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
+
+	r = nand_scan(&drvdata->chip, 1);
+	if (r) {
+		dev_err(dev, "nand_scan() failed: %d\n", r);
+		return r;
+	}
+
+	mtd = nand_to_mtd(&drvdata->chip);
+	mtd->dev.parent = dev;
+	mtd_set_of_node(mtd, dev->of_node);
+	mtd->owner = THIS_MODULE;
+	if (mtd->writesize == 512)
+		mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
+
+	r = mtd_device_register(mtd, NULL, 0);
+	if (r) {
+		dev_err(dev, "mtd_device_register() failed: %d\n",
+			r);
+		goto err_release_nand;
+	}
+
+	return 0;
+
+err_release_nand:
+	rb91x_nand_release(drvdata);
+	return r;
+}
+
+static int rb91x_nand_remove(struct platform_device *pdev)
+{
+	struct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	rb91x_nand_release(drvdata);
+
+	return 0;
+}
+
+static const struct of_device_id rb91x_nand_match[] = {
+	{ .compatible = "mikrotik,rb91x-nand" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, rb91x_nand_match);
+
+static struct platform_driver rb91x_nand_driver = {
+	.probe	= rb91x_nand_probe,
+	.remove	= rb91x_nand_remove,
+	.driver	= {
+		.name	= "rb91x-nand",
+		.owner	= THIS_MODULE,
+		.of_match_table = rb91x_nand_match,
+	},
+};
+
+module_platform_driver(rb91x_nand_driver);
+
+MODULE_DESCRIPTION("MikrotTik RB91x NAND flash driver");
+MODULE_VERSION(DRV_VERSION);
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
+MODULE_LICENSE("GPL v2");

target/linux/ath79/files/drivers/mtd/parsers/parser_cybertan.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2009 Christian Daniel <cd@maintech.de>
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * TRX flash partition table.
+ * Based on ar7 map by Felix Fietkau <nbd@nbd.name>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/version.h>
+
+struct cybertan_header {
+	char	magic[4];
+	u8	res1[4];
+	char	fw_date[3];
+	char	fw_ver[3];
+	char	id[4];
+	char	hw_ver;
+	char	unused;
+	u8	flags[2];
+	u8	res2[10];
+} __packed;
+
+#define TRX_PARTS	3
+#define TRX_MAGIC	0x30524448
+#define TRX_MAX_OFFSET	3
+
+struct trx_header {
+	__le32 magic;           /* "HDR0" */
+	__le32 len;             /* Length of file including header */
+	__le32 crc32;           /* 32-bit CRC from flag_version to end of file */
+	__le32 flag_version;    /* 0:15 flags, 16:31 version */
+	__le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
+} __packed;
+
+#define IH_MAGIC	0x27051956	/* Image Magic Number */
+#define IH_NMLEN	32		/* Image Name Length */
+
+struct uimage_header {
+	__be32	ih_magic;	/* Image Header Magic Number */
+	__be32	ih_hcrc;	/* Image Header CRC Checksum */
+	__be32	ih_time;	/* Image Creation Timestamp */
+	__be32	ih_size;	/* Image Data Size */
+	__be32	ih_load;	/* Data» Load  Address */
+	__be32	ih_ep;		/* Entry Point Address */
+	__be32	ih_dcrc;	/* Image Data CRC Checksum */
+	uint8_t	ih_os;		/* Operating System */
+	uint8_t	ih_arch;	/* CPU architecture */
+	uint8_t	ih_type;	/* Image Type */
+	uint8_t	ih_comp;	/* Compression Type */
+	uint8_t	ih_name[IH_NMLEN];	/* Image Name */
+} __packed;
+
+struct firmware_header {
+	struct cybertan_header	cybertan;
+	struct trx_header	trx;
+	struct uimage_header	uimage;
+} __packed;
+
+static int cybertan_parse_partitions(struct mtd_info *master,
+				     const struct mtd_partition **pparts,
+				     struct mtd_part_parser_data *data)
+{
+	struct firmware_header header;
+	struct trx_header *theader;
+	struct uimage_header *uheader;
+	struct mtd_partition *trx_parts;
+	size_t retlen;
+	unsigned int kernel_len;
+	int ret;
+
+	trx_parts = kcalloc(TRX_PARTS, sizeof(struct mtd_partition),
+			    GFP_KERNEL);
+	if (!trx_parts) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = mtd_read(master, 0, sizeof(header),
+		       &retlen, (uint8_t *)&header);
+	if (ret)
+		goto free_parts;
+
+	if (retlen != sizeof(header)) {
+		ret = -EIO;
+		goto free_parts;
+	}
+
+	theader = &header.trx;
+	if (theader->magic != cpu_to_le32(TRX_MAGIC)) {
+		printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
+		goto free_parts;
+	}
+
+	uheader = &header.uimage;
+	if (uheader->ih_magic != cpu_to_be32(IH_MAGIC)) {
+		printk(KERN_NOTICE "%s: no uImage found\n", master->name);
+		goto free_parts;
+	}
+
+	kernel_len = le32_to_cpu(theader->offsets[1]) +
+		sizeof(struct cybertan_header);
+
+	trx_parts[0].name = "header";
+	trx_parts[0].offset = 0;
+	trx_parts[0].size = offsetof(struct firmware_header, uimage);
+	trx_parts[0].mask_flags = 0;
+
+	trx_parts[1].name = "kernel";
+	trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
+	trx_parts[1].size = kernel_len - trx_parts[0].size;
+	trx_parts[1].mask_flags = 0;
+
+	trx_parts[2].name = "rootfs";
+	trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
+	trx_parts[2].size = master->size - trx_parts[1].size - trx_parts[0].size;
+	trx_parts[2].mask_flags = 0;
+
+	*pparts = trx_parts;
+	return TRX_PARTS;
+
+free_parts:
+	kfree(trx_parts);
+out:
+	return ret;
+}
+
+static const struct of_device_id mtd_parser_cybertan_of_match_table[] = {
+	{ .compatible = "cybertan,trx" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mtd_parser_cybertan_of_match_table);
+
+static struct mtd_part_parser mtd_parser_cybertan = {
+	.parse_fn = cybertan_parse_partitions,
+	.name = "cybertan-trx",
+	.of_match_table = mtd_parser_cybertan_of_match_table,
+};
+module_mtd_part_parser(mtd_parser_cybertan);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");