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domenico
2025-06-24 12:51:15 +02:00
commit 27c9d80f51
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70
target/linux/bcm27xx/patches-6.6/950-0546-ASoC-dwc-Add-DMACR-handling.patch Normal file
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@@ -0,0 +1,70 @@
From 3454cbb46e2bf08b5506fff06029f082c7d59516 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.com>
Date: Mon, 3 Jul 2023 09:08:16 +0100
Subject: [PATCH 0546/1085] ASoC: dwc: Add DMACR handling
Add control of the DMACR register, which is required for paced DMA
(i.e. DREQ) support.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
---
sound/soc/dwc/dwc-i2s.c | 11 +++++++++--
sound/soc/dwc/local.h | 11 +++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -248,7 +248,7 @@ static void dw_i2s_config(struct dw_i2s_
{
u32 ch_reg;
struct i2s_clk_config_data *config = &dev->config;
-
+ u32 dmacr = 0;
i2s_disable_channels(dev, stream);
@@ -260,6 +260,7 @@ static void dw_i2s_config(struct dw_i2s_
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
dev->tdm_mask << TER_TXSLOT_SHIFT);
+ dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
} else {
i2s_write_reg(dev->i2s_base, RCR(ch_reg),
dev->xfer_resolution);
@@ -267,9 +268,15 @@ static void dw_i2s_config(struct dw_i2s_
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
dev->tdm_mask << RER_RXSLOT_SHIFT);
+ dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
}
-
}
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+ dmacr |= DMACR_DMAEN_TX;
+ else if (stream == SNDRV_PCM_STREAM_CAPTURE)
+ dmacr |= DMACR_DMAEN_RX;
+
+ i2s_write_reg(dev->i2s_base, I2S_DMACR, dmacr);
}
static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
--- a/sound/soc/dwc/local.h
+++ b/sound/soc/dwc/local.h
@@ -63,6 +63,17 @@
#define TER_TXSLOT_SHIFT 8
#define TER_TXCHEN BIT(0)
+#define DMACR_DMAEN_TX BIT(17)
+#define DMACR_DMAEN_RX BIT(16)
+#define DMACR_DMAEN_TXCH3 BIT(11)
+#define DMACR_DMAEN_TXCH2 BIT(10)
+#define DMACR_DMAEN_TXCH1 BIT(9)
+#define DMACR_DMAEN_TXCH0 BIT(8)
+#define DMACR_DMAEN_RXCH3 BIT(3)
+#define DMACR_DMAEN_RXCH2 BIT(2)
+#define DMACR_DMAEN_RXCH1 BIT(1)
+#define DMACR_DMAEN_RXCH0 BIT(0)
+
/* I2SCOMPRegisters */
#define I2S_COMP_PARAM_2 0x01F0
#define I2S_COMP_PARAM_1 0x01F4