Initial commit

target/linux/bmips/Makefile

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+include $(TOPDIR)/rules.mk
+
+ARCH:=mips
+CPU_TYPE:=mips32
+BOARD:=bmips
+BOARDNAME:=Broadcom BMIPS
+SUBTARGETS:=bcm6318 bcm6328 bcm6358 bcm6362 bcm6368 bcm63268
+FEATURES:=gpio squashfs usb
+
+KERNEL_PATCHVER:=6.6
+
+define Target/Description
+	Build firmware images for BCM33xx cable modem chips,
+	BCM63xx DSL chips and BCM7xxx set-top box chips.
+endef
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += ethtool kmod-gpio-button-hotplug
+
+$(eval $(call BuildTarget))

target/linux/bmips/bcm6318/base-files/etc/board.d/01_leds

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+comtrend,ar-5315u)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6318/base-files/etc/board.d/02_network

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+comtrend,ar-5315u)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6318/base-files/etc/uci-defaults/09_fix_crc

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions.sh
+
+case "$(board_name)" in
+comtrend,ar-5315u)
+	mtd fixtrx firmware
+	;;
+esac
+
+exit 0

target/linux/bmips/bcm6318/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm6318/config-6.6

@@ -0,0 +1,297 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+# CONFIG_BCM6348_ENET is not set
+CONFIG_BCM6368_ENETSW=y
+CONFIG_BCM63XX_POWER=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CLK_BCM63268_TIMER is not set
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_BCM6368=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_BCM6318=y
+# CONFIG_PCIE_BCM6328 is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCI_BCM6348 is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCM6318=y
+# CONFIG_PINCTRL_BCM63268 is not set
+# CONFIG_PINCTRL_BCM6328 is not set
+# CONFIG_PINCTRL_BCM6358 is not set
+# CONFIG_PINCTRL_BCM6362 is not set
+# CONFIG_PINCTRL_BCM6368 is not set
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BCM63XX=y
+CONFIG_SPI=y
+# CONFIG_SPI_BCM63XX is not set
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm6318/target.mk

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm6318
+BOARDNAME:=BCM6318 based boards
+
+define Target/Description
+  Build firmware images for Broadcom BCM6318 based boards.
+endef

target/linux/bmips/bcm63268/base-files/etc/board.d/01_leds

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+comtrend,vr-3032u)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	;;
+smartrg,sr505n)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1"
+	;;
+sercomm,h500-s-lowi |\
+sercomm,h500-s-vfes)
+	ucidef_set_led_netdev "wan" "WAN" "green:internet" "wan"
+	ucidef_set_led_netdev "wifi" "WiFi" "green:wifi" "wifi"
+	ucidef_set_led_usbport "usb" "USB" "green:mobile" "usb1-port1" "usb2-port1"
+	;;
+sercomm,shg2500)
+	ucidef_set_led_netdev "wan" "WAN" "green:internet" "wan"
+	ucidef_set_led_usbport "usb1" "USB1" "blue:modem" "usb1-port1" "usb2-port1"
+	ucidef_set_led_usbport "usb2" "USB2" "green:modem" "usb1-port2" "usb2-port2"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm63268/base-files/etc/board.d/02_network

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+comtrend,vr-3032u |\
+smartrg,sr505n)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+	;;
+sercomm,h500-s-lowi |\
+sercomm,h500-s-vfes)
+	ucidef_set_bridge_device switch
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
+	ucidef_set_interface "qtn" device "wifi" protocol "static" ipaddr "1.1.1.1" netmask "255.255.255.252"
+	uci add_list firewall.@zone[0].network='qtn'
+	;;
+comtrend,vg-8050 |\
+sagem,fast-3864-op |\
+sercomm,shg2500)
+	ucidef_set_bridge_device switch
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm63268/base-files/etc/board.d/03_gpio_switches

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+sercomm,h500-s-lowi |\
+sercomm,h500-s-vfes)
+	ucidef_add_gpio_switch "qtn_power" "Quantenna Module Power" "480" "1"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm63268/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	comtrend,vg-8050 |\
+	comtrend,vr-3032u |\
+	sagem,fast-3864-op)
+		CI_JFFS2_CLEAN_MARKERS=1
+		nand_do_upgrade "$1"
+		;;
+	sercomm,h500-s-lowi |\
+	sercomm,h500-s-vfes |\
+	sercomm,shg2500)
+		nand_do_upgrade "$1"
+		;;
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm63268/config-6.6

@@ -0,0 +1,312 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+# CONFIG_BCM6348_ENET is not set
+CONFIG_BCM6368_ENETSW=y
+CONFIG_BCM63XX_POWER=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_BCM63268_TIMER=y
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_BCM6368=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_BRCMNAND_BCM63XX=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_BCM6318 is not set
+CONFIG_PCIE_BCM6328=y
+CONFIG_PCIE_PME=y
+# CONFIG_PCI_BCM6348 is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_BCM6318 is not set
+CONFIG_PINCTRL_BCM63268=y
+# CONFIG_PINCTRL_BCM6328 is not set
+# CONFIG_PINCTRL_BCM6358 is not set
+# CONFIG_PINCTRL_BCM6362 is not set
+# CONFIG_PINCTRL_BCM6368 is not set
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BCM63XX=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm63268/target.mk

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm63268
+BOARDNAME:=BCM63268 based boards
+FEATURES+=nand
+
+define Target/Description
+  Build firmware images for Broadcom BCM63268 based boards.
+endef

target/linux/bmips/bcm6328/base-files/etc/board.d/01_leds

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+arcadyan,ar7516)
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan"
+	ucidef_set_led_netdev "wlan0" "WiFi" "green:wifi" "phy0-ap0"
+	;;
+nucom,r5010unv2 |\
+sercomm,ad1018)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6328/base-files/etc/board.d/02_network

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+arcadyan,ar7516)
+	ucidef_set_bridge_device switch
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
+	;;
+inteno,xg6846)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan ext1"
+	;;
+comtrend,ar-5381u |\
+comtrend,ar-5387un |\
+innacomm,w3400v6 |\
+nucom,r5010unv2)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+	;;
+sercomm,ad1018)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 fibre"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6328/base-files/etc/uci-defaults/09_fix_crc

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions.sh
+
+case "$(board_name)" in
+arcadyan,ar7516 |\
+comtrend,ar-5381u |\
+comtrend,ar-5387un |\
+nucom,r5010unv2)
+	mtd fixtrx firmware
+	;;
+esac
+
+exit 0

target/linux/bmips/bcm6328/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	sercomm,ad1018)
+		nand_do_upgrade "$1"
+		;;
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm6328/config-6.6

@@ -0,0 +1,310 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+# CONFIG_BCM6348_ENET is not set
+CONFIG_BCM6368_ENETSW=y
+CONFIG_BCM63XX_POWER=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CLK_BCM63268_TIMER is not set
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_BCM6368=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_BCM6318 is not set
+CONFIG_PCIE_BCM6328=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_BCM6348=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_BCM6318 is not set
+# CONFIG_PINCTRL_BCM63268 is not set
+CONFIG_PINCTRL_BCM6328=y
+# CONFIG_PINCTRL_BCM6358 is not set
+# CONFIG_PINCTRL_BCM6362 is not set
+# CONFIG_PINCTRL_BCM6368 is not set
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BCM63XX=y
+CONFIG_SPI=y
+# CONFIG_SPI_BCM63XX is not set
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm6328/target.mk

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm6328
+BOARDNAME:=BCM6328 based boards
+FEATURES+=nand
+
+define Target/Description
+  Build firmware images for Broadcom BCM6328 based boards.
+endef

target/linux/bmips/bcm6358/base-files/etc/board.d/01_leds

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+huawei,hg556a-b)
+	ucidef_set_led_usbport "usb" "USB" "red:hspa" "1-1-port1" "1-1-port2" "usb1-port2" "usb2-port2"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6358/base-files/etc/board.d/02_network

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+huawei,hg556a-b)
+	ucidef_set_interface_lan "eth0"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6358/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom

@@ -0,0 +1,34 @@
+#!/bin/sh
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions/caldata.sh
+
+caldata_extract_swap() {
+	local part=$1
+	local offset=$2
+	local count=$3
+	local mtd
+
+	mtd=$(find_mtd_chardev $part)
+	[ -n "$mtd" ] || caldata_die "no mtd device found for partition $part"
+
+	offset=$(($offset / 2))
+	count=$(($count / 2))
+
+	dd if=$mtd of=/lib/firmware/$FIRMWARE bs=2 skip=$offset count=$count conv=swab 2>/dev/null || \
+		caldata_die "failed to extract calibration data from $mtd"
+}
+
+case "$FIRMWARE" in
+	"ath9k-eeprom-pci-0000:00:01.0.bin")
+		case "$(board_name)" in
+			huawei,hg556a-b)
+				caldata_extract_swap "cal_data" 0x1e000 0xeb8
+				;;
+			*)
+				caldata_die "board $board is not supported yet"
+				;;
+		esac
+		;;
+esac

target/linux/bmips/bcm6358/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm6358/config-6.6

@@ -0,0 +1,290 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+CONFIG_BCM6348_ENET=y
+# CONFIG_BCM6368_ENETSW is not set
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CLK_BCM63268_TIMER is not set
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+# CONFIG_MDIO_BUS_MUX_BCM6368 is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+# CONFIG_PCIE_BCM6318 is not set
+# CONFIG_PCIE_BCM6328 is not set
+CONFIG_PCI_BCM6348=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_BCM6318 is not set
+# CONFIG_PINCTRL_BCM63268 is not set
+# CONFIG_PINCTRL_BCM6328 is not set
+CONFIG_PINCTRL_BCM6358=y
+# CONFIG_PINCTRL_BCM6362 is not set
+# CONFIG_PINCTRL_BCM6368 is not set
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_BCM63XX is not set
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm6358/target.mk

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm6358
+BOARDNAME:=BCM6358 based boards
+FEATURES+=low_mem
+
+define Target/Description
+  Build firmware images for Broadcom BCM6358 based boards.
+endef

target/linux/bmips/bcm6362/base-files/etc/board.d/01_leds

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+huawei,hg253s-v2)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	;;
+netgear,dgnd3700-v2)
+	ucidef_set_led_usbport "usb1" "USB1" "green:usb1" "usb1-port1" "usb2-port1"
+	ucidef_set_led_usbport "usb2" "USB2" "green:usb2" "usb1-port2" "usb2-port2"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6362/base-files/etc/board.d/02_network

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+huawei,hg253s-v2 |\
+netgear,dgnd3700-v2)
+	ucidef_set_bridge_device switch
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6362/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	huawei,hg253s-v2 |\
+	netgear,dgnd3700-v2)
+		CI_JFFS2_CLEAN_MARKERS=1
+		nand_do_upgrade "$1"
+		;;
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm6362/config-6.6

@@ -0,0 +1,311 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+# CONFIG_BCM6348_ENET is not set
+CONFIG_BCM6368_ENETSW=y
+CONFIG_BCM63XX_POWER=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CLK_BCM63268_TIMER is not set
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_BCM6368=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_BCM6318 is not set
+CONFIG_PCIE_BCM6328=y
+CONFIG_PCIE_PME=y
+# CONFIG_PCI_BCM6348 is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_BCM6318 is not set
+# CONFIG_PINCTRL_BCM63268 is not set
+# CONFIG_PINCTRL_BCM6328 is not set
+# CONFIG_PINCTRL_BCM6358 is not set
+CONFIG_PINCTRL_BCM6362=y
+# CONFIG_PINCTRL_BCM6368 is not set
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BCM63XX=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm6362/target.mk

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm6362
+BOARDNAME:=BCM6362 based boards
+FEATURES+=nand
+
+define Target/Description
+  Build firmware images for Broadcom BCM6362 based boards.
+endef

target/linux/bmips/bcm6368/base-files/etc/board.d/01_leds

@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+actiontec,r1000h)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan"
+	;;
+comtrend,wap-5813n)
+	ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1"
+	;;
+netgear,dgnd3700-v1 |\
+netgear,dgnd3800b)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "switch.1"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan"
+	ucidef_set_led_netdev "wlan0" "WIFI2G" "green:wifi2g" "phy0-ap0"
+	ucidef_set_led_netdev "wlan1" "WIFI5G" "blue:wifi5g" "phy1-ap0"
+	ucidef_set_led_usbport "usb1" "USB1" "green:usb1" "usb1-port1" "usb2-port1"
+	ucidef_set_led_usbport "usb2" "USB2" "green:usb2" "usb1-port2" "usb2-port2"
+	;;
+netgear,evg2000)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "switch.1"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan"
+	ucidef_set_led_usbdev "usb" "USB" "green:usb" "usb1-port1" "usb2-port1" "usb1-port2" "usb2-port2"
+	;;
+observa,vh4032n)
+	ucidef_set_led_usbport "usb1" "USB1" "blue:hspa" "usb1-port1" "usb2-port1"
+	ucidef_set_led_usbport "usb2" "USB2" "red:hspa" "1-2-port1" "1-2-port2"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6368/base-files/etc/board.d/02_network

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+comtrend,vr-3025u |\
+observa,vh4032n)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+	;;
+comtrend,vr-3025un)
+	ucidef_set_bridge_device switch
+	ucidef_set_interface_lan "lan1 lan2 lan3 iptv"
+	;;
+actiontec,r1000h |\
+comtrend,wap-5813n |\
+netgear,dgnd3700-v1 |\
+netgear,dgnd3800b |\
+netgear,evg2000)
+	ucidef_set_bridge_device switch
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/bmips/bcm6368/base-files/etc/uci-defaults/09_fix_crc

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions.sh
+
+case "$(board_name)" in
+actiontec,r1000h |\
+comtrend,vr-3025u |\
+comtrend,vr-3025un |\
+comtrend,wap-5813n |\
+netgear,evg2000 |\
+observa,vh4032n)
+	mtd fixtrx firmware
+	;;
+esac
+
+exit 0

target/linux/bmips/bcm6368/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	case "$(board_name)" in
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/bmips/bcm6368/config-6.6

@@ -0,0 +1,306 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_L1_IRQ=y
+# CONFIG_BCM6348_ENET is not set
+CONFIG_BCM6368_ENETSW=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BMIPS_GENERIC=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CLK_BCM63268_TIMER is not set
+CONFIG_CLK_BCM_63XX_GATE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_BCM93384WVG is not set
+# CONFIG_DT_BCM93384WVG_VIPER is not set
+# CONFIG_DT_BCM96368MVWG is not set
+# CONFIG_DT_BCM97125CBMB is not set
+# CONFIG_DT_BCM97346DBSMB is not set
+# CONFIG_DT_BCM97358SVMB is not set
+# CONFIG_DT_BCM97360SVMB is not set
+# CONFIG_DT_BCM97362SVMB is not set
+# CONFIG_DT_BCM97420C is not set
+# CONFIG_DT_BCM97425SVMB is not set
+# CONFIG_DT_BCM97435SVMB is not set
+# CONFIG_DT_BCM9EJTAGPRB is not set
+# CONFIG_DT_COMTREND_VR3032U is not set
+# CONFIG_DT_NETGEAR_CVG834G is not set
+CONFIG_DT_NONE=y
+# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set
+# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CFE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_REGMAP=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
+# CONFIG_LEDS_SERCOMM_MSP430 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_BCM6368=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_O32_FP64_SUPPORT=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MTD_BCM63XX_PARTS is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+# CONFIG_MTD_PARSER_IMAGETAG is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BCM63XX_FW=y
+CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+# CONFIG_PCIE_BCM6318 is not set
+# CONFIG_PCIE_BCM6328 is not set
+CONFIG_PCI_BCM6348=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x80010000
+CONFIG_PHY_BCM63XX_USBH=y
+# CONFIG_PHY_BRCM_SATA is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_BCM6318 is not set
+# CONFIG_PINCTRL_BCM63268 is not set
+# CONFIG_PINCTRL_BCM6328 is not set
+# CONFIG_PINCTRL_BCM6358 is not set
+# CONFIG_PINCTRL_BCM6362 is not set
+CONFIG_PINCTRL_BCM6368=y
+CONFIG_PINCTRL_BCM63XX=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_BCM6345=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_BCM63XX is not set
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_BMIPS4350=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TARGET_ISA_REV=0
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/bmips/bcm6368/target.mk

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+SUBTARGET:=bcm6368
+BOARDNAME:=BCM6368 based boards
+FEATURES+=nand
+
+define Target/Description
+  Build firmware images for Broadcom BCM6368 based boards.
+endef

target/linux/bmips/dts/bcm63167-sercomm-h500-s-lowi.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63167-sercomm-h500-s.dtsi"
+
+/ {
+	model = "Sercomm H500-s lowi";
+	compatible = "sercomm,h500-s-lowi", "brcm,bcm63167", "brcm,bcm63268";
+};

target/linux/bmips/dts/bcm63167-sercomm-h500-s-vfes.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63167-sercomm-h500-s.dtsi"
+
+/ {
+	model = "Sercomm H500-s vfes";
+	compatible = "sercomm,h500-s-vfes", "brcm,bcm63167", "brcm,bcm63268";
+};

target/linux/bmips/dts/bcm63167-sercomm-h500-s.dtsi

@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <dt-bindings/leds/common.h>
+
+#include "bcm63268.dtsi"
+
+/ {
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	led@0 {
+		reg = <0>;
+		label = "red:mobile";
+	};
+
+	led@1 {
+		reg = <1>;
+		label = "green:mobile";
+	};
+
+	led_power_red: led@8 {
+		reg = <8>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led@9 {
+		reg = <9>;
+		label = "green:wifi";
+	};
+
+	led@12 {
+		reg = <12>;
+		label = "red:phone";
+	};
+
+	led@13 {
+		reg = <13>;
+		label = "red:wifi";
+	};
+
+	led@14 {
+		reg = <14>;
+		label = "red:internet";
+	};
+
+	led@15 {
+		reg = <15>;
+		label = "green:internet";
+	};
+
+	led@16 {
+		reg = <16>;
+		label = "green:phone";
+	};
+
+	led_power_green: led@17 {
+		reg = <17>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@23 {
+		reg = <23>;
+		label = "blue:mobile";
+	};
+};
+
+&mdio_int {
+	phy12: ethernet-phy@c {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <12>;
+	};
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53134";
+		reg = <30>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "wifi";
+
+				phy-mode = "rgmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii-txid";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <4>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@20000 {
+				label = "part_map";
+				reg = <0x0020000 0x00a0000>;
+				read-only;
+			};
+
+			partition@c0000 {
+				label = "cferam1";
+				reg = <0x00c0000 0x0140000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "cferam2";
+				reg = <0x0200000 0x0140000>;
+				read-only;
+			};
+
+			partition@6920000 {
+				label = "bootflag1";
+				reg = <0x6920000 0x0140000>;
+			};
+
+			partition@6a60000 {
+				label = "bootflag2";
+				reg = <0x6a60000 0x0140000>;
+			};
+
+			partition@520000 {
+				compatible = "sercomm,wfi";
+				label = "wfi";
+				reg = <0x0520000 0x6400000>;
+			};
+
+			partition@6ba0000 {
+				label = "xml_cfg";
+				reg = <0x6ba0000 0x0280000>;
+				read-only;
+			};
+
+			partition@6e20000 {
+				label = "app_data";
+				reg = <0x6e20000 0x0280000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		port@3 {
+			reg = <3>;
+			label = "wan";
+
+			phy-handle = <&phy12>;
+			phy-mode = "gmii";
+		};
+
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii-txid";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio0",  "gpio1",  "gpio8",  "gpio9",
+		       "gpio12", "gpio13", "gpio14", "gpio15",
+		       "gpio16", "gpio17", "gpio23";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts

@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63268.dtsi"
+
+/ {
+	model = "Comtrend VR-3032u";
+	compatible = "comtrend,vr-3032u", "brcm,bcm63168", "brcm,bcm63268";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_green;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+
+	brcm,serial-leds;
+	brcm,serial-dat-low;
+	brcm,serial-shift-inv;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_serial_led>;
+
+	led@0 {
+		/* GPHY0 Spd 0 */
+		reg = <0>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <0>;
+	};
+
+	led@1 {
+		/* GPHY0 Spd 1 */
+		reg = <1>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <1>;
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@7 {
+		reg = <7>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@8 {
+		reg = <8>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@9 {
+		/* EPHY0 Act */
+		reg = <9>;
+		brcm,hardware-controlled;
+	};
+
+	led@10 {
+		/* EPHY1 Act */
+		reg = <10>;
+		brcm,hardware-controlled;
+	};
+
+	led@11 {
+		/* EPHY2 Act */
+		reg = <11>;
+		brcm,hardware-controlled;
+	};
+
+	led@12 {
+		/* GPHY0 Act */
+		reg = <12>;
+		brcm,hardware-controlled;
+	};
+
+	led@13 {
+		/* EPHY0 Spd */
+		reg = <13>;
+		brcm,hardware-controlled;
+	};
+
+	led@14 {
+		/* EPHY1 Spd */
+		reg = <14>;
+		brcm,hardware-controlled;
+	};
+
+	led@15 {
+		/* EPHY2 Spd */
+		reg = <15>;
+		brcm,hardware-controlled;
+	};
+
+	led_power_green: led@20 {
+		reg = <20>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@20000 {
+				compatible = "brcm,wfi-split";
+				label = "wfi";
+				reg = <0x0020000 0x7ac0000>;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan2";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan4";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm63168-sagem-fast-3864-op.dts

@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63268.dtsi"
+
+/ {
+	model = "Sagemcom F@ST 3864 OP";
+	compatible = "sagem,fast-3864-op", "brcm,bcm63168", "brcm,bcm63268";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+	brcm,serial-leds;
+	brcm,serial-dat-low;
+	brcm,serial-shift-inv;
+	brcm,serial-mux;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds &pinctrl_serial_led>;
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	led@4 {
+		reg = <4>;
+		active-low;
+		label = "green:fxs";
+	};
+
+	led@5 {
+		reg = <5>;
+		active-low;
+		label = "red:fxs";
+	};
+
+	led@8 {
+		reg = <8>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@9 {
+		reg = <9>;
+		active-low;
+		label = "green:dsl_bonding";
+	};
+
+	led_power_red: led@15 {
+		reg = <15>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led_power_green: led@20 {
+		reg = <20>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53125";
+		reg = <0x1e>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					asym-pause;
+					pause;
+				};
+			};
+		};
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom_nvram";
+				reg = <0x00000000 0x00020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@20000 {
+				compatible = "brcm,wfi-split";
+				label = "wfi";
+				reg = <0x00020000 0x7ac0000>;
+			};
+
+			partition@7ae0000 {
+				label = "stock_hidden1";
+				reg = <0x07ae0000 0x0020000>;
+				read-only;
+			};
+
+			partition@7b00000 {
+				label = "stock_data";
+				reg = <0x07b00000 0x0400000>;
+				read-only;
+			};
+
+			partition@7f00000 {
+				label = "stock_hidden2";
+				reg = <0x07f00000 0x0100000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio8", "gpio9", "gpio15",
+		       "gpio20";
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		port@3 {
+			reg = <3>;
+			label = "wan";
+
+			phy-handle = <&phy4>;
+		};
+
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm63168-sercomm-shg2500.dts

@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63268.dtsi"
+
+/ {
+	model = "Sercomm SHG2500";
+	compatible = "sercomm,shg2500", "brcm,bcm63168", "brcm,bcm63268";
+
+	aliases {
+		led-boot = &led_power_red;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_red;
+		led-upgrade = &led_power_red;
+	};
+
+	i2c {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm4360-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cferom_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm4360-sprom.bin";
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	led-controller@1 {
+		compatible = "sercomm,msp430-leds";
+		reg = <1>;
+		spi-max-frequency = <500000>;
+
+		led@1 {
+			reg = <1>;
+			label = "red:modem";
+		};
+
+		led@2 {
+			reg = <2>;
+			label = "green:modem";
+		};
+
+		led@3 {
+			reg = <3>;
+			label = "blue:modem";
+		};
+
+		led@4 {
+			reg = <4>;
+			label = "red:internet";
+		};
+
+		led@5 {
+			reg = <5>;
+			label = "red:phone";
+		};
+
+		led@6 {
+			reg = <6>;
+			label = "green:phone";
+		};
+
+		led@7 {
+			reg = <7>;
+			label = "green:wifi";
+		};
+
+		led_power_red: led@8 {
+			reg = <8>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@9 {
+			reg = <9>;
+			label = "green:internet";
+		};
+	};
+};
+
+&mdio_int {
+	phy12: ethernet-phy@c {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <12>;
+	};
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53125";
+		reg = <30>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan1";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan3";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan4";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@20000 {
+				label = "part_map";
+				reg = <0x0020000 0x00a0000>;
+				read-only;
+			};
+
+			partition@c0000 {
+				label = "cferam1";
+				reg = <0x00c0000 0x0140000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "cferam2";
+				reg = <0x0200000 0x0140000>;
+				read-only;
+			};
+
+			artition@6920000 {
+				label = "bootflag1";
+				reg = <0x6920000 0x0140000>;
+			};
+
+			partition@6a60000 {
+				label = "bootflag2";
+				reg = <0x6a60000 0x0140000>;
+			};
+
+			partition@520000 {
+				compatible = "sercomm,wfi";
+				label = "wfi";
+				reg = <0x0520000 0x6400000>;
+			};
+
+			partition@6ba0000 {
+				label = "xml_cfg";
+				reg = <0x6ba0000 0x0280000>;
+				read-only;
+			};
+
+			partition@6e20000 {
+				label = "app_data";
+				reg = <0x6e20000 0x0280000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_uart1: uart1-pins {
+		pinctrl_uart1_sdin: uart1_sdin {
+			function = "uart1_sdin";
+			pins = "gpio12";
+		};
+
+		pinctrl_uart1_sdout: uart1_sdout {
+			function = "uart1_sdout";
+			pins = "gpio13";
+		};
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		port@3 {
+			reg = <3>;
+			label = "wan";
+
+			phy-handle = <&phy12>;
+			phy-mode = "gmii";
+		};
+
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm63168-smartrg-sr505n.dts

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63268.dtsi"
+
+/ {
+	model = "SmartRG SR505n";
+	compatible = "smartrg,sr505n", "brcm,bcm63168", "brcm,bcm63268";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+		
+		reset {
+			label = "reset";
+			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+   			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cfe";
+				reg = <0x000000 0x010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				label = "firmware";
+				reg = <0x010000 0xfd0000>;
+			};
+
+			partition@fe0000 {
+				label = "nvram";
+				reg = <0xfe0000 0x020000>;
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	wps_green@1 {
+		reg = <1>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	inet_green@8 {
+		reg = <8>;
+		active-low;
+		label = "green:inet";
+	};
+
+	lan2_green@9 {
+		/* EPHY1 Act */
+		reg = <9>;
+		brcm,hardware-controlled;
+	};
+
+	lan3_green@10 {
+		/* EPHY2 Act */
+		reg = <10>;
+		brcm,hardware-controlled;
+	};
+
+	lan4_green@11 {
+		/* EPHY3 Act */
+		reg = <11>;
+		brcm,hardware-controlled;
+	};
+
+	lan1_green@12 {
+		/* GPHY0 Act */
+		reg = <12>;
+		brcm,hardware-controlled;
+	};
+
+	dsl_green@14 {
+		reg = <14>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	inet_red@15 {
+		reg = <15>;
+		active-low;
+		label = "red:inet";
+	};
+
+	usb_green@16 {
+		reg = <16>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led_power_green: power_green@20 {
+		reg = <20>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led_power_red: power_red@21 {
+		reg = <21>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1", "gpio8", 
+			"gpio9", "gpio10",
+			"gpio11", "gpio12",
+			"gpio14", "gpio15",
+			"gpio16", "gpio20",
+			"gpio21";
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan2";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan4";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "gmii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm63169-comtrend-vg-8050.dts

@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm63268.dtsi"
+
+/ {
+	model = "Comtrend VG-8050";
+	compatible = "comtrend,vg-8050", "brcm,bcm63169", "brcm,bcm63268";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hsspi_cs5>;
+
+	switch@5 {
+		compatible = "brcm,bcm53125";
+		reg = <5>;
+		spi-max-frequency = <781000>;
+		spi-cpha;
+		spi-cpol;
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan4";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "wan";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port6>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	brcm,serial-leds;
+	brcm,serial-dat-low;
+	brcm,serial-shift-inv;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_serial_led>;
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led_power_red: led@3 {
+		reg = <3>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led_power_green: led@6 {
+		reg = <6>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@7 {
+		reg = <7>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@8 {
+		reg = <8>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@10 {
+		reg = <10>;
+		active-low;
+		label = "green:voip";
+	};
+
+	led@12 {
+		reg = <12>;
+		active-low;
+		label = "red:voip";
+	};
+
+	led@14 {
+		reg = <14>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@20000 {
+				compatible = "brcm,wfi-split";
+				label = "wfi";
+				reg = <0x0020000 0x7ac0000>;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port6: port@6 {
+			reg = <6>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts

@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6318.dtsi"
+
+/ {
+	model = "Comtrend AR-5315u";
+	compatible = "comtrend,ar-5315u", "brcm,bcm6318";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm43217-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43217-sprom.bin";
+		brcm,sprom-fixups = <6 0x1c00>,
+				    <65 0x1255>,
+				    <97 0xfe55>,
+				    <98 0x171d>,
+				    <99 0xfa42>,
+				    <113 0xfeb7>,
+				    <114 0x18cd>,
+				    <115 0xfa4f>,
+				    <162 0x6444>,
+				    <170 0x6444>,
+				    <172 0x6444>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <62500000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x010000>;
+				label = "cfe";
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				reg = <0x010000 0xfe0000>;
+				label = "firmware";
+			};
+
+			partition@ff0000 {
+				reg = <0xff0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds
+		     &pinctrl_ephy0_act_led &pinctrl_ephy1_act_led
+		     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led_power_green: led@1 {
+		reg = <1>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@4 {
+		/* EPHY0 Act */
+		reg = <4>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <4>;
+	};
+
+	led@5 {
+		/* EPHY1 Act */
+		reg = <5>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <5>;
+	};
+
+	led@6 {
+		/* EPHY2 Act */
+		reg = <6>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <6>;
+	};
+
+	led@7 {
+		/* EPHY3 Act */
+		reg = <7>;
+		brcm,hardware-controlled;
+		brcm,link-signal-sources = <7>;
+	};
+
+	led@8 {
+		reg = <8>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@9 {
+		reg = <9>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@10 {
+		reg = <10>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	led_power_red: led@11 {
+		reg = <11>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio0", "gpio1",
+		       "gpio2", "gpio8",
+		       "gpio9", "gpio10",
+		       "gpio11";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan4";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6318.dtsi

@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm6318-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm6318-reset.h>
+#include <dt-bindings/soc/bcm6318-pm.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm6318";
+
+	aliases {
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		spi1 = &hsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+
+		hsspi_osc: hsspi-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <250000000>;
+			clock-output-names = "hsspi_osc";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-hpt-frequency = <166500000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips3300", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@10000004 {
+			compatible = "brcm,bcm6318-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		ubus_clk: clock-controller@10000008 {
+			compatible = "brcm,bcm6318-ubus-clocks";
+			reg = <0x10000008 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		ext_intc: interrupt-controller@10000018 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6318-ext-intc";
+			reg = <0x10000018 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_EXT0>,
+				     <BCM6318_IRQ_EXT1>,
+				     <BCM6318_IRQ_EXT2>,
+				     <BCM6318_IRQ_EXT3>;
+		};
+
+		periph_intc: interrupt-controller@10000020 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0x10000020 0x20>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		wdt: watchdog@10000068 {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0x10000068 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		pll_cntl: syscon@10000074 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10000074 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0>;
+				mask = <0x1>;
+			};
+		};
+
+		gpio_cntl: syscon@10000080 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6318-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0x10000080 0x80>;
+			ranges = <0 0x10000080 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm6318-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 50>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@18 {
+				compatible = "brcm,bcm6318-pinctrl";
+				reg = <0x18 0x10>, <0x54 0x18>;
+
+				pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
+					function = "ephy0_spd_led";
+					pins = "gpio0";
+				};
+
+				pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
+					function = "ephy1_spd_led";
+					pins = "gpio1";
+				};
+
+				pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
+					function = "ephy2_spd_led";
+					pins = "gpio2";
+				};
+
+				pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
+					function = "ephy3_spd_led";
+					pins = "gpio3";
+				};
+
+				pinctrl_ephy0_act_led: ephy0_act_led-pins {
+					function = "ephy0_act_led";
+					pins = "gpio4";
+				};
+
+				pinctrl_ephy1_act_led: ephy1_act_led-pins {
+					function = "ephy1_act_led";
+					pins = "gpio5";
+				};
+
+				pinctrl_ephy2_act_led: ephy2_act_led-pins {
+					function = "ephy2_act_led";
+					pins = "gpio6";
+				};
+
+				pinctrl_ephy3_act_led: ephy3_act_led-pins {
+					function = "ephy3_act_led";
+					pins = "gpio7";
+				};
+
+				pinctrl_serial_led: serial_led-pins {
+					pinctrl_serial_led_data: serial_led_data-pins {
+						function = "serial_led_data";
+						pins = "gpio6";
+					};
+
+					pinctrl_serial_led_clk: serial_led_clk-pins {
+						function = "serial_led_clk";
+						pins = "gpio7";
+					};
+				};
+
+				pinctrl_inet_act_led: inet_act_led-pins {
+					function = "inet_act_led";
+					pins = "gpio8";
+				};
+
+				pinctrl_inet_fail_led: inet_fail_led-pins {
+					function = "inet_fail_led";
+					pins = "gpio9";
+				};
+
+				pinctrl_dsl_led: dsl_led-pins {
+					function = "dsl_led";
+					pins = "gpio10";
+				};
+
+				pinctrl_post_fail_led: post_fail_led-pins {
+					function = "post_fail_led";
+					pins = "gpio11";
+				};
+
+				pinctrl_wlan_wps_led: wlan_wps_led-pins {
+					function = "wlan_wps_led";
+					pins = "gpio12";
+				};
+
+				pinctrl_usb_pwron: usb_pwron-pins {
+					function = "usb_pwron";
+					pins = "gpio13";
+				};
+
+				pinctrl_usb_device_led: usb_device_led-pins {
+					function = "usb_device_led";
+					pins = "gpio13";
+				};
+
+				pinctrl_usb_active: usb_active-pins {
+					function = "usb_active";
+					pins = "gpio40";
+				};
+			};
+		};
+
+		uart0: serial@10000100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000100 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		leds: led-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x10000200 0x24>;
+
+			status = "disabled";
+		};
+
+		periph_pwr: power-controller@100008e8 {
+			compatible = "brcm,bcm6318-power-controller";
+			reg = <0x100008e8 0x4>;
+
+			#power-domain-cells = <1>;
+		};
+
+		hsspi: spi@10003000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0x10003000 0x600>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_HSSPI>;
+
+			clocks = <&periph_clk BCM6318_CLK_HSSPI>,
+				 <&hsspi_osc>;
+			clock-names = "hsspi",
+				      "pll";
+
+			resets = <&periph_rst BCM6318_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		ehci: usb@10005000 {
+			compatible = "brcm,bcm6318-ehci", "generic-ehci";
+			reg = <0x10005000 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@10005100 {
+			compatible = "brcm,bcm6318-ohci", "generic-ohci";
+			reg = <0x10005100 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@10005200 {
+			compatible = "brcm,bcm6318-usbh-phy";
+			reg = <0x10005200 0x38>;
+
+			#phy-cells = <1>;
+
+			clocks = <&periph_clk BCM6318_CLK_USBD>,
+				 <&ubus_clk BCM6318_UCLK_USB>;
+			clock-names = "usbh",
+				      "usb_ref";
+
+			power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_USB>;
+			resets = <&periph_rst BCM6318_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		pcie: pcie@10010000 {
+			compatible = "brcm,bcm6318-pcie";
+			reg = <0x10010000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_PCIE_RC>;
+
+			clocks = <&periph_clk BCM6318_CLK_PCIE>,
+				 <&periph_clk BCM6318_CLK_PCIE25>,
+				 <&ubus_clk BCM6318_UCLK_PCIE>;
+			clock-names = "pcie",
+				      "pcie25",
+				      "pcie-ubus";
+
+			resets = <&periph_rst BCM6318_RST_PCIE>,
+				 <&periph_rst BCM6318_RST_PCIE_EXT>,
+				 <&periph_rst BCM6318_RST_PCIE_CORE>,
+				 <&periph_rst BCM6318_RST_PCIE_HARD>;
+			reset-names = "pcie",
+				      "pcie-ext",
+				      "pcie-core",
+				      "pcie-hard";
+
+			power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;
+
+			status = "disabled";
+		};
+
+		switch0: switch@10080000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6318-switch";
+			reg = <0x10080000 0x8000>;
+			big-endian;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					phy-mode = "internal";
+					ethernet = <&ethernet>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+
+		mdio: mdio@100800b0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-mdio-mux";
+			reg = <0x100800b0 0x8>;
+
+			mdio_int: mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
+
+				phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+				};
+
+				phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+				};
+
+				phy4: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <4>;
+				};
+			};
+
+			mdio_ext: mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>;
+			};
+		};
+
+		ethernet: ethernet@10088000 {
+			compatible = "brcm,bcm6318-enetsw";
+			reg = <0x10088000 0x80>,
+			      <0x10088200 0x80>,
+			      <0x10088400 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6318_IRQ_ENETSW_RX_DMA0>,
+				     <BCM6318_IRQ_ENETSW_TX_DMA0>;
+			interrupt-names = "rx",
+					  "tx";
+
+			clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
+				 <&periph_clk BCM6318_CLK_ROBOSW025>,
+				 <&ubus_clk BCM6318_UCLK_ROBOSW>;
+
+			resets = <&periph_rst BCM6318_RST_ENETSW>,
+				 <&periph_rst BCM6318_RST_EPHY>;
+
+			power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>,
+					<&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>,
+					<&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>,
+					<&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+		};
+	};
+};

target/linux/bmips/dts/bcm63268.dtsi

@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm63268-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm63268-reset.h>
+#include <dt-bindings/soc/bcm63268-pm.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm63268";
+
+	aliases {
+		nflash = &nflash;
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &lsspi;
+		spi1 = &hsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+
+		hsspi_osc: hsspi-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <400000000>;
+			clock-output-names = "hsspi_osc";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-hpt-frequency = <200000000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@10000004 {
+			compatible = "brcm,bcm63268-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		pll_cntl: syscon@10000008 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10000008 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0x0>;
+				mask = <0x1>;
+			};
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		ext_intc: interrupt-controller@10000018 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0x10000018 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_EXT0>,
+				     <BCM63268_IRQ_EXT1>,
+				     <BCM63268_IRQ_EXT2>,
+				     <BCM63268_IRQ_EXT3>;
+		};
+
+		periph_intc: interrupt-controller@10000020 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0x10000020 0x20>,
+			      <0x10000040 0x20>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		wdt: watchdog@1000009c {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0x1000009c 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		timer_clk: clock-controller@100000ac {
+			compatible = "brcm,bcm63268-timer-clocks";
+			reg = <0x100000ac 0x4>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		gpio_cntl: syscon@100000c0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm63268-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0x100000c0 0x80>;
+			ranges = <0 0x100000c0 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm63268-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 52>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@10 {
+				compatible = "brcm,bcm63268-pinctrl";
+				reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
+
+				pinctrl_serial_led: serial_led-pins {
+					pinctrl_serial_led_clk: serial_led_clk-pins {
+						function = "serial_led_clk";
+						pins = "gpio0";
+					};
+
+					pinctrl_serial_led_data: serial_led_data-pins {
+						function = "serial_led_data";
+						pins = "gpio1";
+					};
+				};
+
+				pinctrl_hsspi_cs4: hsspi_cs4-pins {
+					function = "hsspi_cs4";
+					pins = "gpio16";
+				};
+
+				pinctrl_hsspi_cs5: hsspi_cs5-pins {
+					function = "hsspi_cs5";
+					pins = "gpio17";
+				};
+
+				pinctrl_hsspi_cs6: hsspi_cs6-pins {
+					function = "hsspi_cs6";
+					pins = "gpio8";
+				};
+
+				pinctrl_hsspi_cs7: hsspi_cs7-pins {
+					function = "hsspi_cs7";
+					pins = "gpio9";
+				};
+
+				pinctrl_adsl_spi: adsl_spi {
+					pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
+						function = "adsl_spi_miso";
+						pins = "gpio18";
+					};
+
+					pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
+						function = "adsl_spi_mosi";
+						pins = "gpio19";
+					};
+				};
+
+				pinctrl_vreq_clk: vreq_clk-pins {
+					function = "vreq_clk";
+					pins = "gpio22";
+				};
+
+				pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
+					function = "pcie_clkreq_b";
+					pins = "gpio23";
+				};
+
+				pinctrl_robosw_led_clk: robosw_led_clk-pins {
+					function = "robosw_led_clk";
+					pins = "gpio30";
+				};
+
+				pinctrl_robosw_led_data: robosw_led_data-pins {
+					function = "robosw_led_data";
+					pins = "gpio31";
+				};
+
+				pinctrl_nand: nand-pins {
+					function = "nand";
+					group = "nand_grp";
+				};
+
+				pinctrl_gpio35_alt: gpio35_alt-pins {
+					function = "gpio35_alt";
+					pin = "gpio35";
+				};
+
+				pinctrl_dectpd: dectpd-pins {
+					function = "dectpd";
+					group = "dectpd_grp";
+				};
+
+				pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
+					function = "vdsl_phy_override_0";
+					group = "vdsl_phy_override_0_grp";
+				};
+
+				pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
+					function = "vdsl_phy_override_1";
+					group = "vdsl_phy_override_1_grp";
+				};
+
+				pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
+					function = "vdsl_phy_override_2";
+					group = "vdsl_phy_override_2_grp";
+				};
+
+				pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
+					function = "vdsl_phy_override_3";
+					group = "vdsl_phy_override_3_grp";
+				};
+
+				pinctrl_dsl_gpio8: dsl_gpio8-pins {
+					function = "dsl_gpio8";
+					group = "dsl_gpio8";
+				};
+
+				pinctrl_dsl_gpio9: dsl_gpio9-pins {
+					function = "dsl_gpio9";
+					group = "dsl_gpio9";
+				};
+			};
+		};
+
+		uart0: serial@10000180 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000180 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		uart1: serial@100001a0 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x100001a0 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_UART1>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		nflash: nand@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v4.0",
+				     "brcm,brcmnand";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_NAND>;
+
+			clocks = <&periph_clk BCM63268_CLK_NAND>;
+			clock-names = "nand";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+
+			status = "disabled";
+		};
+
+		lsspi: spi@10000800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-spi";
+			reg = <0x10000800 0x70c>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_LSSPI>;
+
+			clocks = <&periph_clk BCM63268_CLK_SPI>;
+			clock-names = "spi";
+
+			resets = <&periph_rst BCM63268_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		hsspi: spi@10001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0x10001000 0x600>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_HSSPI>;
+
+			clocks = <&periph_clk BCM63268_CLK_HSSPI>,
+				 <&hsspi_osc>;
+			clock-names = "hsspi",
+				      "pll";
+
+			resets = <&periph_rst BCM63268_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		serdes_cntl: syscon@10001804 {
+			compatible = "syscon";
+			reg = <0x10001804 0x4>;
+			native-endian;
+		};
+
+		periph_pwr: power-controller@1000184c {
+			compatible = "brcm,bcm63268-power-controller";
+			reg = <0x1000184c 0x4>;
+			#power-domain-cells = <1>;
+		};
+
+		leds: led-controller@10001900 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x10001900 0x24>;
+
+			status = "disabled";
+		};
+
+		ehci: usb@10002500 {
+			compatible = "brcm,bcm63268-ehci", "generic-ehci";
+			reg = <0x10002500 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@10002600 {
+			compatible = "brcm,bcm63268-ohci", "generic-ohci";
+			reg = <0x10002600 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@10002700 {
+			compatible = "brcm,bcm63268-usbh-phy";
+			reg = <0x10002700 0x38>;
+
+			#phy-cells = <1>;
+
+			clocks = <&periph_clk BCM63268_CLK_USBH>,
+				 <&timer_clk BCM63268_TCLK_USB_REF>;
+			clock-names = "usbh",
+				      "usb_ref";
+
+			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
+			resets = <&periph_rst BCM63268_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		random: rng@10002880 {
+			compatible = "brcm,bcm6368-rng";
+			reg = <0x10002880 0x14>;
+
+			clocks = <&periph_clk BCM63268_CLK_IPSEC>;
+			clock-names = "ipsec";
+
+			resets = <&periph_rst BCM63268_RST_IPSEC>;
+
+			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_IPSEC>;
+		};
+
+		ethernet: ethernet@1000d800 {
+			compatible = "brcm,bcm63268-enetsw";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
+				     <BCM63268_IRQ_ENETSW_TX_DMA0>;
+			interrupt-names = "rx",
+					  "tx";
+
+			clocks = <&periph_clk BCM63268_CLK_GMAC>,
+				 <&periph_clk BCM63268_CLK_ROBOSW>,
+				 <&periph_clk BCM63268_CLK_ROBOSW250>,
+				 <&timer_clk BCM63268_TCLK_EPHY1>,
+				 <&timer_clk BCM63268_TCLK_EPHY2>,
+				 <&timer_clk BCM63268_TCLK_EPHY3>,
+				 <&timer_clk BCM63268_TCLK_GPHY1>;
+
+			resets = <&periph_rst BCM63268_RST_ENETSW>,
+				 <&periph_rst BCM63268_RST_EPHY>,
+				 <&periph_rst BCM63268_RST_GPHY>;
+
+			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+		};
+
+		pcie: pcie@106e0000 {
+			compatible = "brcm,bcm6328-pcie";
+			reg = <0x106e0000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM63268_IRQ_PCIE_RC>;
+
+			clocks = <&periph_clk BCM63268_CLK_PCIE>;
+			clock-names = "pcie";
+
+			resets = <&periph_rst BCM63268_RST_PCIE>,
+				 <&periph_rst BCM63268_RST_PCIE_EXT>,
+				 <&periph_rst BCM63268_RST_PCIE_CORE>,
+				 <&periph_rst BCM63268_RST_PCIE_HARD>;
+			reset-names = "pcie",
+				      "pcie-ext",
+				      "pcie-core",
+				      "pcie-hard";
+
+			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
+
+			brcm,serdes = <&serdes_cntl>;
+
+			status = "disabled";
+		};
+
+		switch0: switch@10700000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm63268-switch";
+			reg = <0x10700000 0x8000>;
+			big-endian;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					phy-mode = "internal";
+					ethernet = <&ethernet>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+
+		mdio: mdio@107000b0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-mdio-mux";
+			reg = <0x107000b0 0x8>;
+
+			mdio_int: mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
+
+				phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+				};
+
+				phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+				};
+
+				phy4: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <4>;
+				};
+			};
+
+			mdio_ext: mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>;
+			};
+		};
+	};
+};

target/linux/bmips/dts/bcm6328-arcadyan-ar7516.dts

@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "Arcadyan AR7516";
+	compatible = "arcadyan,ar7516", "brcm,bcm6328";
+
+	aliases {
+		led-failsafe = &led_upgrade_green;
+		led-upgrade = &led_upgrade_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm43227-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43227-sprom.bin";
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cfe";
+				reg = <0x000000 0x010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				label = "firmware";
+				reg = <0x010000 0x7e0000>;
+			};
+
+			partition@7f0000 {
+				label = "nvram";
+				reg = <0x7f0000 0x010000>;
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ephy0_act_led &pinctrl_ephy1_act_led
+		     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led
+		     &pinctrl_leds>;
+
+	led_upgrade_green: led@1 {
+		reg = <1>;
+		label = "green:upgrade";
+	};
+
+	led@6 {
+		reg = <6>;
+		active-low;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@7 {
+		reg = <7>;
+		active-low;
+		label = "green:wifi";
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1", "gpio6", "gpio7";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "wan";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328-comtrend-ar-5381u.dts

@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "Comtrend AR-5381u";
+	compatible = "comtrend,ar-5381u", "brcm,bcm6328";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_alarm_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm43225-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43225-sprom.bin";
+		brcm,sprom-fixups = <97 0xfee5>,
+				    <98 0x157c>,
+				    <99 0xfae7>,
+				    <113 0xfefa>,
+				    <114 0x15d6>,
+				    <115 0xfaf8>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x010000>;
+				label = "cfe";
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				reg = <0x010000 0xfe0000>;
+				label = "firmware";
+			};
+
+			partition@ff0000 {
+				reg = <0xff0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	led_alarm_red: led@2 {
+		reg = <2>;
+		active-low;
+		function = LED_FUNCTION_ALARM;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led_power_green: led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio2", "gpio3", "gpio4";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts

@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "Comtrend AR-5387un";
+	compatible = "comtrend,ar-5387un", "brcm,bcm6328";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm43225-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43225-sprom.bin";
+		brcm,sprom-fixups = <2 0x05bb>,
+				    <65 0x1204>,
+				    <78 0x0303>,
+				    <79 0x0202>,
+				    <80 0xff02>,
+				    <87 0x0315>,
+				    <88 0x0315>,
+				    <96 0x2048>,
+				    <97 0xff11>,
+				    <98 0x1567>,
+				    <99 0xfb24>,
+				    <100 0x3e3c>,
+				    <101 0x4038>,
+				    <102 0xfe7f>,
+				    <103 0x1279>,
+				    <112 0x2048>,
+				    <113 0xff03>,
+				    <114 0x154c>,
+				    <115 0xfb27>,
+				    <116 0x3e3c>,
+				    <117 0x4038>,
+				    <118 0xfe87>,
+				    <119 0x1233>,
+				    <203 0x2226>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x010000>;
+				label = "cfe";
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				reg = <0x010000 0xfe0000>;
+				label = "firmware";
+			};
+
+			partition@ff0000 {
+				reg = <0xff0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	led@1 {
+		reg = <1>;
+		label = "red:internet";
+	};
+
+	led_power_red: led@4 {
+		reg = <4>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led@7 {
+		reg = <7>;
+		label = "green:internet";
+	};
+
+	led_power_green: led@8 {
+		reg = <8>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@11 {
+		reg = <11>;
+		active-low;
+		label = "green:dsl";
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1", "gpio4", "gpio7",
+		       "gpio8", "gpio11";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts

@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "Innacomm W3400V6";
+	compatible = "innacomm,w3400v6", "brcm,bcm6328";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm4318-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm4318-sprom.bin";
+	};
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x000000 0x010000>;
+				label = "cfe";
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				reg = <0x010000 0x7e0000>;
+				label = "firmware";
+			};
+
+			partition@7f0000 {
+				reg = <0x7f0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	led_power_green: led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led_power_red: led@5 {
+		reg = <5>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led@11 {
+		reg = <11>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1", "gpio2", "gpio3",
+		       "gpio4", "gpio5", "gpio11";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan4";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328-inteno-xg6846.dts

@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/*
+ * Devicetree for the Inteno XG6846 router, mostly used as a
+ * media converter from fiber to twisted pair ethernet
+ * "fiber modem" in many households in Sweden. The Marvell
+ * switch has one of its ports connected to an SFP (Small Form
+ * Factor pluggable) optical fiber receiver, which is bridged
+ * to the twisted pair connector LAN1.
+ *
+ * This device tree is inspired by research from the OpenWrt
+ * and Sweclockers forums, including contributions from
+ * NPeca75, mrhaav and csom.
+ *
+ * Some devices have a USB type A host receptacle mounted,
+ * some do not.
+ */
+#include "bcm6328.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Inteno XG6846";
+	compatible = "inteno,xg6846", "brcm,bcm6328";
+
+	/* OpenWrt-specific aliases */
+	aliases {
+		led-boot = &led_pwr_red;
+		led-failsafe = &led_pwr_red;
+		led-running = &led_pwr_green;
+		led-upgrade = &led_pwr_red;
+		led-usb = &led_usb_green;
+	};
+
+	chosen {
+		bootargs = "rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
+	};
+
+	/*
+	 * This I2C port is connected to the SFP and reflects the EEPROM etc
+	 * inside the SFP module. If the module is not plugged in, consequently
+	 * nothing will be found on the bus.
+	 */
+	i2c0: i2c-sfp {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	/* This I2C bus is used for the external CATV connector (usually unused) */
+	i2c1: i2c-catv {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	sfp0: sfp0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c0>;
+		los-gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		/*
+		 * HW 1.0-1.1: Spansion S25FL128S1
+		 * HW 1.3: Winbond W25Q128
+		 *
+		 * Fast Read Data max speed is 50MHz, see the Winbond W25Q128
+		 * datasheet table 9.5 "AC Electrical Characteristics", we can
+		 * use this speed because the chip supports fast reads. Older
+		 * HW has different NOR chips, I assume they can all do fast
+		 * reads.
+		 */
+		spi-max-frequency = <104000000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		m25p,fast-read;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cfe: partition@0 {
+				label = "cfe";
+				reg = <0x0000000 0x0010000>;
+				read-only;
+			};
+
+			partition@10000 {
+				compatible = "openwrt,uimage", "denx,uimage";
+				reg = <0x010000 0xfe0000>;
+				label = "firmware";
+				openwrt,offset = <0x30000>;
+			};
+
+			partition@ff0000 {
+				reg = <0xff0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&cfe {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_cfe_6a0: macaddr@6a0 {
+		reg = <0x6a0 0x6>;
+	};
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&mdio_ext {
+	switch1: switch@0 {
+		/* The switch is not using any external IRQ, sadly */
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan1";
+				phy-handle = <&lan1phy>;
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan2";
+				phy-handle = <&lan2phy>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+				phy-handle = <&lan3phy>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan4";
+				phy-handle = <&lan4phy>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "ext1";
+				phy-handle = <&ext1phy>;
+			};
+
+			port@5 {
+				reg = <5>;
+				phy-mode = "rgmii-id";
+				label = "wan";
+				sfp = <&sfp0>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				phy-mode = "rgmii-id";
+				label = "cpu";
+				ethernet = <&switch0port4>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lan1phy: ethernet-phy@0 {
+				reg = <0>;
+				interrupt-parent = <&switch1>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan2phy: ethernet-phy@1 {
+				reg = <1>;
+				interrupt-parent = <&switch1>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan3phy: ethernet-phy@2 {
+				reg = <2>;
+				interrupt-parent = <&switch1>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan4phy: ethernet-phy@3 {
+				reg = <3>;
+				interrupt-parent = <&switch1>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			ext1phy: ethernet-phy@4 {
+				reg = <4>;
+				interrupt-parent = <&switch1>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_xg6846_usb_spd_led: xg6846_usb_spd_led-pins {
+		function = "led";
+		pins = "gpio17";
+	};
+};
+
+&leds {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_xg6846_usb_spd_led>, /* GPIO16 LED USB */
+		    <&pinctrl_ephy1_spd_led>, /* GPIO18 LED PWR red */
+		    <&pinctrl_ephy3_spd_led>; /* GPIO20 LED PWR green */
+
+	/* On board variants without USB this LED is not mounted */
+	led_usb_green: led@16 {
+		reg = <16>;
+		active-low;
+		label = "green:usb";
+		default-state = "off";
+	};
+
+	/*
+	 * LED 18 and 20 drive the same physical LED, the PWR
+	 * LED that can be both red and green.
+	 */
+	led_pwr_red: led@18 {
+		reg = <18>;
+		active-low;
+		label = "red:pwr";
+		default-state = "off";
+	};
+
+	led_pwr_green: led@20 {
+		reg = <20>;
+		active-low;
+		label = "green:pwr";
+		default-state = "off";
+	};
+
+};

target/linux/bmips/dts/bcm6328-nucom-r5010unv2.dts

@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "NuCom R5010UNv2";
+	compatible = "nucom,r5010unv2", "brcm,bcm6328";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm43217-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43217-sprom.bin";
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <16666667>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cfe";
+				reg = <0x000000 0x010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cfe_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@10000 {
+				compatible = "brcm,bcm963xx-imagetag";
+				label = "firmware";
+				reg = <0x010000 0xfe0000>;
+			};
+
+			partition@ff0000 {
+				label = "nvram";
+				reg = <0xff0000 0x010000>;
+			};
+		};
+	};
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ephy0_act_led &pinctrl_ephy1_act_led
+		     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led
+		     &pinctrl_leds>;
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@2 {
+		reg = <2>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:dsl";
+	};
+
+	led_power_green: led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led_power_red: led@5 {
+		reg = <5>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+		panic-indicator;
+	};
+
+	led@10 {
+		reg = <10>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@11 {
+		reg = <11>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1", "gpio2", "gpio3",
+		       "gpio4", "gpio5", "gpio10",
+		       "gpio11";
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts

@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6328.dtsi"
+
+/ {
+	model = "Sercomm AD1018";
+	compatible = "sercomm,ad1018", "brcm,bcm6328";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_green;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	bcm432217-sprom {
+		compatible = "brcm,bcma-sprom";
+
+		pci-bus = <1>;
+		pci-dev = <0>;
+
+		nvmem-cells = <&macaddr_cferom_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43217-sprom.bin";
+		brcm,sprom-fixups = <6 0x1c00>,
+				    <65 0x1256>,
+				    <96 0x2046>,
+				    <97 0xfe69>,
+				    <98 0x1726>,
+				    <99 0xfa5c>,
+				    <112 0x2046>,
+				    <113 0xfea8>,
+				    <114 0x1978>,
+				    <115 0xfa26>,
+				    <161 0x2222>,
+				    <169 0x2222>,
+				    <171 0x2222>,
+				    <173 0x2222>,
+				    <174 0x4444>,
+				    <175 0x2222>,
+				    <176 0x4444>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds &pinctrl_serial_led
+		     &pinctrl_ephy0_spd_led &pinctrl_ephy1_act_led
+		     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;
+
+	brcm,serial-leds;
+	brcm,serial-shift-inv;
+	brcm,serial-dat-low;
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		label = "red:internet";
+	};
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led_power_green: led@8 {
+		reg = <8>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@10 {
+		reg = <10>;
+		active-low;
+		label = "green:adsl";
+	};
+
+	led@11 {
+		reg = <11>;
+		active-low;
+		label = "red:adsl";
+	};
+
+	led@12 {
+		reg = <12>;
+		active-low;
+		label = "green:phone";
+	};
+
+	led@13 {
+		reg = <13>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@14 {
+		reg = <14>;
+		active-low;
+		label = "green:wifi";
+	};
+
+	led@15 {
+		reg = <15>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@17 {
+		/* EPHY0 Spd */
+		reg = <17>;
+		brcm,hardware-controlled;
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio0", "gpio1";
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						compatible = "mac-base";
+						reg = <0x6a0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@20000 {
+				label = "mmap";
+				reg = <0x0020000 0x00a0000>;
+				read-only;
+			};
+
+			partition@c0000 {
+				label = "cferam1";
+				reg = <0x00c0000 0x0140000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "cferam2";
+				reg = <0x0200000 0x0140000>;
+				read-only;
+			};
+
+			partition@340000 {
+				label = "serial";
+				reg = <0x0340000 0x00a0000>;
+				read-only;
+			};
+
+			partition@3e0000 {
+				label = "protect";
+				reg = <0x03e0000 0x0140000>;
+				read-only;
+			};
+
+			partition@6920000 {
+				label = "bootflag1";
+				reg = <0x6920000 0x0140000>;
+				read-only;
+			};
+
+			partition@6a60000 {
+				label = "bootflag2";
+				reg = <0x6a60000 0x0140000>;
+				read-only;
+			};
+
+			partition@520000 {
+				compatible = "sercomm,wfi";
+				label = "wfi";
+				reg = <0x0520000 0x6400000>;
+			};
+
+			partition@6ba0000 {
+				label = "xml_cfg";
+				reg = <0x6ba0000 0x0280000>;
+				read-only;
+			};
+
+			partition@6e20000 {
+				label = "app_dat";
+				reg = <0x6e20000 0x0280000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "fibre";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6328.dtsi

@@ -0,0 +1,510 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm6328-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm6328-reset.h>
+#include <dt-bindings/soc/bcm6328-pm.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm6328";
+
+	aliases {
+		nflash = &nflash;
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi1 = &hsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+
+		hsspi_osc: hsspi-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <133333333>;
+			clock-output-names = "hsspi_osc";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-hpt-frequency = <160000000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@10000004 {
+			compatible = "brcm,bcm6328-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		ext_intc: interrupt-controller@10000018 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0x10000018 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_EXTO>,
+				     <BCM6328_IRQ_EXT1>,
+				     <BCM6328_IRQ_EXT2>,
+				     <BCM6328_IRQ_EXT3>;
+		};
+
+		periph_intc: interrupt-controller@10000020 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0x10000020 0x10>,
+			      <0x10000030 0x10>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		wdt: watchdog@1000005c {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0x1000005c 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		pll_cntl: syscon@10000068 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10000068 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0>;
+				mask = <0x1>;
+			};
+		};
+
+		gpio_cntl: syscon@10000080 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6328-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0x10000080 0x80>;
+			ranges = <0 0x10000080 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm6328-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 32>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@18 {
+				compatible = "brcm,bcm6328-pinctrl";
+				reg = <0x18 0x10>;
+
+				pinctrl_serial_led: serial_led-pins {
+					pinctrl_serial_led_data: serial_led_data-pins {
+						function = "serial_led_data";
+						pins = "gpio6";
+					};
+
+					pinctrl_serial_led_clk: serial_led_clk-pins {
+						function = "serial_led_clk";
+						pins = "gpio7";
+					};
+				};
+
+				pinctrl_inet_act_led: inet_act_led-pins {
+					function = "inet_act_led";
+					pins = "gpio11";
+				};
+
+				pinctrl_pcie_clkreq: pcie_clkreq-pins {
+					function = "pcie_clkreq";
+					pins = "gpio16";
+				};
+
+				pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
+					function = "led";
+					pins = "gpio17";
+				};
+
+				pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
+					function = "led";
+					pins = "gpio18";
+				};
+
+				pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
+					function = "led";
+					pins = "gpio19";
+				};
+
+				pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
+					function = "led";
+					pins = "gpio20";
+				};
+
+				pinctrl_ephy0_act_led: ephy0_act_led-pins {
+					function = "ephy0_act_led";
+					pins = "gpio25";
+				};
+
+				pinctrl_ephy1_act_led: ephy1_act_led-pins {
+					function = "ephy1_act_led";
+					pins = "gpio26";
+				};
+
+				pinctrl_ephy2_act_led: ephy2_act_led-pins {
+					function = "ephy2_act_led";
+					pins = "gpio27";
+				};
+
+				pinctrl_ephy3_act_led: ephy3_act_led-pins {
+					function = "ephy3_act_led";
+					pins = "gpio28";
+				};
+
+				pinctrl_hsspi_cs1: hsspi_cs1-pins {
+					function = "hsspi_cs1";
+					pins = "hsspi_cs1";
+				};
+
+				pinctrl_usb_port1_device: usb_port1_device-pins {
+					function = "usb_device_port";
+					pins = "usb_port1";
+				};
+
+				pinctrl_usb_port1_host: usb_port1_host-pins {
+					function = "usb_host_port";
+					pins = "usb_port1";
+				};
+			};
+		};
+
+		uart0: serial@10000100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000100 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		uart1: serial@10000120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000120 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_UART1>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		nflash: nand@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg = <0x10000200 0x180>,
+			      <0x10000400 0x200>,
+			      <0x10000070 0x10>;
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_NAND>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller@10000800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x10000800 0x24>;
+
+			status = "disabled";
+		};
+
+		hsspi: spi@10001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0x10001000 0x600>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_HSSPI>;
+
+			clocks = <&periph_clk BCM6328_CLK_HSSPI>,
+				 <&hsspi_osc>;
+			clock-names = "hsspi",
+				      "pll";
+
+			resets = <&periph_rst BCM6328_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		serdes_cntl: syscon@10001800 {
+			compatible = "syscon";
+			reg = <0x10001800 0x4>;
+			native-endian;
+		};
+
+		periph_pwr: power-controller@10001848 {
+			compatible = "brcm,bcm6328-power-controller";
+			reg = <0x10001848 0x4>;
+
+			#power-domain-cells = <1>;
+		};
+
+		ehci: usb@10002500 {
+			compatible = "brcm,bcm6328-ehci", "generic-ehci";
+			reg = <0x10002500 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@10002600 {
+			compatible = "brcm,bcm6328-ohci", "generic-ohci";
+			reg = <0x10002600 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@10002700 {
+			compatible = "brcm,bcm6328-usbh-phy";
+			reg = <0x10002700 0x38>;
+
+			#phy-cells = <1>;
+
+			clocks = <&periph_clk BCM6328_CLK_USBH>;
+			clock-names = "usbh";
+
+			power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>;
+			resets = <&periph_rst BCM6328_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		ethernet: ethernet@1000d800 {
+			compatible = "brcm,bcm6328-enetsw";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_ENETSW_RX_DMA0>,
+				     <BCM6328_IRQ_ENETSW_TX_DMA0>;
+			interrupt-names = "rx",
+					  "tx";
+
+			clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
+
+			resets = <&periph_rst BCM6328_RST_ENETSW>,
+				 <&periph_rst BCM6328_RST_EPHY>;
+
+			power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>,
+					<&periph_pwr BCM6328_POWER_DOMAIN_EPHY>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+		};
+
+		switch0: switch@10e00000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-switch";
+			reg = <0x10e00000 0x8000>;
+			big-endian;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					phy-mode = "internal";
+					ethernet = <&ethernet>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+
+		mdio: mdio@10e000b0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-mdio-mux";
+			reg = <0x10e000b0 0x8>;
+
+			mdio_int: mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
+
+				phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+				};
+
+				phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+				};
+
+				phy4: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <4>;
+				};
+			};
+
+			mdio_ext: mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>;
+			};
+		};
+
+		pcie: pcie@10e40000 {
+			compatible = "brcm,bcm6328-pcie";
+			reg = <0x10e40000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6328_IRQ_PCIE_RC>;
+
+			clocks = <&periph_clk BCM6328_CLK_PCIE>;
+			clock-names = "pcie";
+
+			resets = <&periph_rst BCM6328_RST_PCIE>,
+				 <&periph_rst BCM6328_RST_PCIE_EXT>,
+				 <&periph_rst BCM6328_RST_PCIE_CORE>,
+				 <&periph_rst BCM6328_RST_PCIE_HARD>;
+			reset-names = "pcie",
+				      "pcie-ext",
+				      "pcie-core",
+				      "pcie-hard";
+
+			power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_PCIE>;
+
+			brcm,serdes = <&serdes_cntl>;
+
+			status = "disabled";
+		};
+	};
+};

target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts

@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6358.dtsi"
+
+/ {
+	model = "Huawei EchoLife HG556a (version B)";
+	compatible = "huawei,hg556a-b", "brcm,bcm6358";
+
+	aliases {
+		led-boot = &led_power_red;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_red;
+		led-upgrade = &led_power_red;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		help {
+			label = "help";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_HELP>;
+			debounce-interval = <60>;
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+
+		restart {
+			label = "restart";
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_CONFIG>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@0 {
+			label = "red:message";
+			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "red:hspa";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		led@2 {
+			label = "red:dsl";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@3 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		led@6 {
+			label = "all";
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		led@12 {
+			label = "green:lan1";
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+
+		led@13 {
+			label = "red:lan1";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		led@15 {
+			label = "green:lan2";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		};
+
+		led@22 {
+			label = "red:lan2";
+			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+		};
+
+		led@23 {
+			label = "green:lan3";
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+		};
+
+		led@26 {
+			label = "red:lan3";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+		};
+
+		led@27 {
+			label = "green:lan4";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+		};
+
+		led@28 {
+			label = "red:lan4";
+			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	ath9k-leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&ath9k 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet1 {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+
+	phy-mode = "mii";
+
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
+&iudma {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+
+	ath9k: wifi@1,0 {
+		compatible = "pci168c,0029";
+		reg = <0x0800 0 0 0 0>;
+
+		qca,no-eeprom;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "cfe";
+			reg = <0x000000 0x020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			label = "firmware";
+			reg = <0x020000 0xec0000>;
+			compatible = "brcm,bcm963xx-imagetag";
+		};
+
+		cal_data: partition@ee0000 {
+			label = "cal_data";
+			reg = <0xee0000 0x100000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cal_data_1e000: cal@1e000 {
+					reg = <0x1e000 0xeb8>;
+				};
+			};
+		};
+
+		partition@fe0000 {
+			label = "nvram";
+			reg = <0xfe0000 0x020000>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6358.dtsi

@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm6358-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm6358-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm6358-reset.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm6358";
+
+	aliases {
+		pflash = &pflash;
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &lsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-cbr-reg = <0xff400000>;
+		mips-hpt-frequency = <150000000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	pflash: nor@1e000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x1e000000 0x2000000>;
+		bank-width = <2>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@fffe0004 {
+			compatible = "brcm,bcm6358-clocks";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		pll_cntl: syscon@fffe0008 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0xfffe0008 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0x0>;
+				mask = <0x1>;
+			};
+		};
+
+		periph_intc: interrupt-controller@fffe000c {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0xfffe000c 0x8>,
+			      <0xfffe0038 0x8>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		ext_intc0: interrupt-controller@fffe0014 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0xfffe0014 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_EXT0>,
+				     <BCM6358_IRQ_EXT1>,
+				     <BCM6358_IRQ_EXT2>,
+				     <BCM6358_IRQ_EXT3>;
+		};
+
+		ext_intc1: interrupt-controller@fffe001c {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0xfffe001c 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_EXT4>,
+				     <BCM6358_IRQ_EXT5>;
+		};
+
+		periph_rst: reset-controller@fffe0034 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0034 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog@fffe005c {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0xfffe005c 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		gpio_cntl: syscon@fffe0080 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6358-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0xfffe0080 0x50>;
+			ranges = <0 0xfffe0080 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm6358-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 40>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@18 {
+				compatible = "brcm,bcm6358-pinctrl";
+				reg = <0x18 0x4>;
+
+				pinctrl_ebi_cs: ebi_cs-pins {
+					function = "ebi_cs";
+					groups = "ebi_cs_grp";
+				};
+
+				pinctrl_uart1: uart1-pins {
+					function = "uart1";
+					groups = "uart1_grp";
+				};
+
+				pinctrl_serial_led: serial_led-pins {
+					function = "serial_led";
+					groups = "serial_led_grp";
+				};
+
+				pinctrl_legacy_led: legacy_led-pins {
+					function = "legacy_led";
+					groups = "legacy_led_grp";
+				};
+
+				pinctrl_led: led-pins {
+					function = "led";
+					groups = "led_grp";
+				};
+
+				pinctrl_spi_cs_23: spi_cs-pins {
+					function = "spi_cs";
+					groups = "spi_cs_grp";
+				};
+
+				pinctrl_utopia: utopia-pins {
+					function = "utopia";
+					groups = "utopia_grp";
+				};
+
+				pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
+					function = "pwm_syn_clk";
+					groups = "pwm_syn_clk_grp";
+				};
+
+				pinctrl_sys_irq: sys_irq-pins {
+					function = "sys_irq";
+					groups = "sys_irq_grp";
+				};
+			};
+		};
+
+		leds: led-controller@fffe00d0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-leds";
+			reg = <0xfffe00d0 0x8>;
+
+			status = "disabled";
+		};
+
+		uart0: serial@fffe0100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0100 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		uart1: serial@fffe0120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0120 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_UART1>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		lsspi: spi@fffe0800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-spi";
+			reg = <0xfffe0800 0x70c>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_SPI>;
+
+			clocks = <&periph_clk BCM6358_CLK_SPI>;
+			clock-names = "spi";
+
+			resets = <&periph_rst BCM6358_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		pci: pci@fffe1000 {
+			compatible = "brcm,bcm6348-pci";
+			reg = <0xfffe1000 0x200>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
+				 <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_MPI>;
+
+			resets = <&periph_rst BCM6358_RST_MPI>;
+			reset-names = "pci";
+
+			brcm,remap;
+
+			status = "disabled";
+		};
+
+		ehci: usb@fffe1300 {
+			compatible = "brcm,bcm6358-ehci", "generic-ehci";
+			reg = <0xfffe1300 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@fffe1400 {
+			compatible = "brcm,bcm6358-ohci", "generic-ohci";
+			reg = <0xfffe1400 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@fffe1500 {
+			compatible = "brcm,bcm6358-usbh-phy";
+			reg = <0xfffe1500 0x38>;
+
+			#phy-cells = <1>;
+
+			resets = <&periph_rst BCM6358_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		ethernet0: ethernet@fffe4000 {
+			compatible = "brcm,bcm6358-emac";
+			reg = <0xfffe4000 0x2dc>;
+
+			clocks = <&periph_clk BCM6358_CLK_ENET0>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_EMAC0>,
+					<BCM6358_IRQ_EMAC0_RX_DMA>,
+					<BCM6358_IRQ_EMAC0_TX_DMA>;
+			interrupt-names = "emac",
+					  "rx",
+					  "tx";
+
+			brcm,iudma = <&iudma>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+
+			mdio0: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		ethernet1: ethernet@fffe4800 {
+			compatible = "brcm,bcm6358-emac";
+			reg = <0xfffe4800 0x2dc>;
+
+			clocks = <&periph_clk BCM6358_CLK_ENET1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6358_IRQ_EMAC1>,
+				     <BCM6358_IRQ_EMAC1_RX_DMA>,
+				     <BCM6358_IRQ_EMAC1_TX_DMA>;
+			interrupt-names = "emac",
+					  "rx",
+					  "tx";
+
+			brcm,iudma = <&iudma>;
+			brcm,external-mii;
+
+			dma-rx = <2>;
+			dma-tx = <3>;
+
+			status = "disabled";
+
+			mdio1: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		iudma: dma@fffe5000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6358-iudma";
+			reg = <0xfffe5000 0x24>,
+			      <0xfffe5100 0x80>,
+			      <0xfffe5200 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			dma-channels = <8>;
+
+			clocks = <&periph_clk BCM6358_CLK_EMUSB>,
+				 <&periph_clk BCM6358_CLK_USBSU>,
+				 <&periph_clk BCM6358_CLK_EPHY>,
+				 <&periph_clk BCM6358_CLK_ENET>;
+
+			resets = <&periph_rst BCM6358_RST_ENET>,
+				 <&periph_rst BCM6358_RST_EPHY>;
+
+			status = "disabled";
+		};
+	};
+};

target/linux/bmips/dts/bcm6362-huawei-hg253s-v2.dts

@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6362.dtsi"
+
+/ {
+	model = "Huawei HG253s v2";
+	compatible = "huawei,hg253s-v2", "brcm,bcm6362";
+
+	aliases {
+		led-boot = &led_phone_green;
+		led-failsafe = &led_phone_green;
+		led-upgrade = &led_phone_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_phone_green: led@28 {
+			label = "green:phone";
+			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+		};
+
+		led@30 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds>;
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led@5 {
+		reg = <5>;
+		active-low;
+		label = "green:wifi";
+	};
+};
+
+&lsspi {
+	status = "okay";
+
+	switch@0 {
+		compatible = "brcm,bcm53125";
+		reg = <0>;
+		spi-max-frequency = <781000>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					asym-pause;
+					pause;
+				};
+			};
+		};
+	};
+};
+
+&mdio_ext {
+	phy24: ethernet-phy@18 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <24>;
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0020000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@20000 {
+				compatible = "brcm,wfi";
+				label = "wfi";
+				reg = <0x0020000 0x7d80000>;
+			};
+
+			partition@7da0000 {
+				label = "nvram";
+				reg = <0x7da0000 0x160000>;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio3", "gpio5";
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		port@5 {
+			reg = <5>;
+			label = "wan";
+
+			phy-handle = <&phy24>;
+			phy-mode = "rgmii-txid";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts

@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6362.dtsi"
+
+/ {
+	model = "Netgear DGND3700 v2";
+	compatible = "netgear,dgnd3700-v2", "brcm,bcm6362";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@28 {
+			label = "green:dsl";
+			gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@34 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			panic-indicator;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cferom_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&leds {
+	status = "okay";
+
+	brcm,serial-leds;
+	brcm,serial-dat-low;
+	brcm,serial-shift-inv;
+	brcm,serial-mux;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_leds &pinctrl_serial_led>;
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		label = "green:internet";
+	};
+
+	led_power_green: led@8 {
+		reg = <8>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@9 {
+		reg = <9>;
+		active-low;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@10 {
+		reg = <10>;
+		active-low;
+		label = "green:usb1";
+	};
+
+	led@11 {
+		reg = <11>;
+		active-low;
+		label = "green:usb2";
+	};
+
+	led@12 {
+		reg = <12>;
+		active-low;
+		label = "amber:internet";
+	};
+
+	led@13 {
+		reg = <13>;
+		active-low;
+		label = "green:ethernet";
+	};
+
+	led@14 {
+		reg = <14>;
+		active-low;
+		label = "amber:dsl";
+	};
+
+	led@16 {
+		reg = <16>;
+		active-low;
+		label = "amber:usb1";
+	};
+
+	led@17 {
+		reg = <17>;
+		active-low;
+		label = "amber:usb2";
+	};
+
+	led@18 {
+		reg = <18>;
+		active-low;
+		label = "amber:ethernet";
+	};
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53125";
+		reg = <30>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan1";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan2";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan4";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "wan";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "cferom";
+				reg = <0x0000000 0x0004000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_cferom_6a0: macaddr@6a0 {
+						reg = <0x6a0 0x6>;
+					};
+				};
+			};
+
+			partition@4000 {
+				compatible = "brcm,wfi";
+				label = "wfi";
+				reg = <0x0004000 0x1c7c000>;
+				brcm,cferam = "cfe";
+			};
+
+			partition@1c80000 {
+				label = "flag";
+				reg = <0x1c80000 0x0040000>;
+				read-only;
+			};
+
+			partition@1cc0000 {
+				label = "pcbasn";
+				reg = <0x1cc0000 0x0040000>;
+				read-only;
+			};
+
+			partition@1d00000 {
+				label = "xxx";
+				reg = <0x1d00000 0x0080000>;
+				read-only;
+			};
+
+			partition@1d80000 {
+				label = "language_dev";
+				reg = <0x1d80000 0x0040000>;
+				read-only;
+			};
+
+			partition@1dc0000 {
+				label = "scnvram";
+				reg = <0x1dc0000 0x0100000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_leds: leds {
+		function = "led";
+		pins = "gpio1";
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6362.dtsi

@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm6362-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm6362-reset.h>
+#include <dt-bindings/soc/bcm6362-pm.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm6362";
+
+	aliases {
+		nflash = &nflash;
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &lsspi;
+		spi1 = &hsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+
+		hsspi_osc: hsspi-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <400000000>;
+			clock-output-names = "hsspi_osc";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-hpt-frequency = <200000000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@10000004 {
+			compatible = "brcm,bcm6362-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		pll_cntl: syscon@10000008 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10000008 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0x0>;
+				mask = <0x1>;
+			};
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		ext_intc: interrupt-controller@10000018 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0x10000018 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_EXT0>,
+				     <BCM6362_IRQ_EXT1>,
+				     <BCM6362_IRQ_EXT2>,
+				     <BCM6362_IRQ_EXT3>;
+		};
+
+		periph_intc: interrupt-controller@10000020 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0x10000020 0x10>,
+			      <0x10000030 0x10>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		wdt: watchdog@1000005c {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0x1000005c 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		gpio_cntl: syscon@10000080 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6362-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0x10000080 0x80>;
+			ranges = <0 0x10000080 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm6362-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 48>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@18 {
+				compatible = "brcm,bcm6362-pinctrl";
+				reg = <0x18 0x10>, <0x38 0x4>;
+
+				pinctrl_usb_device_led: usb_device_led-pins {
+					function = "usb_device_led";
+					pins = "gpio0";
+				};
+
+				pinctrl_sys_irq: sys_irq-pins {
+					function = "sys_irq";
+					pins = "gpio1";
+				};
+
+				pinctrl_serial_led: serial_led-pins {
+					pinctrl_serial_led_clk: serial_led_clk-pins {
+						function = "serial_led_clk";
+						pins = "gpio2";
+					};
+
+					pinctrl_serial_led_data: serial_led_data-pins {
+						function = "serial_led_data";
+						pins = "gpio3";
+					};
+				};
+
+				pinctrl_robosw_led_data: robosw_led_data-pins {
+					function = "robosw_led_data";
+					pins = "gpio4";
+				};
+
+				pinctrl_robosw_led_clk: robosw_led_clk-pins {
+					function = "robosw_led_clk";
+					pins = "gpio5";
+				};
+
+				pinctrl_robosw_led0: robosw_led0-pins {
+					function = "robosw_led0";
+					pins = "gpio6";
+				};
+
+				pinctrl_robosw_led1: robosw_led1-pins {
+					function = "robosw_led1";
+					pins = "gpio7";
+				};
+
+				pinctrl_inet_led: inet_led-pins {
+					function = "inet_led";
+					pins = "gpio8";
+				};
+
+				pinctrl_spi_cs2: spi_cs2-pins {
+					function = "spi_cs2";
+					pins = "gpio9";
+				};
+
+				pinctrl_spi_cs3: spi_cs3-pins {
+					function = "spi_cs3";
+					pins = "gpio10";
+				};
+
+				pinctrl_ntr_pulse: ntr_pulse-pins {
+					function = "ntr_pulse";
+					pins = "gpio11";
+				};
+
+				pinctrl_uart1_scts: uart1_scts-pins {
+					function = "uart1_scts";
+					pins = "gpio12";
+				};
+
+				pinctrl_uart1_srts: uart1_srts-pins {
+					function = "uart1_srts";
+					pins = "gpio13";
+				};
+
+				pinctrl_uart1: uart1-pins {
+					pinctrl_uart1_sdin: uart1_sdin-pins {
+						function = "uart1_sdin";
+						pins = "gpio14";
+					};
+
+					pinctrl_uart1_sdout: uart1_sdout-pins {
+						function = "uart1_sdout";
+						pins = "gpio15";
+					};
+				};
+
+				pinctrl_adsl_spi: adsl_spi-pins {
+					pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
+						function = "adsl_spi_miso";
+						pins = "gpio16";
+					};
+
+					pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
+						function = "adsl_spi_mosi";
+						pins = "gpio17";
+					};
+
+					pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
+						function = "adsl_spi_clk";
+						pins = "gpio18";
+					};
+
+					pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
+						function = "adsl_spi_cs";
+						pins = "gpio19";
+					};
+				};
+
+				pinctrl_ephy0_led: ephy0_led-pins {
+					function = "ephy0_led";
+					pins = "gpio20";
+				};
+
+				pinctrl_ephy1_led: ephy1_led-pins {
+					function = "ephy1_led";
+					pins = "gpio21";
+				};
+
+				pinctrl_ephy2_led: ephy2_led-pins {
+					function = "ephy2_led";
+					pins = "gpio22";
+				};
+
+				pinctrl_ephy3_led: ephy3_led-pins {
+					function = "ephy3_led";
+					pins = "gpio23";
+				};
+
+				pinctrl_ext_irq0: ext_irq0-pins {
+					function = "ext_irq0";
+					pins = "gpio24";
+				};
+
+				pinctrl_ext_irq1: ext_irq1-pins {
+					function = "ext_irq1";
+					pins = "gpio25";
+				};
+
+				pinctrl_ext_irq2: ext_irq2-pins {
+					function = "ext_irq2";
+					pins = "gpio26";
+				};
+
+				pinctrl_ext_irq3: ext_irq3-pins {
+					function = "ext_irq3";
+					pins = "gpio27";
+				};
+
+				pinctrl_nand: nand-pins {
+					function = "nand";
+					group = "nand_grp";
+				};
+			};
+		};
+
+		uart0: serial@10000100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000100 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		uart1: serial@10000120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000120 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_UART1>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		nflash: nand@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x10000070 0x10>;
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_NAND>;
+
+			clocks = <&periph_clk BCM6362_CLK_NAND>;
+			clock-names = "nand";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+
+			status = "disabled";
+		};
+
+		lsspi: spi@10000800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-spi";
+			reg = <0x10000800 0x70c>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_LSSPI>;
+
+			clocks = <&periph_clk BCM6362_CLK_SPI>;
+			clock-names = "spi";
+
+			resets = <&periph_rst BCM6362_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		hsspi: spi@10001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0x10001000 0x600>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_HSSPI>;
+
+			clocks = <&periph_clk BCM6362_CLK_HSSPI>,
+				 <&hsspi_osc>;
+			clock-names = "hsspi",
+				      "pll";
+
+			resets = <&periph_rst BCM6362_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		serdes_cntl: syscon@10001804 {
+			compatible = "syscon";
+			reg = <0x10001804 0x4>;
+			native-endian;
+		};
+
+		periph_pwr: power-controller@10001848 {
+			compatible = "brcm,bcm6362-power-controller";
+			reg = <0x10001848 0x4>;
+			#power-domain-cells = <1>;
+		};
+
+		leds: led-controller@10001900 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x10001900 0x24>;
+
+			status = "disabled";
+		};
+
+		ehci: usb@10002500 {
+			compatible = "brcm,bcm6362-ehci", "generic-ehci";
+			reg = <0x10002500 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@10002600 {
+			compatible = "brcm,bcm6362-ohci", "generic-ohci";
+			reg = <0x10002600 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@10002700 {
+			compatible = "brcm,bcm6362-usbh-phy";
+			reg = <0x10002700 0x38>;
+
+			#phy-cells = <1>;
+
+			clocks = <&periph_clk BCM6362_CLK_USBH>;
+			clock-names = "usbh";
+
+			power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
+			resets = <&periph_rst BCM6362_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		random: rng@10002880 {
+			compatible = "brcm,bcm6368-rng";
+			reg = <0x10002880 0x14>;
+
+			clocks = <&periph_clk BCM6362_CLK_IPSEC>;
+			clock-names = "ipsec";
+
+			resets = <&periph_rst BCM6362_RST_IPSEC>;
+
+			power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_IPSEC>;
+		};
+
+		ethernet: ethernet@1000d800 {
+			compatible = "brcm,bcm6362-enetsw";
+			reg = <0x1000d800 0x80>,
+			      <0x1000da00 0x80>,
+			      <0x1000dc00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;
+			interrupt-names = "rx";
+
+			clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
+				 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
+				 <&periph_clk BCM6362_CLK_ROBOSW>;
+
+			resets = <&periph_rst BCM6362_RST_ENETSW>,
+				 <&periph_rst BCM6362_RST_EPHY>;
+
+			power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,
+					<&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+		};
+
+		switch0: switch@10e00000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6362-switch";
+			reg = <0x10e00000 0x8000>;
+			big-endian;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					phy-mode = "internal";
+					ethernet = <&ethernet>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+
+		mdio: mdio@10e000b0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-mdio-mux";
+			reg = <0x10e000b0 0x8>;
+
+			mdio_int: mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
+
+				phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+				};
+
+				phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+				};
+
+				phy4: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <4>;
+				};
+			};
+
+			mdio_ext: mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>;
+			};
+		};
+
+		pcie: pcie@10e40000 {
+			compatible = "brcm,bcm6328-pcie";
+			reg = <0x10e40000 0x10000>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6362_IRQ_PCIE_RC>;
+
+			clocks = <&periph_clk BCM6362_CLK_PCIE>;
+			clock-names = "pcie";
+
+			resets = <&periph_rst BCM6362_RST_PCIE>,
+				 <&periph_rst BCM6362_RST_PCIE_EXT>,
+				 <&periph_rst BCM6362_RST_PCIE_CORE>;
+			reset-names = "pcie",
+				      "pcie-ext",
+				      "pcie-core";
+
+			power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
+
+			brcm,serdes = <&serdes_cntl>;
+
+			status = "disabled";
+		};
+	};
+};

target/linux/bmips/dts/bcm6368-actiontec-r1000h.dts

@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Actiontec R1000H";
+	compatible = "actiontec,r1000h", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@5 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@21 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_green: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@23 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		led@30 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
+		};
+
+		led@31 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53115";
+		reg = <30>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan1";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan2";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan4";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "wan";
+			};
+
+			port@5 {
+				/* HPNA coaxial port */
+				reg = <5>;
+				label = "coax";
+
+				phy-mode = "mii";
+
+				fixed-link {
+					speed = <100>;
+					full-duplex;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port5: port@5 {
+			reg = <5>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x000000 0x020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					reg = <0x6a0 0x6>;
+				};
+			};
+		};
+
+		partition@20000 {
+			label = "firmware";
+			reg = <0x020000 0x1fc0000>;
+			compatible = "brcm,bcm963xx-imagetag";
+		};
+
+		partition@fe0000 {
+			label = "nvram";
+			reg = <0x1fe0000 0x020000>;
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts

@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Comtrend VR-3025u";
+	compatible = "comtrend,vr-3025u", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "green:dsl";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@5 {
+			label = "green:internet";
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_power_green: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_power_red: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		led@31 {
+			label = "red:internet";
+			gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	bcm43222-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <1>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43222-sprom.bin";
+		brcm,sprom-fixups = <97 0xfeb3>,
+				    <98 0x1618>,
+				    <99 0xfab0>,
+				    <113 0xfed1>,
+				    <114 0x1609>,
+				    <115 0xfad9>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x0000000 0x0020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			compatible = "brcm,bcm963xx-imagetag";
+			label = "firmware";
+			reg = <0x0020000 0x1fc0000>;
+		};
+
+		partition@1fe0000 {
+			label = "nvram";
+			reg = <0x1fe0000 0x020000>;
+		};
+	};
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ephy0_led &pinctrl_ephy1_led
+		     &pinctrl_ephy2_led &pinctrl_ephy3_led>;
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6368-comtrend-vr-3025un.dts

@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Comtrend VR-3025un";
+	compatible = "comtrend,vr-3025un", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "green:dsl";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@5 {
+			label = "green:internet";
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_power_green: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_power_red: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		led@31 {
+			label = "red:internet";
+			gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	bcm43222-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <1>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43222-sprom.bin";
+		brcm,sprom-fixups = <97 0xfeb3>,
+				    <98 0x1618>,
+				    <99 0xfab0>,
+				    <113 0xfed1>,
+				    <114 0x1609>,
+				    <115 0xfad9>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x000000 0x010000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			compatible = "brcm,bcm963xx-imagetag";
+			label = "firmware";
+			reg = <0x010000 0x7e0000>;
+		};
+
+		partition@1fe0000 {
+			label = "nvram";
+			reg = <0x7f0000 0x010000>;
+		};
+	};
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ephy0_led &pinctrl_ephy1_led
+		     &pinctrl_ephy2_led &pinctrl_ephy3_led>;
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "iptv";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6368-netgear-dgnd3700-v1.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368-netgear-dgnd3700.dtsi"
+
+/ {
+	model = "Netgear DGND3700 v1";
+	compatible = "netgear,dgnd3700-v1", "brcm,bcm6368";
+};

target/linux/bmips/dts/bcm6368-netgear-dgnd3700.dtsi

@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <dt-bindings/leds/common.h>
+
+#include "bcm6368.dtsi"
+
+/ {
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		rfkill {
+			label = "rfkill";
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "green:dsl";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@4 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		led@5 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		led@11 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led@13 {
+			/* Front USB port */
+			label = "green:usb2";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		led@14 {
+			/* Back USB port */
+			label = "green:usb1";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+			panic-indicator;
+		};
+
+		led@23 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_green: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+		};
+
+		led@26 {
+			label = "green:wifi2g";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+		};
+
+		led@27 {
+			label = "blue:wifi5g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&lsspi {
+	status = "okay";
+
+	switch@1 {
+		compatible = "brcm,bcm53115";
+		reg = <1>;
+		spi-max-frequency = <781000>;
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "wan";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&nflash {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-step-size = <512>;
+		nand-ecc-strength = <15>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "storage";
+				reg = <0 0>; /* autodetected size */
+			};
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x0000000 0x0020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					reg = <0x6a0 0x6>;
+				};
+			};
+		};
+
+		partition@20000 {
+			compatible = "brcm,bcm963xx-imagetag";
+			label = "firmware";
+			reg = <0x0020000 0x1e20000>;
+		};
+
+		partition@1e40000 {
+			label = "board_data";
+			reg = <0x1e40000 0x1a0000>;
+			read-only;
+		};
+
+		partition@1fe0000 {
+			label = "nvram";
+			reg = <0x1fe0000 0x020000>;
+		};
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port5: port@5 {
+			reg = <5>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6368-netgear-dgnd3800b.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368-netgear-dgnd3700.dtsi"
+
+/ {
+	model = "Netgear DGND3800B";
+	compatible = "netgear,dgnd3800b", "brcm,bcm6368";
+};

target/linux/bmips/dts/bcm6368-observa-vh4032n.dts

@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Observa VH4032N";
+	compatible = "observa,vh4032n", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_blue;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_blue;
+		led-upgrade = &led_power_blue;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		rfkill {
+			label = "rfkill";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "blue:dsl";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@5 {
+			label = "red:dsl";
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		led@11 {
+			label = "blue:hspa";
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led@12 {
+			label = "red:hspa";
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_blue: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_power_red: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		led@25 {
+			label = "blue:voice";
+			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+		};
+
+		led@26 {
+			label = "red:voice";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	bcm43222-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <1>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm43222-sprom.bin";
+		brcm,sprom-fixups = <2   0x04d2>, <4   0x4350>,
+				    <65  0x1300>, <68  0x0402>,
+				    <70  0x0090>, <71  0x4c19>,
+				    <72  0x2345>, <87  0x0315>,
+				    <88  0x0315>, <96  0x2048>,
+				    <97  0xfed7>, <98  0x15a6>,
+				    <99  0xfaee>, <100 0x3e3a>,
+				    <101 0x3a36>, <102 0xff7f>,
+				    <103 0x11b9>, <104 0xfc53>,
+				    <105 0xffe6>, <106 0xfdd2>,
+				    <107 0xfe49>, <108 0xff6a>,
+				    <109 0x136e>, <110 0xfbed>,
+				    <111 0x0000>, <112 0x2048>,
+				    <113 0xfee2>, <114 0x15e5>,
+				    <115 0xfaed>, <116 0x3e3a>,
+				    <117 0x3a36>, <118 0xffc8>,
+				    <119 0x12b8>, <120 0xfca1>,
+				    <121 0xff9b>, <122 0x122a>,
+				    <123 0xfcc8>, <124 0xff95>,
+				    <125 0x146b>, <126 0xfbba>,
+				    <127 0x0000>, <161 0x0000>,
+				    <162 0x0000>, <169 0x0000>,
+				    <170 0x0000>, <171 0x0000>,
+				    <172 0x0000>, <173 0x0000>,
+				    <174 0x0000>, <175 0x0000>,
+				    <176 0x0000>, <219 0x1108>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gpio {
+	usb_hub_reset {
+		gpio-hog;
+		gpios = <27 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb-hub-reset-gpio";
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x0000000 0x0020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			compatible = "brcm,bcm963xx-imagetag";
+			label = "firmware";
+			reg = <0x0020000 0x1fc0000>;
+		};
+
+		partition@1fe0000 {
+			label = "nvram";
+			reg = <0x1fe0000 0x020000>;
+		};
+	};
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ephy0_led &pinctrl_ephy1_led
+		     &pinctrl_ephy2_led &pinctrl_ephy3_led>;
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "lan4";
+
+			phy-handle = <&phy1>;
+			phy-mode = "mii";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan3";
+
+			phy-handle = <&phy2>;
+			phy-mode = "mii";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+
+			phy-handle = <&phy3>;
+			phy-mode = "mii";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan1";
+
+			phy-handle = <&phy4>;
+			phy-mode = "mii";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6368.dtsi

@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include <dt-bindings/clock/bcm6368-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/reset/bcm6368-reset.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "brcm,bcm6368";
+
+	aliases {
+		nflash = &nflash;
+		pflash = &pflash;
+		pinctrl = &pinctrl;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &lsspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+
+			#clock-cells = <0>;
+
+			clock-frequency = <50000000>;
+			clock-output-names = "periph";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mips-cbr-reg = <0xff400000>;
+		mips-hpt-frequency = <200000000>;
+
+		cpu@0 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bmips4350", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		#address-cells = <0>;
+		compatible = "mti,cpu-interrupt-controller";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0>;
+	};
+
+	ubus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		compatible = "simple-bus";
+		ranges;
+
+		periph_clk: clock-controller@10000004 {
+			compatible = "brcm,bcm6368-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		pll_cntl: syscon@10000008 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10000008 0x4>;
+			native-endian;
+
+			syscon-reboot {
+				compatible = "syscon-reboot";
+				offset = <0x0>;
+				mask = <0x1>;
+			};
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		ext_intc0: interrupt-controller@10000018 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0x10000018 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_EXT0>,
+				     <BCM6368_IRQ_EXT1>,
+				     <BCM6368_IRQ_EXT2>,
+				     <BCM6368_IRQ_EXT3>;
+		};
+
+		ext_intc1: interrupt-controller@1000001c {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-ext-intc";
+			reg = <0x1000001c 0x4>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_EXT4>,
+				     <BCM6368_IRQ_EXT5>;
+		};
+
+		periph_intc: interrupt-controller@10000020 {
+			#address-cells = <1>;
+			compatible = "brcm,bcm6345-l1-intc";
+			reg = <0x10000020 0x10>,
+			      <0x10000030 0x10>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpu_intc>;
+			interrupts = <2>, <3>;
+		};
+
+		wdt: watchdog@1000005c {
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0x1000005c 0xc>;
+
+			clocks = <&periph_osc>;
+
+			timeout-sec = <30>;
+		};
+
+		gpio_cntl: syscon@10000080 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "brcm,bcm6368-gpio-sysctl",
+				     "syscon", "simple-mfd";
+			reg = <0x10000080 0x80>;
+			ranges = <0 0x10000080 0x80>;
+			native-endian;
+
+			gpio: gpio@0 {
+				compatible = "brcm,bcm6368-gpio";
+				reg-names = "dirout", "dat";
+				reg = <0x0 0x8>, <0x8 0x8>;
+
+				gpio-controller;
+				gpio-ranges = <&pinctrl 0 0 38>;
+				#gpio-cells = <2>;
+			};
+
+			pinctrl: pinctrl@18 {
+				compatible = "brcm,bcm6368-pinctrl";
+				reg = <0x18 0x4>, <0x38 0x4>;
+
+				pinctrl_analog_afe_0: analog_afe_0-pins {
+					function = "analog_afe_0";
+					pins = "gpio0";
+				};
+
+				pinctrl_analog_afe_1: analog_afe_1-pins {
+					function = "analog_afe_1";
+					pins = "gpio1";
+				};
+
+				pinctrl_sys_irq: sys_irq-pins {
+					function = "sys_irq";
+					pins = "gpio2";
+				};
+
+				pinctrl_serial_led: serial_led-pins {
+					pinctrl_serial_led_data: serial_led_data-pins {
+						function = "serial_led_data";
+						pins = "gpio3";
+					};
+
+					pinctrl_serial_led_clk: serial_led_clk-pins {
+						function = "serial_led_clk";
+						pins = "gpio4";
+					};
+				};
+
+				pinctrl_inet_led: inet_led-pins {
+					function = "inet_led";
+					pins = "gpio5";
+				};
+
+				pinctrl_ephy0_led: ephy0_led-pins {
+					function = "ephy0_led";
+					pins = "gpio6";
+				};
+
+				pinctrl_ephy1_led: ephy1_led-pins {
+					function = "ephy1_led";
+					pins = "gpio7";
+				};
+
+				pinctrl_ephy2_led: ephy2_led-pins {
+					function = "ephy2_led";
+					pins = "gpio8";
+				};
+
+				pinctrl_ephy3_led: ephy3_led-pins {
+					function = "ephy3_led";
+					pins = "gpio9";
+				};
+
+				pinctrl_robosw_led_data: robosw_led_data-pins {
+					function = "robosw_led_data";
+					pins = "gpio10";
+				};
+
+				pinctrl_robosw_led_clk: robosw_led_clk-pins {
+					function = "robosw_led_clk";
+					pins = "gpio11";
+				};
+
+				pinctrl_robosw_led0: robosw_led0-pins {
+					function = "robosw_led0";
+					pins = "gpio12";
+				};
+
+				pinctrl_robosw_led1: robosw_led1-pins {
+					function = "robosw_led1";
+					pins = "gpio13";
+				};
+
+				pinctrl_usb_device_led: usb_device_led-pins {
+					function = "usb_device_led";
+					pins = "gpio14";
+				};
+
+				pinctrl_pci: pci-pins {
+					pinctrl_pci_req1: pci_req1-pins {
+						function = "pci_req1";
+						pins = "gpio16";
+					};
+
+					pinctrl_pci_gnt1: pci_gnt1-pins {
+						function = "pci_gnt1";
+						pins = "gpio17";
+					};
+
+					pinctrl_pci_intb: pci_intb-pins {
+						function = "pci_intb";
+						pins = "gpio18";
+					};
+
+					pinctrl_pci_req0: pci_req0-pins {
+						function = "pci_req0";
+						pins = "gpio19";
+					};
+
+					pinctrl_pci_gnt0: pci_gnt0-pins {
+						function = "pci_gnt0";
+						pins = "gpio20";
+					};
+				};
+
+				pinctrl_pcmcia: pcmcia-pins {
+					pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
+						function = "pcmcia_cd1";
+						pins = "gpio22";
+					};
+
+					pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
+						function = "pcmcia_cd2";
+						pins = "gpio23";
+					};
+
+					pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
+						function = "pcmcia_vs1";
+						pins = "gpio24";
+					};
+
+					pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
+						function = "pcmcia_vs2";
+						pins = "gpio25";
+					};
+				};
+
+				pinctrl_ebi_cs2: ebi_cs2-pins {
+					function = "ebi_cs2";
+					pins = "gpio26";
+				};
+
+				pinctrl_ebi_cs3: ebi_cs3-pins {
+					function = "ebi_cs3";
+					pins = "gpio27";
+				};
+
+				pinctrl_spi_cs2: spi_cs2-pins {
+					function = "spi_cs2";
+					pins = "gpio28";
+				};
+
+				pinctrl_spi_cs3: spi_cs3-pins {
+					function = "spi_cs3";
+					pins = "gpio29";
+				};
+
+				pinctrl_spi_cs4: spi_cs4-pins {
+					function = "spi_cs4";
+					pins = "gpio30";
+				};
+
+				pinctrl_spi_cs5: spi_cs5-pins {
+					function = "spi_cs5";
+					pins = "gpio31";
+				};
+
+				pinctrl_uart1: uart1-pins {
+					function = "uart1";
+					group = "uart1_grp";
+				};
+			};
+		};
+
+		leds: led-controller@100000d0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-leds";
+			reg = <0x100000d0 0x8>;
+
+			status = "disabled";
+		};
+
+		uart0: serial@10000100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000100 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_UART0>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		uart1: serial@10000120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000120 0x18>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_UART1>;
+
+			clocks = <&periph_osc>;
+			clock-names = "periph";
+
+			status = "disabled";
+		};
+
+		nflash: nand@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.1",
+				     "brcm,brcmnand";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x10000070 0x10>;
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_NAND>;
+
+			clocks = <&periph_clk BCM6368_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
+		lsspi: spi@10000800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6358-spi";
+			reg = <0x10000800 0x70c>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_SPI>;
+
+			clocks = <&periph_clk BCM6368_CLK_SPI>;
+			clock-names = "spi";
+
+			resets = <&periph_rst BCM6368_RST_SPI>;
+
+			status = "disabled";
+		};
+
+		pci: pci@10001000 {
+			compatible = "brcm,bcm6348-pci";
+			reg = <0x10001000 0x200>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			device_type = "pci";
+			bus-range = <0x00 0x01>;
+			ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
+				 <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
+			linux,pci-probe-only = <1>;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_MPI>;
+
+			resets = <&periph_rst BCM6368_RST_MPI>;
+			reset-names = "pci";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pci>;
+
+			brcm,remap;
+
+			status = "disabled";
+		};
+
+		ehci: usb@10001500 {
+			compatible = "brcm,bcm6368-ehci", "generic-ehci";
+			reg = <0x10001500 0x100>;
+			big-endian;
+			spurious-oc;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_EHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		ohci: usb@10001600 {
+			compatible = "brcm,bcm6368-ohci", "generic-ohci";
+			reg = <0x10001600 0x100>;
+			big-endian;
+			no-big-frame-no;
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_OHCI>;
+
+			phys = <&usbh 0>;
+			phy-names = "usb";
+
+			status = "disabled";
+		};
+
+		usbh: usb-phy@10001700 {
+			compatible = "brcm,bcm6368-usbh-phy";
+			reg = <0x10001700 0x38>;
+
+			#phy-cells = <1>;
+
+			clocks = <&periph_clk BCM6368_CLK_USBH>;
+			clock-names = "usbh";
+
+			resets = <&periph_rst BCM6368_RST_USBH>;
+
+			status = "disabled";
+		};
+
+		random: rng@10004180 {
+			compatible = "brcm,bcm6368-rng";
+			reg = <0x10004180 0x14>;
+
+			clocks = <&periph_clk BCM6368_CLK_IPSEC>;
+			clock-names = "ipsec";
+
+			resets = <&periph_rst BCM6368_RST_IPSEC>;
+		};
+
+		ethernet: ethernet@10006800 {
+			compatible = "brcm,bcm6368-enetsw";
+			reg = <0x10006800 0x80>,
+			      <0x10006a00 0x80>,
+			      <0x10006c00 0x80>;
+			reg-names = "dma",
+				    "dma-channels",
+				    "dma-sram";
+
+			interrupt-parent = <&periph_intc>;
+			interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
+				     <BCM6368_IRQ_ENETSW_TX_DMA0>;
+			interrupt-names = "rx",
+					  "tx";
+
+			clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
+				 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
+				 <&periph_clk BCM6368_CLK_ROBOSW>;
+
+			resets = <&periph_rst BCM6368_RST_SWITCH>,
+				 <&periph_rst BCM6368_RST_EPHY>;
+
+			dma-rx = <0>;
+			dma-tx = <1>;
+
+			status = "disabled";
+		};
+
+		switch0: switch@10f00000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-switch";
+			reg = <0x10f00000 0x8000>;
+			big-endian;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					phy-mode = "internal";
+					ethernet = <&ethernet>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+
+		mdio: mdio@10f000b0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm6368-mdio-mux";
+			reg = <0x10f000b0 0x8>;
+
+			mdio_int: mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				phy1: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <1>;
+				};
+
+				phy2: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+				};
+
+				phy3: ethernet-phy@3 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <3>;
+				};
+
+				phy4: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <4>;
+				};
+			};
+
+			mdio_ext: mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>;
+			};
+		};
+	};
+
+	pflash: nor@18000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x18000000 0x2000000>;
+		bank-width = <2>;
+
+		status = "disabled";
+	};
+};

target/linux/bmips/dts/bcm6369-comtrend-wap-5813n.dts

@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Comtrend WAP-5813n";
+	compatible = "comtrend,wap-5813n", "brcm,bcm6369", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WLAN>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@5 {
+			label = "green:internet";
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@14 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_green: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		led@23 {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@24 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+
+		led@31 {
+			label = "red:internet";
+			gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	bcm4322-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <1>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm4322-sprom.bin";
+		brcm,sprom-fixups = <97 0xfeed>,
+				    <98 0x15d1>,
+				    <99 0xfb0d>,
+				    <113 0xfef7>,
+				    <114 0x15f7>,
+				    <115 0xfb1a>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&lsspi {
+	status = "okay";
+
+	switch@0 {
+		compatible = "brcm,bcm53115";
+		reg = <0>;
+		spi-max-frequency = <781000>;
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan4";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan3";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan1";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "wan";
+			};
+
+			port@5 {
+				reg = <5>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port4>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x000000 0x010000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			label = "firmware";
+			reg = <0x010000 0x7e0000>;
+			compatible = "brcm,bcm963xx-imagetag";
+		};
+
+		partition@fe0000 {
+			label = "nvram";
+			reg = <0x7f0000 0x010000>;
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/dts/bcm6369-netgear-evg2000.dts

@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "bcm6368.dtsi"
+
+/ {
+	model = "Netgear EVG2000";
+	compatible = "netgear,evg2000", "brcm,bcm6369", "brcm,bcm6368";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "green:voip2";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@4 {
+			label = "red:internet";
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		led@5 {
+			label = "green:internet";
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		led@14 {
+			label = "green:voip1";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+
+		led@15 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_green: led@22 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led@23 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+			panic-indicator;
+		};
+
+		led@24 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+		};
+
+		led@27 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	bcm4322-sprom {
+		compatible = "brcm,ssb-sprom";
+
+		pci-bus = <0>;
+		pci-dev = <1>;
+
+		nvmem-cells = <&macaddr_cfe_6a0 1>;
+		nvmem-cell-names = "mac-address";
+
+		brcm,sprom = "brcm/bcm4322-sprom.bin";
+		brcm,sprom-fixups = <219 0xec08>;
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&mdio_ext {
+	switch@1e {
+		compatible = "brcm,bcm53115";
+		reg = <30>;
+
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "wan";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan1";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan3";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan4";
+			};
+
+			port@8 {
+				reg = <8>;
+
+				phy-mode = "rgmii";
+				ethernet = <&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port5: port@5 {
+			reg = <5>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&pflash {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "CFE";
+			reg = <0x000000 0x020000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_cfe_6a0: macaddr@6a0 {
+					compatible = "mac-base";
+					reg = <0x6a0 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@20000 {
+			label = "firmware";
+			reg = <0x020000 0xf40000>;
+			compatible = "brcm,bcm963xx-imagetag";
+		};
+
+		partition@f60000 {
+			label = "board_data";
+			reg = <0xf60000 0x080000>;
+			read-only;
+		};
+
+		partition@fe0000 {
+			label = "nvram";
+			reg = <0xfe0000 0x020000>;
+		};
+	};
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pci {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};

target/linux/bmips/files/arch/mips/pci/fixup-bmips.c

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <linux/pci.h>
+
+int bmips_pci_irq = -1;
+
+int pcibios_plat_dev_init(struct pci_dev *pci_dev)
+{
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_map_irq(const struct pci_dev *pci_dev, u8 slot, u8 pin)
+{
+	return bmips_pci_irq;
+}

target/linux/bmips/files/drivers/leds/leds-sercomm-msp430.c

@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Sercomm MSP430G2513 LEDs.
+ *
+ * Copyright 2023 Álvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spi/spi.h>
+#include "leds.h"
+
+/*
+ * MSP430G2513 SPI protocol description:
+ * +----+----+----+----+----+----+
+ * | b1 | b2 | b3 | b4 | b5 | b6 |
+ * +----+----+----+----+----+----+
+ * 6 bytes TX & RX per transaction.
+ *
+ * LEDs:
+ * MSP430G2513 can control up to 9 LEDs.
+ * b1: LED ID [1,9]
+ * b2: LED function
+ * b3-b6: LED function parameters
+ *
+ * LED functions:
+ * [0] Off
+ * [1] On
+ * [2] Flash
+ *   - b4: delay (x 6ms)
+ *   - b5: repeat (0 = infinite)
+ * [3] Pulse
+ *   - b3: delay (x 6ms)
+ *   - b4: blink while pulsing? (unknown)
+ *   - b5: repeat (0 = infinite)
+ * [4] Pulse On
+ *   - b3: delay (x 6ms)
+ *   - b4: blink while pulsing? (unknown)
+ *   - b5: repeat (0 = infinite)
+ * [5] Pulse Off
+ *   - b3: delay (x 6ms)
+ *   - b4: blink while pulsing? (unknown)
+ *   - b5: repeat (0 = infinite)
+ * [6] Level
+ *   - b3: brightness [0,4]
+ *
+ * MCU Commands (b1 = 0x55):
+ * [0x0a] FW upgrade data
+ *   - b3: Data size (usually 0x40), which is appended to TX & RX.
+ * [0x31] Get MCU version? (unknown)
+ * [0x68] Get MCU work mode
+ * [0xa5] Start FW upgrade
+ * [0xf0] End FW upgrade
+ */
+
+#define MSP430_CMD_BYTES		6
+#define MSP430_CMD_MCU			0x55
+#define MSP430_MCU_WM			0x68
+
+#define MSP430_LED_MIN_ID		1
+#define MSP430_LED_MAX_ID		9
+
+#define MSP430_LED_OFF			0
+#define MSP430_LED_ON			1
+#define MSP430_LED_FLASH		2
+#define MSP430_LED_PULSE		3
+#define MSP430_LED_PULSE_ON		4
+#define MSP430_LED_PULSE_OFF		5
+#define MSP430_LED_LEVEL		6
+
+#define MSP430_LED_BLINK_DEF		500
+#define MSP430_LED_BLINK_MASK		0xff
+#define MSP430_LED_BLINK_MS		6
+#define MSP430_LED_BLINK_MAX		(MSP430_LED_BLINK_MS * \
+					 MSP430_LED_BLINK_MASK)
+
+#define MSP430_LED_BRIGHTNESS_MAX	5
+#define MSP430_LED_REPEAT_MAX		0xff
+
+/**
+ * struct msp430_led - state container for Sercomm MSP430 based LEDs
+ * @cdev: LED class device for this LED
+ * @spi: spi resource
+ * @id: LED ID
+ */
+struct msp430_led {
+	struct led_classdev cdev;
+	struct spi_device *spi;
+	u8 id;
+};
+
+static inline int msp430_cmd(struct spi_device *spi, u8 tx[MSP430_CMD_BYTES],
+			     u8 rx[MSP430_CMD_BYTES])
+{
+	struct device *dev = &spi->dev;
+	int rc;
+
+	memset(rx, 0, MSP430_CMD_BYTES);
+
+	rc = spi_write_then_read(spi, tx, MSP430_CMD_BYTES,
+				  rx, MSP430_CMD_BYTES);
+	if (rc)
+		dev_err(dev, "spi error\n");
+
+	dev_dbg(dev, "msp430_cmd: [%02x %02x %02x %02x %02x %02x]"
+		" -> [%02x %02x %02x %02x %02x %02x]",
+		tx[0], tx[1], tx[2], tx[3], tx[4], tx[5],
+		rx[0], rx[1], rx[2], rx[3], rx[4], rx[5]);
+
+	return rc;
+}
+
+static unsigned long msp430_blink_delay(unsigned long delay)
+{
+	unsigned long msp430_delay;
+
+	msp430_delay = delay + MSP430_LED_BLINK_MS / 2;
+	msp430_delay = msp430_delay / MSP430_LED_BLINK_MS;
+	if (msp430_delay == 0)
+		msp430_delay = 1;
+
+	return msp430_delay;
+}
+
+static int msp430_blink_set(struct led_classdev *led_cdev,
+			    unsigned long *delay_on,
+			    unsigned long *delay_off)
+{
+	struct msp430_led *led =
+		container_of(led_cdev, struct msp430_led, cdev);
+	u8 tx[MSP430_CMD_BYTES] = {led->id, MSP430_LED_FLASH, 0, 0, 0, 0};
+	u8 rx[MSP430_CMD_BYTES];
+	unsigned long delay;
+
+	if (!*delay_on)
+		*delay_on = MSP430_LED_BLINK_DEF;
+	if (!*delay_off)
+		*delay_off = MSP430_LED_BLINK_DEF;
+
+	delay = msp430_blink_delay(*delay_on);
+	if (delay != msp430_blink_delay(*delay_off)) {
+		dev_dbg(led_cdev->dev,
+			"fallback to soft blinking (delay_on != delay_off)\n");
+		return -EINVAL;
+	}
+
+	if (delay > MSP430_LED_BLINK_MASK) {
+		dev_dbg(led_cdev->dev,
+			"fallback to soft blinking (delay > %ums)\n",
+			MSP430_LED_BLINK_MAX);
+		return -EINVAL;
+	}
+
+	tx[3] = delay;
+
+	return msp430_cmd(led->spi, tx, rx);
+}
+
+static int msp430_brightness_set(struct led_classdev *led_cdev,
+				 enum led_brightness brightness)
+{
+	struct msp430_led *led =
+		container_of(led_cdev, struct msp430_led, cdev);
+	u8 tx[MSP430_CMD_BYTES] = {led->id, 0, 0, 0, 0, 0};
+	u8 rx[MSP430_CMD_BYTES];
+	u8 val = (u8) brightness;
+
+	switch (val)
+	{
+	case LED_OFF:
+		tx[1] = MSP430_LED_OFF;
+		break;
+	case MSP430_LED_BRIGHTNESS_MAX:
+		tx[1] = MSP430_LED_ON;
+		break;
+	default:
+		tx[1] = MSP430_LED_LEVEL;
+		tx[2] = val - 1;
+		break;
+	}
+
+	return msp430_cmd(led->spi, tx, rx);
+}
+
+static int msp430_pattern_clear(struct led_classdev *ldev)
+{
+	msp430_brightness_set(ldev, LED_OFF);
+
+	return 0;
+}
+
+static int msp430_pattern_set(struct led_classdev *led_cdev,
+			      struct led_pattern *pattern,
+			      u32 len, int repeat)
+{
+	struct msp430_led *led =
+		container_of(led_cdev, struct msp430_led, cdev);
+	u8 tx[MSP430_CMD_BYTES] = {led->id, 0, 0, 0, 0, 0};
+	u8 rx[MSP430_CMD_BYTES];
+	unsigned long delay0;
+	unsigned long delay1;
+	int rc;
+
+	if (len != 2 ||
+	    repeat > MSP430_LED_REPEAT_MAX ||
+	    pattern[0].delta_t > MSP430_LED_BLINK_MAX ||
+	    pattern[1].delta_t > MSP430_LED_BLINK_MAX)
+		return -EINVAL;
+
+	delay0 = msp430_blink_delay(pattern[0].delta_t);
+	delay1 = msp430_blink_delay(pattern[1].delta_t);
+
+	/* Infinite pattern */
+	if (repeat < 0)
+		repeat = 0;
+
+	/* Pulse: <off> <delay> <max> <delay> */
+	if (delay0 == delay1 &&
+	    pattern[0].brightness == LED_OFF &&
+	    pattern[1].brightness == MSP430_LED_BRIGHTNESS_MAX)
+	{
+		tx[1] = MSP430_LED_PULSE;
+		tx[2] = delay0;
+		tx[4] = (u8) repeat;
+	}
+
+	/* Pulse On: <off> <delay> <max> <0ms> */
+	if (pattern[0].delta_t != 0 &&
+	    pattern[1].delta_t == 0 &&
+	    pattern[0].brightness == LED_OFF &&
+	    pattern[1].brightness == MSP430_LED_BRIGHTNESS_MAX) {
+		tx[1] = MSP430_LED_PULSE_ON;
+		tx[2] = delay0;
+		tx[4] = (u8) repeat;
+	}
+
+	/* Pulse Off: <max> <delay> <off> <0ms> */
+	if (pattern[0].delta_t != 0 &&
+	    pattern[1].delta_t == 0 &&
+	    pattern[0].brightness == MSP430_LED_BRIGHTNESS_MAX &&
+	    pattern[1].brightness == LED_OFF) {
+		tx[1] = MSP430_LED_PULSE_OFF;
+		tx[2] = delay0;
+		tx[4] = (u8) repeat;
+	}
+
+	if (!tx[1])
+		return -EINVAL;
+
+	rc = msp430_cmd(led->spi, tx, rx);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+static int msp430_led(struct spi_device *spi, struct device_node *nc, u8 id)
+{
+	struct device *dev = &spi->dev;
+	struct led_init_data init_data = {};
+	struct msp430_led *led;
+	enum led_default_state state;
+	int rc;
+
+	led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL);
+	if (!led)
+		return -ENOMEM;
+
+	led->id = id;
+	led->spi = spi;
+
+	init_data.fwnode = of_fwnode_handle(nc);
+
+	state = led_init_default_state_get(init_data.fwnode);
+	switch (state) {
+	case LEDS_DEFSTATE_ON:
+		led->cdev.brightness = MSP430_LED_BRIGHTNESS_MAX;
+		break;
+	default:
+		led->cdev.brightness = LED_OFF;
+		break;
+	}
+
+	msp430_brightness_set(&led->cdev, led->cdev.brightness);
+
+	led->cdev.blink_set = msp430_blink_set;
+	led->cdev.brightness_set_blocking = msp430_brightness_set;
+	led->cdev.max_brightness = MSP430_LED_BRIGHTNESS_MAX;
+	led->cdev.pattern_clear = msp430_pattern_clear;
+	led->cdev.pattern_set = msp430_pattern_set;
+
+	rc = devm_led_classdev_register_ext(dev, &led->cdev, &init_data);
+	if (rc < 0)
+		return rc;
+
+	dev_dbg(dev, "registered LED %s\n", led->cdev.name);
+
+	return 0;
+}
+
+static inline int msp430_check_workmode(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+	u8 tx[MSP430_CMD_BYTES] = {MSP430_CMD_MCU, MSP430_MCU_WM, 0, 0, 0, 0};
+	u8 rx[MSP430_CMD_BYTES];
+	int rc;
+
+	rc = msp430_cmd(spi, tx, rx);
+	if (rc)
+		return rc;
+
+	if ((rx[3] == 0xA5 && rx[4] == 'Z') ||
+	    (rx[4] == 0xA5 && rx[5] == 'Z') ||
+	    (rx[4] == '\b' && rx[5] == '\n')) {
+		dev_err(dev, "invalid workmode: "
+			"[%02x %02x %02x %02x %02x %02x]\n",
+			rx[0], rx[1], rx[2], rx[3], rx[4], rx[5]);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int msp430_leds_probe(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+	struct device_node *np = dev_of_node(dev);
+	struct device_node *child;
+	int rc;
+
+	rc = msp430_check_workmode(spi);
+	if (rc)
+		return rc;
+
+	for_each_available_child_of_node(np, child) {
+		u32 reg;
+
+		if (of_property_read_u32(child, "reg", &reg))
+			continue;
+
+		if (reg < MSP430_LED_MIN_ID || reg > MSP430_LED_MAX_ID) {
+			dev_err(dev, "invalid LED (%u) [%d, %d]\n", reg,
+				MSP430_LED_MIN_ID, MSP430_LED_MAX_ID);
+			continue;
+		}
+
+		rc = msp430_led(spi, child, reg);
+		if (rc < 0) {
+			of_node_put(child);
+			return rc;
+		}
+	}
+
+	return 0;
+}
+
+static const struct of_device_id msp430_leds_of_match[] = {
+	{ .compatible = "sercomm,msp430-leds", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, msp430_leds_of_match);
+
+static const struct spi_device_id msp430_leds_id_table[] = {
+	{ "msp430-leds", 0 },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(spi, msp430_leds_id_table);
+
+static struct spi_driver msp430_leds_driver = {
+	.driver = {
+		.name = KBUILD_MODNAME,
+		.of_match_table = msp430_leds_of_match,
+	},
+	.id_table = msp430_leds_id_table,
+	.probe = msp430_leds_probe,
+};
+module_spi_driver(msp430_leds_driver);
+
+MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
+MODULE_DESCRIPTION("LED driver for Sercomm MSP430 controllers");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:leds-sercomm-msp430");

target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c

@@ -0,0 +1,815 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6348 PCI Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/memblock.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define CARDBUS_DUMMY_ID		0x6348
+#define CARDBUS_PCI_IDSEL		0x8
+#define FAKE_CB_BRIDGE_SLOT		0x1e
+
+#define BCMPCI_REG_TIMERS		0x40
+#define REG_TIMER_TRDY_SHIFT		0
+#define REG_TIMER_TRDY_MASK		(0xff << REG_TIMER_TRDY_SHIFT)
+#define REG_TIMER_RETRY_SHIFT		8
+#define REG_TIMER_RETRY_MASK		(0xff << REG_TIMER_RETRY_SHIFT)
+
+#define MPI_SP0_RANGE_REG		0x100
+#define MPI_SP0_REMAP_REG		0x104
+#define MPI_SP0_REMAP_ENABLE_MASK	(1 << 0)
+#define MPI_SP1_RANGE_REG		0x10C
+#define MPI_SP1_REMAP_REG		0x110
+#define MPI_SP1_REMAP_ENABLE_MASK	(1 << 0)
+
+#define MPI_L2PCFG_REG			0x11c
+#define MPI_L2PCFG_CFG_TYPE_SHIFT	0
+#define MPI_L2PCFG_CFG_TYPE_MASK	(0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
+#define MPI_L2PCFG_REG_SHIFT		2
+#define MPI_L2PCFG_REG_MASK		(0x3f << MPI_L2PCFG_REG_SHIFT)
+#define MPI_L2PCFG_FUNC_SHIFT		8
+#define MPI_L2PCFG_FUNC_MASK		(0x7 << MPI_L2PCFG_FUNC_SHIFT)
+#define MPI_L2PCFG_DEVNUM_SHIFT		11
+#define MPI_L2PCFG_DEVNUM_MASK		(0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
+#define MPI_L2PCFG_CFG_USEREG_MASK	(1 << 30)
+#define MPI_L2PCFG_CFG_SEL_MASK		(1 << 31)
+
+#define MPI_L2PMEMRANGE1_REG		0x120
+#define MPI_L2PMEMBASE1_REG		0x124
+#define MPI_L2PMEMREMAP1_REG		0x128
+#define MPI_L2PMEMRANGE2_REG		0x12C
+#define MPI_L2PMEMBASE2_REG		0x130
+#define MPI_L2PMEMREMAP2_REG		0x134
+#define MPI_L2PIORANGE_REG		0x138
+#define MPI_L2PIOBASE_REG		0x13C
+#define MPI_L2PIOREMAP_REG		0x140
+#define MPI_L2P_BASE_MASK		(0xffff8000)
+#define MPI_L2PREMAP_ENABLED_MASK	(1 << 0)
+#define MPI_L2PREMAP_IS_CARDBUS_MASK	(1 << 2)
+
+#define MPI_PCIMODESEL_REG		0x144
+#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
+#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
+#define MPI_PCIMODESEL_EXT_ARB_MASK	(1 << 2)
+#define MPI_PCIMODESEL_PREFETCH_SHIFT	4
+#define MPI_PCIMODESEL_PREFETCH_MASK	(0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
+
+#define MPI_LOCBUSCTL_REG		0x14c
+#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK	(1 << 0)
+#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK	(1 << 1)
+
+#define MPI_LOCINT_REG			0x150
+#define MPI_LOCINT_MASK(x)		(1 << (x + 16))
+#define MPI_LOCINT_STAT(x)		(1 << (x))
+#define MPI_LOCINT_DIR_FAILED		6
+#define MPI_LOCINT_EXT_PCI_INT		7
+#define MPI_LOCINT_SERR			8
+#define MPI_LOCINT_CSERR		9
+
+#define MPI_PCICFGCTL_REG		0x178
+#define MPI_PCICFGCTL_CFGADDR_SHIFT	2
+#define MPI_PCICFGCTL_CFGADDR_MASK	(0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
+#define MPI_PCICFGCTL_WRITEEN_MASK	(1 << 7)
+
+#define MPI_PCICFGDATA_REG		0x17c
+
+#define PCMCIA_OFFSET			0x54
+
+#define PCMCIA_C1_REG			0x0
+#define PCMCIA_C1_CD1_MASK		(1 << 0)
+#define PCMCIA_C1_CD2_MASK		(1 << 1)
+#define PCMCIA_C1_VS1_MASK		(1 << 2)
+#define PCMCIA_C1_VS2_MASK		(1 << 3)
+#define PCMCIA_C1_VS1OE_MASK		(1 << 6)
+#define PCMCIA_C1_VS2OE_MASK		(1 << 7)
+#define PCMCIA_C1_CBIDSEL_SHIFT		(8)
+#define PCMCIA_C1_CBIDSEL_MASK		(0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
+#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK	(1 << 13)
+#define PCMCIA_C1_EN_PCMCIA_MASK	(1 << 14)
+#define PCMCIA_C1_EN_CARDBUS_MASK	(1 << 15)
+#define PCMCIA_C1_RESET_MASK		(1 << 18)
+
+#ifdef CONFIG_CARDBUS
+struct bcm6348_cb {
+	u16 pci_command;
+	u8 cb_latency;
+	u8 subordinate_busn;
+	u8 cardbus_busn;
+	u8 pci_busn;
+	int bus_assigned;
+	u16 bridge_control;
+
+	u32 mem_base0;
+	u32 mem_limit0;
+	u32 mem_base1;
+	u32 mem_limit1;
+
+	u32 io_base0;
+	u32 io_limit0;
+	u32 io_base1;
+	u32 io_limit1;
+};
+#endif /* CONFIG_CARDBUS */
+
+struct bcm6348_pci {
+	void __iomem *pci;
+	void __iomem *pcmcia;
+	void __iomem *io;
+	int irq;
+	struct reset_control *reset;
+	bool remap;
+#ifdef CONFIG_CARDBUS
+	struct bcm6348_cb cb;
+	int cb_bus;
+#endif /* CONFIG_CARDBUS */
+};
+
+static struct bcm6348_pci bcm6348_pci;
+
+extern int bmips_pci_irq;
+
+static u32 bcm6348_int_cfg_readl(u32 reg)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	u32 tmp;
+
+	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
+	tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
+	__raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
+	iob();
+	return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
+}
+
+static void bcm6348_int_cfg_writel(u32 val, u32 reg)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	u32 tmp;
+
+	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
+	tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
+	__raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
+	__raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
+}
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (data >> ((where & 3) << 3)) & 0xff;
+		break;
+	case 2:
+		ret = (data >> ((where & 3) << 3)) & 0xffff;
+		break;
+	case 4:
+		ret = data;
+		break;
+	}
+
+	return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+			    unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+			(val << ((where & 3) << 3));
+		break;
+	case 2:
+		ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+			(val << ((where & 3) << 3));
+		break;
+	case 4:
+		ret = val;
+		break;
+	}
+
+	return ret;
+}
+
+static int bcm6348_setup_cfg_access(int type, unsigned int busn,
+				    unsigned int devfn, int where)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	unsigned int slot, func, reg;
+	u32 val;
+
+	slot = PCI_SLOT(devfn);
+	func = PCI_FUNC(devfn);
+	reg = where >> 2;
+
+	/* sanity check */
+	if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
+		return 1;
+
+	if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
+		return 1;
+
+	if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
+		return 1;
+
+	/* ok, setup config access */
+	val = (reg << MPI_L2PCFG_REG_SHIFT);
+	val |= (func << MPI_L2PCFG_FUNC_SHIFT);
+	val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
+	val |= MPI_L2PCFG_CFG_USEREG_MASK;
+	val |= MPI_L2PCFG_CFG_SEL_MASK;
+	/* type 0 cycle for local bus, type 1 cycle for anything else */
+	if (type != 0) {
+		/* FIXME: how to specify bus ??? */
+		val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
+	}
+	__raw_writel(val, priv->pci + MPI_L2PCFG_REG);
+
+	return 0;
+}
+
+
+static int bcm6348_do_cfg_read(int type, unsigned int busn,
+			       unsigned int devfn, int where, int size,
+			       u32 *val)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	u32 data;
+
+	/* two phase cycle, first we write address, then read data at
+	 * another location, caller already has a spinlock so no need
+	 * to add one here */
+	if (bcm6348_setup_cfg_access(type, busn, devfn, where))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	iob();
+	data = le32_to_cpu(__raw_readl(priv->io));
+	/* restore IO space normal behaviour */
+	__raw_writel(0, priv->pci + MPI_L2PCFG_REG);
+
+	*val = postprocess_read(data, where, size);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_do_cfg_write(int type, unsigned int busn,
+				unsigned int devfn, int where, int size,
+				u32 val)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	u32 data;
+
+	/* two phase cycle, first we write address, then write data to
+	 * another location, caller already has a spinlock so no need
+	 * to add one here */
+	if (bcm6348_setup_cfg_access(type, busn, devfn, where))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	iob();
+
+	data = le32_to_cpu(__raw_readl(priv->io));
+	data = preprocess_write(data, val, where, size);
+
+	__raw_writel(cpu_to_le32(data), priv->io);
+	wmb();
+	/* no way to know the access is done, we have to wait */
+	udelay(500);
+	/* restore IO space normal behaviour */
+	__raw_writel(0, priv->pci + MPI_L2PCFG_REG);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
+			     int where, int size, u32 *val)
+{
+	int type;
+
+	type = bus->parent ? 1 : 0;
+
+	if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	return bcm6348_do_cfg_read(type, bus->number, devfn,
+				   where, size, val);
+}
+
+static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
+			      int where, int size, u32 val)
+{
+	int type;
+
+	type = bus->parent ? 1 : 0;
+
+	if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	return bcm6348_do_cfg_write(type, bus->number, devfn,
+				    where, size, val);
+}
+
+static struct pci_ops bcm6348_pci_ops = {
+	.read = bcm6348_pci_read,
+	.write = bcm6348_pci_write,
+};
+
+static struct resource bcm6348_pci_io_resource;
+static struct resource bcm6348_pci_mem_resource;
+static struct resource bcm6348_pci_busn_resource;
+
+static struct pci_controller bcm6348_pci_controller = {
+	.pci_ops = &bcm6348_pci_ops,
+	.io_resource = &bcm6348_pci_io_resource,
+	.mem_resource = &bcm6348_pci_mem_resource,
+};
+
+#ifdef CONFIG_CARDBUS
+static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
+{
+	struct bcm6348_cb *cb = &bcm6348_pci.cb;
+	unsigned int reg;
+	u32 data;
+
+	data = 0;
+	reg = where >> 2;
+	switch (reg) {
+	case (PCI_VENDOR_ID >> 2):
+	case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
+		/* create dummy vendor/device id from our cpu id */
+		data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
+		break;
+
+	case (PCI_COMMAND >> 2):
+		data = (PCI_STATUS_DEVSEL_SLOW << 16);
+		data |= cb->pci_command;
+		break;
+
+	case (PCI_CLASS_REVISION >> 2):
+		data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
+		break;
+
+	case (PCI_CACHE_LINE_SIZE >> 2):
+		data = (PCI_HEADER_TYPE_CARDBUS << 16);
+		break;
+
+	case (PCI_INTERRUPT_LINE >> 2):
+		/* bridge control */
+		data = (cb->bridge_control << 16);
+		/* pin:intA line:0xff */
+		data |= (0x1 << 8) | 0xff;
+		break;
+
+	case (PCI_CB_PRIMARY_BUS >> 2):
+		data = (cb->cb_latency << 24);
+		data |= (cb->subordinate_busn << 16);
+		data |= (cb->cardbus_busn << 8);
+		data |= cb->pci_busn;
+		break;
+
+	case (PCI_CB_MEMORY_BASE_0 >> 2):
+		data = cb->mem_base0;
+		break;
+
+	case (PCI_CB_MEMORY_LIMIT_0 >> 2):
+		data = cb->mem_limit0;
+		break;
+
+	case (PCI_CB_MEMORY_BASE_1 >> 2):
+		data = cb->mem_base1;
+		break;
+
+	case (PCI_CB_MEMORY_LIMIT_1 >> 2):
+		data = cb->mem_limit1;
+		break;
+
+	case (PCI_CB_IO_BASE_0 >> 2):
+		/* | 1 for 32bits io support */
+		data = cb->io_base0 | 0x1;
+		break;
+
+	case (PCI_CB_IO_LIMIT_0 >> 2):
+		data = cb->io_limit0;
+		break;
+
+	case (PCI_CB_IO_BASE_1 >> 2):
+		/* | 1 for 32bits io support */
+		data = cb->io_base1 | 0x1;
+		break;
+
+	case (PCI_CB_IO_LIMIT_1 >> 2):
+		data = cb->io_limit1;
+		break;
+	}
+
+	*val = postprocess_read(data, where, size);
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * emulate configuration write access on a cardbus bridge
+ */
+static int bcm6348_cb_bridge_write(int where, int size, u32 val)
+{
+	struct bcm6348_cb *cb = &bcm6348_pci.cb;
+	unsigned int reg;
+	u32 data, tmp;
+	int ret;
+
+	ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
+	if (ret != PCIBIOS_SUCCESSFUL)
+		return ret;
+
+	data = preprocess_write(data, val, where, size);
+
+	reg = where >> 2;
+	switch (reg) {
+	case (PCI_COMMAND >> 2):
+		cb->pci_command = (data & 0xffff);
+		break;
+
+	case (PCI_CB_PRIMARY_BUS >> 2):
+		cb->cb_latency = (data >> 24) & 0xff;
+		cb->subordinate_busn = (data >> 16) & 0xff;
+		cb->cardbus_busn = (data >> 8) & 0xff;
+		cb->pci_busn = data & 0xff;
+		if (cb->cardbus_busn)
+			cb->bus_assigned = 1;
+		break;
+
+	case (PCI_INTERRUPT_LINE >> 2):
+		tmp = (data >> 16) & 0xffff;
+		/* Disable memory prefetch support */
+		tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
+		tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
+		cb->bridge_control = tmp;
+		break;
+
+	case (PCI_CB_MEMORY_BASE_0 >> 2):
+		cb->mem_base0 = data;
+		break;
+
+	case (PCI_CB_MEMORY_LIMIT_0 >> 2):
+		cb->mem_limit0 = data;
+		break;
+
+	case (PCI_CB_MEMORY_BASE_1 >> 2):
+		cb->mem_base1 = data;
+		break;
+
+	case (PCI_CB_MEMORY_LIMIT_1 >> 2):
+		cb->mem_limit1 = data;
+		break;
+
+	case (PCI_CB_IO_BASE_0 >> 2):
+		cb->io_base0 = data;
+		break;
+
+	case (PCI_CB_IO_LIMIT_0 >> 2):
+		cb->io_limit0 = data;
+		break;
+
+	case (PCI_CB_IO_BASE_1 >> 2):
+		cb->io_base1 = data;
+		break;
+
+	case (PCI_CB_IO_LIMIT_1 >> 2):
+		cb->io_limit1 = data;
+		break;
+	}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
+			   int where, int size, u32 *val)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	struct bcm6348_cb *cb = &priv->cb;
+
+	/* Snoop access to slot 0x1e on root bus, we fake a cardbus
+	 * bridge at this location */
+	if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
+		priv->cb_bus = bus->number;
+		return bcm6348_cb_bridge_read(where, size, val);
+	}
+
+	/* A configuration cycle for the device behind the cardbus
+	 * bridge is actually done as a type 0 cycle on the primary
+	 * bus. This means that only one device can be on the cardbus
+	 * bus */
+	if (cb->bus_assigned &&
+	    bus->number == cb->cardbus_busn &&
+	    PCI_SLOT(devfn) == 0)
+		return bcm6348_do_cfg_read(0, 0,
+					   PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
+					   where, size, val);
+
+	return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
+			    int where, int size, u32 val)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	struct bcm6348_cb *cb = &priv->cb;
+
+	if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
+		priv->cb_bus = bus->number;
+		return bcm6348_cb_bridge_write(where, size, val);
+	}
+
+	if (cb->bus_assigned &&
+	    bus->number == cb->cardbus_busn &&
+	    PCI_SLOT(devfn) == 0)
+		return bcm6348_do_cfg_write(0, 0,
+					    PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
+					    where, size, val);
+
+	return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
+static struct pci_ops bcm6348_cb_ops = {
+	.read = bcm6348_cb_read,
+	.write = bcm6348_cb_write,
+};
+
+/*
+ * only one IO window, so it  cannot be shared by PCI and cardbus, use
+ * fixup to choose and detect unhandled configuration
+ */
+static void bcm6348_pci_fixup(struct pci_dev *dev)
+{
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	struct bcm6348_cb *cb = &priv->cb;
+	static int io_window = -1;
+	int i, found, new_io_window;
+	u32 val;
+
+	/* look for any io resource */
+	found = 0;
+	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+		if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
+			found = 1;
+			break;
+		}
+	}
+
+	if (!found)
+		return;
+
+	/* skip our fake bus with only cardbus bridge on it */
+	if (dev->bus->number == priv->cb_bus)
+		return;
+
+	/* find on which bus the device is */
+	if (cb->bus_assigned &&
+	    dev->bus->number == cb->cardbus_busn &&
+	    PCI_SLOT(dev->devfn) == 0)
+		new_io_window = 1;
+	else
+		new_io_window = 0;
+
+	if (new_io_window == io_window)
+		return;
+
+	if (io_window != -1) {
+		pr_err("bcm63xx: both PCI and cardbus devices "
+		       "need IO, which hardware cannot do\n");
+		return;
+	}
+
+	pr_info("bcm63xx: PCI IO window assigned to %s\n",
+	       (new_io_window == 0) ? "PCI" : "cardbus");
+
+	val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
+	if (io_window)
+		val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
+	else
+		val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
+	__raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
+
+	io_window = new_io_window;
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
+
+static struct resource bcm6348_cb_io_resource = {
+	.name = "bcm6348 CB IO space",
+	.flags = IORESOURCE_IO,
+};
+static struct resource bcm6348_cb_mem_resource;
+
+static struct pci_controller bcm6348_cb_controller = {
+	.pci_ops = &bcm6348_cb_ops,
+	.io_resource = &bcm6348_cb_io_resource,
+	.mem_resource = &bcm6348_cb_mem_resource,
+};
+#endif /* CONFIG_CARDBUS */
+
+static void bcm6348_pci_setup(struct bcm6348_pci *priv)
+{
+	u32 val;
+
+	/* Setup local bus to PCI access (PCI memory) */
+	val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
+	__raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
+	__raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
+		     priv->pci + MPI_L2PMEMRANGE1_REG);
+	__raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
+		     priv->pci + MPI_L2PMEMREMAP1_REG);
+
+	/* Set Cardbus IDSEL (type 0 cfg access on primary bus for
+	 * this IDSEL will be done on Cardbus instead) */
+	val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
+	val &= ~PCMCIA_C1_CBIDSEL_MASK;
+	val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
+	__raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
+
+#ifdef CONFIG_CARDBUS
+	/* setup local bus to PCI access (Cardbus memory) */
+	val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
+	__raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
+	__raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
+		     priv->pci + MPI_L2PMEMRANGE2_REG);
+	val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
+	__raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
+#else
+	/* disable second access windows */
+	__raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
+#endif
+
+	/* setup local bus to PCI access (IO memory), we have only 1
+	 * IO window for both PCI and cardbus, but it cannot handle
+	 * both at the same time, assume standard PCI for now, if
+	 * cardbus card has IO zone, PCI fixup will change window to
+	 * cardbus */
+	val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
+	__raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
+	__raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
+		     priv->pci + MPI_L2PIORANGE_REG);
+	__raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
+		     priv->pci + MPI_L2PIOREMAP_REG);
+
+	/* Enable PCI related GPIO pins */
+	__raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
+		     priv->pci + MPI_LOCBUSCTL_REG);
+
+	/* Setup PCI to local bus access, used by PCI device to target
+	 * local RAM while bus mastering */
+	bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
+	if (priv->remap)
+		val = MPI_SP0_REMAP_ENABLE_MASK;
+	else
+		val = 0;
+	__raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
+
+	bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
+	__raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
+
+	/* Setup sp0 range to local RAM size */
+	__raw_writel(~(memblock_phys_mem_size() - 1),
+		     priv->pci + MPI_SP0_RANGE_REG);
+	__raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
+
+	/* Change host bridge retry counter to infinite number of
+	 * retries, needed for some broadcom wifi cards with Silicon
+	 * Backplane bus where access to srom seems very slow */
+	val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
+	val &= ~REG_TIMER_RETRY_MASK;
+	bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
+
+	/* EEnable memory decoder and bus mastering */
+	val = bcm6348_int_cfg_readl(PCI_COMMAND);
+	val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	bcm6348_int_cfg_writel(val, PCI_COMMAND);
+
+	/* Enable read prefetching & disable byte swapping for bus
+	 * mastering transfers */
+	val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
+	val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
+	val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
+	val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
+	val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
+	__raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
+
+	/* Enable pci interrupt */
+	val = __raw_readl(priv->pci + MPI_LOCINT_REG);
+	val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
+	__raw_writel(val, priv->pci + MPI_LOCINT_REG);
+}
+
+static int bcm6348_pci_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct bcm6348_pci *priv = &bcm6348_pci;
+	struct resource *res;
+	LIST_HEAD(resources);
+
+	of_pci_check_probe_only();
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->pci = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->pci))
+		return PTR_ERR(priv->pci);
+
+	priv->pcmcia = priv->pci + PCMCIA_OFFSET;
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (!priv->irq)
+		return -ENODEV;
+
+	bmips_pci_irq = priv->irq;
+
+	priv->reset = devm_reset_control_get(dev, "pci");
+	if (IS_ERR(priv->reset))
+		return PTR_ERR(priv->reset);
+
+	priv->remap = of_property_read_bool(np, "brcm,remap");
+
+	reset_control_reset(priv->reset);
+
+	pci_load_of_ranges(&bcm6348_pci_controller, np);
+	if (!bcm6348_pci_mem_resource.start)
+		return -EINVAL;
+
+	of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
+	pci_add_resource(&resources, &bcm6348_pci_busn_resource);
+
+#ifdef CONFIG_CARDBUS
+	bcm6348_cb_io_resource.start = bcm6348_pci_io_resource.start + (resource_size(&bcm6348_pci_io_resource) >> 1);
+	bcm6348_cb_io_resource.end = bcm6348_pci_io_resource.end;
+	bcm6348_pci_io_resource.end = bcm6348_pci_io_resource.end - (resource_size(&bcm6348_pci_io_resource) >> 1);
+#endif
+
+	/*
+	 * Configuration accesses are done through IO space, remap 4
+	 * first bytes to access it from CPU.
+	 *
+	 * This means that no IO access from CPU should happen while
+	 * we do a configuration cycle, but there's no way we can add
+	 * a spinlock for each io access, so this is currently kind of
+	 * broken on SMP.
+	 */
+	priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
+	if (!priv->io)
+		return -ENOMEM;
+
+	bcm6348_pci_setup(priv);
+
+	register_pci_controller(&bcm6348_pci_controller);
+
+#ifdef CONFIG_CARDBUS
+	priv->cb_bus = -1;
+	register_pci_controller(&bcm6348_cb_controller);
+#endif /* CONFIG_CARDBUS */
+
+	/* Mark memory space used for IO mapping as reserved */
+	request_mem_region(bcm6348_pci_io_resource.start,
+			   resource_size(&bcm6348_pci_io_resource),
+			   "BCM6348 PCI IO space");
+
+	return 0;
+}
+
+static const struct of_device_id bcm6348_pci_of_match[] = {
+	{ .compatible = "brcm,bcm6348-pci", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, bcm6348_pci_of_match);
+
+static struct platform_driver bcm6348_pci_driver = {
+	.probe = bcm6348_pci_probe,
+	.driver	= {
+		.name = "bcm6348-pci",
+		.of_match_table = bcm6348_pci_of_match,
+	},
+};
+module_platform_driver(bcm6348_pci_driver);
+
+MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
+MODULE_DESCRIPTION("BCM6348 PCI Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:bcm6348-pci");

target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c

@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6318 PCIe Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define PCIE_BUS_BRIDGE			0
+#define PCIE_BUS_DEVICE			1
+
+#define PCIE_SPECIFIC_REG		0x188
+#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT	0
+#define SPECIFIC_ENDIAN_MODE_BAR1_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT	2
+#define SPECIFIC_ENDIAN_MODE_BAR2_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT	4
+#define SPECIFIC_ENDIAN_MODE_BAR3_MASK	(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
+#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN	0
+#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
+#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN	2
+
+#define PCIE_CONFIG2_REG		0x408
+#define CONFIG2_BAR1_SIZE_EN		1
+#define CONFIG2_BAR1_SIZE_MASK		0xf
+
+#define PCIE_IDVAL3_REG			0x43c
+#define IDVAL3_CLASS_CODE_MASK		0xffffff
+#define IDVAL3_SUBCLASS_SHIFT		8
+#define IDVAL3_CLASS_SHIFT		16
+
+#define PCIE_DLSTATUS_REG		0x1048
+#define DLSTATUS_PHYLINKUP		(1 << 13)
+
+#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG	0x400c
+#define C2P_MEM_WIN_ENDIAN_MODE_MASK	0x3
+#define C2P_MEM_WIN_ENDIAN_NO_SWAP	0
+#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
+#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
+#define C2P_MEM_WIN_BASE_ADDR_SHIFT	20
+#define C2P_MEM_WIN_BASE_ADDR_MASK	(0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
+
+#define PCIE_RC_BAR1_CONFIG_LO_REG	0x402c
+#define RC_BAR_CFG_LO_SIZE_256MB	0xd
+#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT	20
+#define RC_BAR_CFG_LO_MATCH_ADDR_MASK	(0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
+
+#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
+#define C2P_BASELIMIT_LIMIT_SHIFT	20
+#define C2P_BASELIMIT_LIMIT_MASK	(0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
+#define C2P_BASELIMIT_BASE_SHIFT	4
+#define C2P_BASELIMIT_BASE_MASK		(0xfff << C2P_BASELIMIT_BASE_SHIFT)
+
+#define PCIE_UBUS_BAR1_CFG_REMAP_REG	0x4088
+#define BAR1_CFG_REMAP_OFFSET_SHIFT	20
+#define BAR1_CFG_REMAP_OFFSET_MASK	(0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
+#define BAR1_CFG_REMAP_ACCESS_EN	1
+
+#define PCIE_HARD_DEBUG_REG		0x4204
+#define HARD_DEBUG_SERDES_IDDQ		(1 << 23)
+
+#define PCIE_CPU_INT1_MASK_CLEAR_REG	0x830c
+#define CPU_INT_PCIE_ERR_ATTN_CPU	(1 << 0)
+#define CPU_INT_PCIE_INTA		(1 << 1)
+#define CPU_INT_PCIE_INTB		(1 << 2)
+#define CPU_INT_PCIE_INTC		(1 << 3)
+#define CPU_INT_PCIE_INTD		(1 << 4)
+#define CPU_INT_PCIE_INTR		(1 << 5)
+#define CPU_INT_PCIE_NMI		(1 << 6)
+#define CPU_INT_PCIE_UBUS		(1 << 7)
+#define CPU_INT_IPI			(1 << 8)
+
+#define PCIE_EXT_CFG_INDEX_REG		0x8400
+#define EXT_CFG_FUNC_NUM_SHIFT		12
+#define EXT_CFG_FUNC_NUM_MASK		(0x7 << EXT_CFG_FUNC_NUM_SHIFT)
+#define EXT_CFG_DEV_NUM_SHIFT		15
+#define EXT_CFG_DEV_NUM_MASK		(0xf << EXT_CFG_DEV_NUM_SHIFT)
+#define EXT_CFG_BUS_NUM_SHIFT		20
+#define EXT_CFG_BUS_NUM_MASK		(0xff << EXT_CFG_BUS_NUM_SHIFT)
+
+#define PCIE_DEVICE_OFFSET		0x9000
+
+struct bcm6318_pcie {
+	void __iomem *base;
+	int irq;
+	struct clk *clk;
+	struct clk *clk25;
+	struct clk *clk_ubus;
+	struct reset_control *reset;
+	struct reset_control *reset_ext;
+	struct reset_control *reset_core;
+	struct reset_control *reset_hard;
+};
+
+static struct bcm6318_pcie bcm6318_pcie;
+
+extern int bmips_pci_irq;
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (data >> ((where & 3) << 3)) & 0xff;
+		break;
+	case 2:
+		ret = (data >> ((where & 3) << 3)) & 0xffff;
+		break;
+	case 4:
+		ret = data;
+		break;
+	}
+
+	return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+			    unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+			(val << ((where & 3) << 3));
+		break;
+	case 2:
+		ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+			(val << ((where & 3) << 3));
+		break;
+	case 4:
+		ret = val;
+		break;
+	}
+
+	return ret;
+}
+
+static int bcm6318_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+	struct bcm6318_pcie *priv = &bcm6318_pcie;
+
+	switch (bus->number) {
+	case PCIE_BUS_BRIDGE:
+		return PCI_SLOT(devfn) == 0;
+	case PCIE_BUS_DEVICE:
+		if (PCI_SLOT(devfn) == 0)
+			return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
+					& DLSTATUS_PHYLINKUP;
+		fallthrough;
+	default:
+		return false;
+	}
+}
+
+static int bcm6318_pcie_read(struct pci_bus *bus, unsigned int devfn,
+			     int where, int size, u32 *val)
+{
+	struct bcm6318_pcie *priv = &bcm6318_pcie;
+	u32 data;
+	u32 reg = where & ~3;
+
+	if (!bcm6318_pcie_can_access(bus, devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (bus->number == PCIE_BUS_DEVICE)
+		reg += PCIE_DEVICE_OFFSET;
+
+	data = __raw_readl(priv->base + reg);
+	*val = postprocess_read(data, where, size);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6318_pcie_write(struct pci_bus *bus, unsigned int devfn,
+			      int where, int size, u32 val)
+{
+	struct bcm6318_pcie *priv = &bcm6318_pcie;
+	u32 data;
+	u32 reg = where & ~3;
+
+	if (!bcm6318_pcie_can_access(bus, devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (bus->number == PCIE_BUS_DEVICE)
+		reg += PCIE_DEVICE_OFFSET;
+
+	data = __raw_readl(priv->base + reg);
+	data = preprocess_write(data, val, where, size);
+	__raw_writel(data, priv->base + reg);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops bcm6318_pcie_ops = {
+	.read = bcm6318_pcie_read,
+	.write = bcm6318_pcie_write,
+};
+
+static struct resource bcm6318_pcie_io_resource;
+static struct resource bcm6318_pcie_mem_resource;
+static struct resource bcm6318_pcie_busn_resource;
+
+static struct pci_controller bcm6318_pcie_controller = {
+	.pci_ops = &bcm6318_pcie_ops,
+	.io_resource = &bcm6318_pcie_io_resource,
+	.mem_resource = &bcm6318_pcie_mem_resource,
+};
+
+static void bcm6318_pcie_reset(struct bcm6318_pcie *priv)
+{
+	u32 val;
+
+	reset_control_deassert(priv->reset_hard);
+
+	reset_control_assert(priv->reset);
+	reset_control_assert(priv->reset_core);
+	reset_control_assert(priv->reset_ext);
+	mdelay(10);
+
+	reset_control_deassert(priv->reset_ext);
+	mdelay(10);
+
+	reset_control_deassert(priv->reset);
+	mdelay(10);
+
+	val = __raw_readl(priv->base + PCIE_HARD_DEBUG_REG);
+	val &= ~HARD_DEBUG_SERDES_IDDQ;
+	__raw_writel(val, priv->base + PCIE_HARD_DEBUG_REG);
+	mdelay(10);
+
+	reset_control_deassert(priv->reset_core);
+	mdelay(200);
+}
+
+static void bcm6318_pcie_setup(struct bcm6318_pcie *priv)
+{
+	u32 val;
+
+	__raw_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
+		     CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
+		     priv->base + PCIE_CPU_INT1_MASK_CLEAR_REG);
+
+	val = bcm6318_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
+	val |= (bcm6318_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT)
+	       << C2P_BASELIMIT_BASE_SHIFT;
+	__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
+
+	/* setup class code as bridge */
+	val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
+	val &= ~IDVAL3_CLASS_CODE_MASK;
+	val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+	__raw_writel(val, priv->base + PCIE_IDVAL3_REG);
+
+	/* disable bar1 size */
+	val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
+	val &= ~CONFIG2_BAR1_SIZE_MASK;
+	__raw_writel(val, priv->base + PCIE_CONFIG2_REG);
+
+	/* set bar0 to little endian */
+	val = __raw_readl(priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
+	val |= bcm6318_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
+	val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
+	__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
+
+	__raw_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN,
+		     priv->base + PCIE_SPECIFIC_REG);
+
+	__raw_writel(RC_BAR_CFG_LO_SIZE_256MB,
+		     priv->base + PCIE_RC_BAR1_CONFIG_LO_REG);
+
+	__raw_writel(BAR1_CFG_REMAP_ACCESS_EN,
+		     priv->base + PCIE_UBUS_BAR1_CFG_REMAP_REG);
+
+	__raw_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
+		     priv->base + PCIE_EXT_CFG_INDEX_REG);
+}
+
+static int bcm6318_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct bcm6318_pcie *priv = &bcm6318_pcie;
+	struct resource *res;
+	int ret;
+	LIST_HEAD(resources);
+
+	of_pci_check_probe_only();
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (!priv->irq)
+		return -ENODEV;
+
+	bmips_pci_irq = priv->irq;
+
+	priv->reset = devm_reset_control_get(dev, "pcie");
+	if (IS_ERR(priv->reset))
+		return PTR_ERR(priv->reset);
+
+	priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
+	if (IS_ERR(priv->reset_ext))
+		return PTR_ERR(priv->reset_ext);
+
+	priv->reset_core = devm_reset_control_get(dev, "pcie-core");
+	if (IS_ERR(priv->reset_core))
+		return PTR_ERR(priv->reset_core);
+
+	priv->reset_hard = devm_reset_control_get(dev, "pcie-hard");
+	if (IS_ERR(priv->reset_hard))
+		return PTR_ERR(priv->reset_hard);
+
+	priv->clk = devm_clk_get(dev, "pcie");
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	priv->clk25 = devm_clk_get(dev, "pcie25");
+	if (IS_ERR(priv->clk25))
+		return PTR_ERR(priv->clk25);
+
+	priv->clk_ubus = devm_clk_get(dev, "pcie-ubus");
+	if (IS_ERR(priv->clk_ubus))
+		return PTR_ERR(priv->clk_ubus);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "could not enable clock\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->clk25);
+	if (ret) {
+		dev_err(dev, "could not enable clock\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->clk_ubus);
+	if (ret) {
+		dev_err(dev, "could not enable clock\n");
+		return ret;
+	}
+
+	pci_load_of_ranges(&bcm6318_pcie_controller, np);
+	if (!bcm6318_pcie_mem_resource.start)
+		return -EINVAL;
+
+	of_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource);
+	pci_add_resource(&resources, &bcm6318_pcie_busn_resource);
+
+	bcm6318_pcie_reset(priv);
+	bcm6318_pcie_setup(priv);
+
+	register_pci_controller(&bcm6318_pcie_controller);
+
+	return 0;
+}
+
+static const struct of_device_id bcm6318_pcie_of_match[] = {
+	{ .compatible = "brcm,bcm6318-pcie", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, bcm6318_pcie_of_match);
+
+static struct platform_driver bcm6318_pcie_driver = {
+	.probe = bcm6318_pcie_probe,
+	.driver	= {
+		.name = "bcm6318-pcie",
+		.of_match_table = bcm6318_pcie_of_match,
+	},
+};
+module_platform_driver(bcm6318_pcie_driver);
+
+MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
+MODULE_DESCRIPTION("BCM6318 PCIe Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:bcm6318-pcie");

target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c

@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM6328 PCIe Controller Driver
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+
+#include "../pci.h"
+
+#define SERDES_PCIE_EXD_EN		BIT(15)
+#define SERDES_PCIE_EN			BIT(0)
+
+#define PCIE_BUS_BRIDGE			0
+#define PCIE_BUS_DEVICE			1
+
+#define PCIE_CONFIG2_REG		0x408
+#define CONFIG2_BAR1_SIZE_EN		1
+#define CONFIG2_BAR1_SIZE_MASK		0xf
+
+#define PCIE_IDVAL3_REG			0x43c
+#define IDVAL3_CLASS_CODE_MASK		0xffffff
+#define IDVAL3_SUBCLASS_SHIFT		8
+#define IDVAL3_CLASS_SHIFT		16
+
+#define PCIE_DLSTATUS_REG		0x1048
+#define DLSTATUS_PHYLINKUP		(1 << 13)
+
+#define PCIE_BRIDGE_OPT1_REG		0x2820
+#define OPT1_RD_BE_OPT_EN		(1 << 7)
+#define OPT1_RD_REPLY_BE_FIX_EN		(1 << 9)
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN	(1 << 11)
+#define OPT1_L1_INT_STATUS_MASK_POL	(1 << 12)
+
+#define PCIE_BRIDGE_OPT2_REG		0x2824
+#define OPT2_UBUS_UR_DECODE_DIS		(1 << 2)
+#define OPT2_TX_CREDIT_CHK_EN		(1 << 4)
+#define OPT2_CFG_TYPE1_BD_SEL		(1 << 7)
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT	16
+#define OPT2_CFG_TYPE1_BUS_NO_MASK	(0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG	0x2828
+#define BASEMASK_REMAP_EN		(1 << 0)
+#define BASEMASK_SWAP_EN		(1 << 1)
+#define BASEMASK_MASK_SHIFT		4
+#define BASEMASK_MASK_MASK		(0xfff << BASEMASK_MASK_SHIFT)
+#define BASEMASK_BASE_SHIFT		20
+#define BASEMASK_BASE_MASK		(0xfff << BASEMASK_BASE_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
+#define REBASE_ADDR_BASE_SHIFT		20
+#define REBASE_ADDR_BASE_MASK		(0xfff << REBASE_ADDR_BASE_SHIFT)
+
+#define PCIE_BRIDGE_RC_INT_MASK_REG	0x2854
+#define PCIE_RC_INT_A			(1 << 0)
+#define PCIE_RC_INT_B			(1 << 1)
+#define PCIE_RC_INT_C			(1 << 2)
+#define PCIE_RC_INT_D			(1 << 3)
+
+#define PCIE_DEVICE_OFFSET		0x8000
+
+struct bcm6328_pcie {
+	void __iomem *base;
+	int irq;
+	struct regmap *serdes;
+	struct device **pm;
+	struct device_link **link_pm;
+	unsigned int num_pms;
+	struct clk *clk;
+	struct reset_control *reset;
+	struct reset_control *reset_ext;
+	struct reset_control *reset_core;
+	struct reset_control *reset_hard;
+};
+
+static struct bcm6328_pcie bcm6328_pcie;
+
+extern int bmips_pci_irq;
+
+/*
+ * swizzle 32bits data to return only the needed part
+ */
+static int postprocess_read(u32 data, int where, unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (data >> ((where & 3) << 3)) & 0xff;
+		break;
+	case 2:
+		ret = (data >> ((where & 3) << 3)) & 0xffff;
+		break;
+	case 4:
+		ret = data;
+		break;
+	}
+
+	return ret;
+}
+
+static int preprocess_write(u32 orig_data, u32 val, int where,
+			    unsigned int size)
+{
+	u32 ret = 0;
+
+	switch (size) {
+	case 1:
+		ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
+		      (val << ((where & 3) << 3));
+		break;
+	case 2:
+		ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
+		      (val << ((where & 3) << 3));
+		break;
+	case 4:
+		ret = val;
+		break;
+	}
+
+	return ret;
+}
+
+static int bcm6328_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+	struct bcm6328_pcie *priv = &bcm6328_pcie;
+
+	switch (bus->number) {
+	case PCIE_BUS_BRIDGE:
+		return PCI_SLOT(devfn) == 0;
+	case PCIE_BUS_DEVICE:
+		if (PCI_SLOT(devfn) == 0)
+			return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
+			       & DLSTATUS_PHYLINKUP;
+		fallthrough;
+	default:
+		return false;
+	}
+}
+
+static int bcm6328_pcie_read(struct pci_bus *bus, unsigned int devfn,
+			     int where, int size, u32 *val)
+{
+	struct bcm6328_pcie *priv = &bcm6328_pcie;
+	u32 data;
+	u32 reg = where & ~3;
+
+	if (!bcm6328_pcie_can_access(bus, devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (bus->number == PCIE_BUS_DEVICE)
+		reg += PCIE_DEVICE_OFFSET;
+
+	data = __raw_readl(priv->base + reg);
+	*val = postprocess_read(data, where, size);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int bcm6328_pcie_write(struct pci_bus *bus, unsigned int devfn,
+			      int where, int size, u32 val)
+{
+	struct bcm6328_pcie *priv = &bcm6328_pcie;
+	u32 data;
+	u32 reg = where & ~3;
+
+	if (!bcm6328_pcie_can_access(bus, devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (bus->number == PCIE_BUS_DEVICE)
+		reg += PCIE_DEVICE_OFFSET;
+
+	data = __raw_readl(priv->base + reg);
+	data = preprocess_write(data, val, where, size);
+	__raw_writel(data, priv->base + reg);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops bcm6328_pcie_ops = {
+	.read = bcm6328_pcie_read,
+	.write = bcm6328_pcie_write,
+};
+
+static struct resource bcm6328_pcie_io_resource;
+static struct resource bcm6328_pcie_mem_resource;
+static struct resource bcm6328_pcie_busn_resource;
+
+static struct pci_controller bcm6328_pcie_controller = {
+	.pci_ops = &bcm6328_pcie_ops,
+	.io_resource = &bcm6328_pcie_io_resource,
+	.mem_resource = &bcm6328_pcie_mem_resource,
+};
+
+static void bcm6328_pcie_reset(struct bcm6328_pcie *priv)
+{
+	regmap_write_bits(priv->serdes, 0,
+			  SERDES_PCIE_EXD_EN | SERDES_PCIE_EN,
+			  SERDES_PCIE_EXD_EN | SERDES_PCIE_EN);
+
+	reset_control_assert(priv->reset);
+	reset_control_assert(priv->reset_core);
+	reset_control_assert(priv->reset_ext);
+	if (priv->reset_hard) {
+		reset_control_assert(priv->reset_hard);
+		mdelay(10);
+		reset_control_deassert(priv->reset_hard);
+	}
+	mdelay(10);
+
+	reset_control_deassert(priv->reset_core);
+	reset_control_deassert(priv->reset);
+	mdelay(10);
+
+	reset_control_deassert(priv->reset_ext);
+	mdelay(200);
+}
+
+static void bcm6328_pcie_setup(struct bcm6328_pcie *priv)
+{
+	u32 val;
+
+	val = __raw_readl(priv->base + PCIE_BRIDGE_OPT1_REG);
+	val |= OPT1_RD_BE_OPT_EN;
+	val |= OPT1_RD_REPLY_BE_FIX_EN;
+	val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
+	val |= OPT1_L1_INT_STATUS_MASK_POL;
+	__raw_writel(val, priv->base + PCIE_BRIDGE_OPT1_REG);
+
+	val = __raw_readl(priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);
+	val |= PCIE_RC_INT_A;
+	val |= PCIE_RC_INT_B;
+	val |= PCIE_RC_INT_C;
+	val |= PCIE_RC_INT_D;
+	__raw_writel(val, priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);
+
+	val = __raw_readl(priv->base + PCIE_BRIDGE_OPT2_REG);
+	/* enable credit checking and error checking */
+	val |= OPT2_TX_CREDIT_CHK_EN;
+	val |= OPT2_UBUS_UR_DECODE_DIS;
+	/* set device bus/func for the pcie device */
+	val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
+	val |= OPT2_CFG_TYPE1_BD_SEL;
+	__raw_writel(val, priv->base + PCIE_BRIDGE_OPT2_REG);
+
+	/* setup class code as bridge */
+	val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
+	val &= ~IDVAL3_CLASS_CODE_MASK;
+	val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+	__raw_writel(val, priv->base + PCIE_IDVAL3_REG);
+
+	/* disable bar1 size */
+	val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
+	val &= ~CONFIG2_BAR1_SIZE_MASK;
+	__raw_writel(val, priv->base + PCIE_CONFIG2_REG);
+
+	/* set bar0 to little endian */
+	val = (bcm6328_pcie_mem_resource.start >> 20)
+	      << BASEMASK_BASE_SHIFT;
+	val |= (bcm6328_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+	val |= BASEMASK_REMAP_EN;
+	__raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_BASEMASK_REG);
+
+	val = (bcm6328_pcie_mem_resource.start >> 20)
+	      << REBASE_ADDR_BASE_SHIFT;
+	__raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+}
+
+static int bcm6328_pcie_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct bcm6328_pcie *priv = &bcm6328_pcie;
+	struct resource *res;
+	unsigned int i;
+	int ret;
+	LIST_HEAD(resources);
+
+	pm_runtime_enable(dev);
+	pm_runtime_no_callbacks(dev);
+
+	priv->num_pms = of_count_phandle_with_args(np, "power-domains",
+						   "#power-domain-cells");
+	if (priv->num_pms > 1) {
+		priv->pm = devm_kcalloc(dev, priv->num_pms,
+					sizeof(struct device *), GFP_KERNEL);
+		if (!priv->pm)
+			return -ENOMEM;
+
+		priv->link_pm = devm_kcalloc(dev, priv->num_pms,
+					     sizeof(struct device_link *),
+					     GFP_KERNEL);
+		if (!priv->link_pm)
+			return -ENOMEM;
+
+		for (i = 0; i < priv->num_pms; i++) {
+			priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
+			if (IS_ERR(priv->pm[i])) {
+				dev_err(dev, "error getting pm %d\n", i);
+				return -EINVAL;
+			}
+
+			priv->link_pm[i] = device_link_add(dev, priv->pm[i],
+				DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
+				DL_FLAG_RPM_ACTIVE);
+		}
+	}
+
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0) {
+		pm_runtime_disable(dev);
+		dev_info(dev, "PM prober defer: ret=%d\n", ret);
+		return -EPROBE_DEFER;
+	}
+
+	of_pci_check_probe_only();
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (!priv->irq)
+		return -ENODEV;
+
+	bmips_pci_irq = priv->irq;
+
+	priv->serdes = syscon_regmap_lookup_by_phandle(np, "brcm,serdes");
+	if (IS_ERR(priv->serdes))
+		return PTR_ERR(priv->serdes);
+
+	priv->reset = devm_reset_control_get(dev, "pcie");
+	if (IS_ERR(priv->reset))
+		return PTR_ERR(priv->reset);
+
+	priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
+	if (IS_ERR(priv->reset_ext))
+		return PTR_ERR(priv->reset_ext);
+
+	priv->reset_core = devm_reset_control_get(dev, "pcie-core");
+	if (IS_ERR(priv->reset_core))
+		return PTR_ERR(priv->reset_core);
+
+	priv->reset_hard = devm_reset_control_get_optional(dev, "pcie-hard");
+	if (IS_ERR(priv->reset_hard))
+		return PTR_ERR(priv->reset_hard);
+
+	priv->clk = devm_clk_get(dev, "pcie");
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "could not enable clock\n");
+		return ret;
+	}
+
+	pci_load_of_ranges(&bcm6328_pcie_controller, np);
+	if (!bcm6328_pcie_mem_resource.start)
+		return -EINVAL;
+
+	of_pci_parse_bus_range(np, &bcm6328_pcie_busn_resource);
+	pci_add_resource(&resources, &bcm6328_pcie_busn_resource);
+
+	bcm6328_pcie_reset(priv);
+	bcm6328_pcie_setup(priv);
+
+	register_pci_controller(&bcm6328_pcie_controller);
+
+	return 0;
+}
+
+static const struct of_device_id bcm6328_pcie_of_match[] = {
+	{ .compatible = "brcm,bcm6328-pcie", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, bcm6328_pcie_of_match);
+
+static struct platform_driver bcm6328_pcie_driver = {
+	.probe = bcm6328_pcie_probe,
+	.driver	= {
+		.name = "bcm6328-pcie",
+		.of_match_table = bcm6328_pcie_of_match,
+	},
+};
+module_platform_driver(bcm6328_pcie_driver);
+
+MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
+MODULE_DESCRIPTION("BCM6328 PCIe Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:bcm6328-pcie");

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H
+
+#define BCM6318_IRQ_TIMER0		0
+#define BCM6318_IRQ_TIMER1		1
+#define BCM6318_IRQ_TIMER2		2
+#define BCM6318_IRQ_TIMER3		3
+#define BCM6318_IRQ_USBS		4
+#define BCM6318_IRQ_USB_CTL_RX_DMA	5
+#define BCM6318_IRQ_USB_CTL_TX_DMA	6
+#define BCM6318_IRQ_USB_BULK_RX_DMA	7
+#define BCM6318_IRQ_USB_BULK_TX_DMA	8
+#define BCM6318_IRQ_USB_ISO_RX_DMA	9
+#define BCM6318_IRQ_USB_ISO_TX_DMA	10
+#define BCM6318_IRQ_DG			11
+#define BCM6318_IRQ_EPHY		12
+#define BCM6318_IRQ_EPHY_EN0N		13
+#define BCM6318_IRQ_EPHY_EN1N		14
+#define BCM6318_IRQ_EPHY_EN2N		15
+#define BCM6318_IRQ_EPHY_EN3N		16
+#define BCM6318_IRQ_EPHY_EN0		17
+#define BCM6318_IRQ_EPHY_EN1		18
+#define BCM6318_IRQ_EPHY_EN2		19
+#define BCM6318_IRQ_EPHY_EN3		20
+#define BCM6318_IRQ_XDSL		21
+#define BCM6318_IRQ_SDR			22
+#define BCM6318_IRQ_PCIE_RC		23
+#define BCM6318_IRQ_EXT0		24
+#define BCM6318_IRQ_EXT1		25
+#define BCM6318_IRQ_EXT2		26
+#define BCM6318_IRQ_EXT3		27
+#define BCM6318_IRQ_UART0		28
+#define BCM6318_IRQ_HSSPI		29
+#define BCM6318_IRQ_WAKE_ON_IRQ		30
+#define BCM6318_IRQ_TIMER		31
+#define BCM6318_IRQ_ENETSW_RX_DMA0	32
+#define BCM6318_IRQ_ENETSW_RX_DMA1	33
+#define BCM6318_IRQ_ENETSW_RX_DMA2	34
+#define BCM6318_IRQ_ENETSW_RX_DMA3	35
+#define BCM6318_IRQ_WDTIMER		37
+#define BCM6318_IRQ_ENETSW		40
+#define BCM6318_IRQ_OHCI		41
+#define BCM6318_IRQ_EHCI		42
+#define BCM6318_IRQ_ATM_DMA0		43
+#define BCM6318_IRQ_ATM_DMA1		44
+#define BCM6318_IRQ_ATM_DMA2		45
+#define BCM6318_IRQ_ATM_DMA3		46
+#define BCM6318_IRQ_ATM_DMA4		47
+#define BCM6318_IRQ_ATM_DMA5		48
+#define BCM6318_IRQ_ATM_DMA6		49
+#define BCM6318_IRQ_ATM_DMA7		50
+#define BCM6318_IRQ_ATM_DMA8		51
+#define BCM6318_IRQ_ATM_DMA9		52
+#define BCM6318_IRQ_ATM_DMA10		53
+#define BCM6318_IRQ_ATM_DMA11		54
+#define BCM6318_IRQ_ATM_DMA12		55
+#define BCM6318_IRQ_ATM_DMA13		56
+#define BCM6318_IRQ_ATM_DMA14		57
+#define BCM6318_IRQ_ATM_DMA15		58
+#define BCM6318_IRQ_ATM_DMA16		59
+#define BCM6318_IRQ_ATM_DMA17		60
+#define BCM6318_IRQ_ATM_DMA18		61
+#define BCM6318_IRQ_ATM_DMA19		62
+#define BCM6318_IRQ_SAR			63
+#define BCM6318_IRQ_ADSL_ENERGY		64
+#define BCM6318_IRQ_ADSL_ENERGY_N	65
+#define BCM6318_IRQ_USB_ENERGY_ON	66
+#define BCM6318_IRQ_USB_ENERGY_OFF	67
+#define BCM6318_IRQ_PVTMON_TEMP		68
+#define BCM6318_IRQ_SYSPLL_LOCK		69
+#define BCM6318_IRQ_LCPLL_LOCK		70
+#define BCM6318_IRQ_PMU_STABLE		71
+#define BCM6318_IRQ_ENETSW_TX_DMA0	72
+#define BCM6318_IRQ_ENETSW_TX_DMA1	73
+#define BCM6318_IRQ_ENETSW_TX_DMA2	74
+#define BCM6318_IRQ_ENETSW_TX_DMA3	75
+#define BCM6318_IRQ_EPHY0_IDDQ_ENERGY	76
+#define BCM6318_IRQ_EPHY1_IDDQ_ENERGY	77
+#define BCM6318_IRQ_EPHY2_IDDQ_ENERGY	78
+#define BCM6318_IRQ_EPHY3_IDDQ_ENERGY	79
+
+#define BCM6318_EXTIRQ_0		0 /* GPIO 33 */
+#define BCM6318_EXTIRQ_1		1
+#define BCM6318_EXTIRQ_2		2
+#define BCM6318_EXTIRQ_3		3
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H */

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
+
+#define BCM63268_IRQ_TIMER		0
+#define BCM63268_IRQ_ENETSW_RX_DMA0	1
+#define BCM63268_IRQ_ENETSW_RX_DMA1	2
+#define BCM63268_IRQ_ENETSW_RX_DMA2	3
+#define BCM63268_IRQ_ENETSW_RX_DMA3	4
+#define BCM63268_IRQ_UART0		5
+#define BCM63268_IRQ_HSSPI		6
+#define BCM63268_IRQ_WLAN		7
+#define BCM63268_IRQ_IPSEC		8
+#define BCM63268_IRQ_OHCI		9
+#define BCM63268_IRQ_EHCI		10
+#define BCM63268_IRQ_USBS		11
+#define BCM63268_IRQ_PCM		12
+#define BCM63268_IRQ_EPHY		13
+#define BCM63268_IRQ_DG			14
+#define BCM63268_IRQ_EPHY0_EN		15
+#define BCM63268_IRQ_EPHY1_EN		16
+#define BCM63268_IRQ_EPHY2_EN		17
+#define BCM63268_IRQ_GPHY_EN		18
+#define BCM63268_IRQ_USB_CTL_RX_DMA	19
+#define BCM63268_IRQ_USB_BULK_RX_DMA	20
+#define BCM63268_IRQ_ISO_RX_DMA		21
+#define BCM63268_IRQ_IPSEC_DMA0		22
+#define BCM63268_IRQ_XDSL		23
+#define BCM63268_IRQ_FAP0		24
+#define BCM63268_IRQ_FAP1		25
+#define BCM63268_IRQ_ATM_DMA0		26
+#define BCM63268_IRQ_ATM_DMA1		27
+#define BCM63268_IRQ_ATM_DMA2		28
+#define BCM63268_IRQ_ATM_DMA3		29
+#define BCM63268_IRQ_WAKE_ON_IRQ	30
+#define BCM63268_IRQ_GPHY		31
+#define BCM63268_IRQ_DECT0              32
+#define BCM63268_IRQ_DECT1		33
+#define BCM63268_IRQ_UART1              34
+#define BCM63268_IRQ_WLAN_GPIO		35
+#define BCM63268_IRQ_USB_CTL_TX_DMA	36
+#define BCM63268_IRQ_USB_BULK_TX_DMA	37
+#define BCM63268_IRQ_ISO_TX_DMA		38
+#define BCM63268_IRQ_IPSEC_DMA1		39
+#define BCM63268_IRQ_PCIE_RC		40
+#define BCM63268_IRQ_PCIE_EP		41
+#define BCM63268_IRQ_PCM_DMA0		42
+#define BCM63268_IRQ_PCM_DMA1		43
+#define BCM63268_IRQ_EXT0		44
+#define BCM63268_IRQ_EXT1		45
+#define BCM63268_IRQ_EXT2		46
+#define BCM63268_IRQ_EXT3		47
+#define BCM63268_IRQ_ENETSW		48
+#define BCM63268_IRQ_SAR		49
+#define BCM63268_IRQ_NAND		50
+#define BCM63268_IRQ_RING_OSC		52
+#define BCM63268_IRQ_USB_CONNECT	53
+#define BCM63268_IRQ_USB_DISCONNECT	54
+#define BCM63268_IRQ_PER_MBOX0		55
+#define BCM63268_IRQ_PER_MBOX1		56
+#define BCM63268_IRQ_PER_MBOX2		57
+#define BCM63268_IRQ_PER_MBOX3		58
+#define BCM63268_IRQ_ATM_DMA4		59
+#define BCM63268_IRQ_ATM_DMA5		60
+#define BCM63268_IRQ_ATM_DMA6		61
+#define BCM63268_IRQ_ATM_DMA7		62
+#define BCM63268_IRQ_ENETSW_TX_DMA0	64
+#define BCM63268_IRQ_ENETSW_TX_DMA1	65
+#define BCM63268_IRQ_ENETSW_TX_DMA2	66
+#define BCM63268_IRQ_ENETSW_TX_DMA3	67
+#define BCM63268_IRQ_ATM_DMA8		68
+#define BCM63268_IRQ_ATM_DMA9		69
+#define BCM63268_IRQ_ATM_DMA10		70
+#define BCM63268_IRQ_ATM_DMA11		71
+#define BCM63268_IRQ_ATM_DMA12		72
+#define BCM63268_IRQ_ATM_DMA13		73
+#define BCM63268_IRQ_ATM_DMA14		74
+#define BCM63268_IRQ_ATM_DMA15		75
+#define BCM63268_IRQ_ATM_DMA16		76
+#define BCM63268_IRQ_ATM_DMA17		77
+#define BCM63268_IRQ_ATM_DMA18		78
+#define BCM63268_IRQ_ATM_DMA19		79
+#define BCM63268_IRQ_LSSPI		80
+
+#define BCM63268_EXTIRQ_0		0 /* GPIO 32 */
+#define BCM63268_EXTIRQ_1		1 /* GPIO 33 */
+#define BCM63268_EXTIRQ_2		2 /* GPIO 34 */
+#define BCM63268_EXTIRQ_3		3 /* GPIO 35 */
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H */

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h

@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
+
+#define BCM6328_IRQ_NAND		0
+#define BCM6328_IRQ_PCM			1
+#define BCM6328_IRQ_PCM_DMA0		2
+#define BCM6328_IRQ_PCM_DMA1		3
+#define BCM6328_IRQ_USBS		4
+#define BCM6328_IRQ_USB_CTL_RX_DMA	5
+#define BCM6328_IRQ_USB_CTL_TX_DMA	6
+#define BCM6328_IRQ_USB_BULK_RX_DMA	7
+#define BCM6328_IRQ_USB_BULK_TX_DMA	8
+#define BCM6328_IRQ_USB_ISO_RX_DMA	9
+#define BCM6328_IRQ_USB_ISO_TX_DMA	10
+#define BCM6328_IRQ_DG			11
+#define BCM6328_IRQ_EPHY		12
+#define BCM6328_IRQ_EPHY_EN0N		13
+#define BCM6328_IRQ_EPHY_EN1N		14
+#define BCM6328_IRQ_EPHY_EN2N		15
+#define BCM6328_IRQ_EPHY_EN3N		16
+#define BCM6328_IRQ_EPHY_EN0		17
+#define BCM6328_IRQ_EPHY_EN1		18
+#define BCM6328_IRQ_EPHY_EN2		19
+#define BCM6328_IRQ_EPHY_EN3		20
+#define BCM6328_IRQ_XDSL		21
+#define BCM6328_IRQ_PCIE_EP		22
+#define BCM6328_IRQ_PCIE_RC		23
+#define BCM6328_IRQ_EXTO		24
+#define BCM6328_IRQ_EXT1		25
+#define BCM6328_IRQ_EXT2		26
+#define BCM6328_IRQ_EXT3		27
+#define BCM6328_IRQ_UART0		28
+#define BCM6328_IRQ_HSSPI		29
+#define BCM6328_IRQ_WAKE_ON_IRQ		30
+#define BCM6328_IRQ_TIMER		31
+#define BCM6328_IRQ_ENETSW_RX_DMA0	32
+#define BCM6328_IRQ_ENETSW_RX_DMA1	33
+#define BCM6328_IRQ_ENETSW_TX_DMA0	34
+#define BCM6328_IRQ_ENETSW_TX_DMA1	35
+#define BCM6328_IRQ_UART1		39
+#define BCM6328_IRQ_ENETSW		40
+#define BCM6328_IRQ_OHCI		41
+#define BCM6328_IRQ_EHCI		42
+#define BCM6328_IRQ_ATM_DMA0		43
+#define BCM6328_IRQ_ATM_DMA1		44
+#define BCM6328_IRQ_ATM_DMA2		45
+#define BCM6328_IRQ_ATM_DMA3		46
+#define BCM6328_IRQ_ATM_DMA4		47
+#define BCM6328_IRQ_ATM_DMA5		48
+#define BCM6328_IRQ_ATM_DMA6		49
+#define BCM6328_IRQ_ATM_DMA7		50
+#define BCM6328_IRQ_ATM_DMA8		51
+#define BCM6328_IRQ_ATM_DMA9		52
+#define BCM6328_IRQ_ATM_DMA10		53
+#define BCM6328_IRQ_ATM_DMA11		54
+#define BCM6328_IRQ_ATM_DMA12		55
+#define BCM6328_IRQ_ATM_DMA13		56
+#define BCM6328_IRQ_ATM_DMA14		57
+#define BCM6328_IRQ_ATM_DMA15		58
+#define BCM6328_IRQ_ATM_DMA16		59
+#define BCM6328_IRQ_ATM_DMA17		60
+#define BCM6328_IRQ_ATM_DMA18		61
+#define BCM6328_IRQ_ATM_DMA19		62
+#define BCM6328_IRQ_SAR			63
+
+#define BCM6328_EXTIRQ_0		0 /* GPIO 23 */
+#define BCM6328_EXTIRQ_1		1 /* GPIO 24 */
+#define BCM6328_EXTIRQ_2		2 /* GPIO 15 */
+#define BCM6328_EXTIRQ_3		3 /* GPIO 12 */
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H */

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6358-interrupt-controller.h

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H
+
+#define BCM6358_IRQ_TIMER		0
+#define BCM6358_IRQ_SPI			1
+#define BCM6358_IRQ_UART0		2
+#define BCM6358_IRQ_UART1		3
+#define BCM6358_IRQ_OHCI		5
+#define BCM6358_IRQ_EMAC1		6
+#define BCM6358_IRQ_USBS		7
+#define BCM6358_IRQ_EMAC0		8
+#define BCM6358_IRQ_EPHY		9
+#define BCM6358_IRQ_EHCI		10
+#define BCM6358_IRQ_USB_CTL_RX_DMA	11
+#define BCM6358_IRQ_USB_CTL_TX_DMA	12
+#define BCM6358_IRQ_USB_BULK_RX_DMA	13
+#define BCM6358_IRQ_USB_BULK_TX_DMA	14
+#define BCM6358_IRQ_EMAC0_RX_DMA	15
+#define BCM6358_IRQ_EMAC0_TX_DMA	16
+#define BCM6358_IRQ_EMAC1_RX_DMA	17
+#define BCM6358_IRQ_EMAC1_TX_DMA	18
+#define BCM6358_IRQ_ATM		        19
+#define BCM6358_IRQ_EXT4		20
+#define BCM6358_IRQ_EXT5		21
+#define BCM6358_IRQ_PCM			22
+#define BCM6358_IRQ_PCM_RX_DMA		23
+#define BCM6358_IRQ_PCM_TX_DMA		24
+#define BCM6358_IRQ_EXT0		25
+#define BCM6358_IRQ_EXT1		26
+#define BCM6358_IRQ_EXT2		27
+#define BCM6358_IRQ_EXT3		28
+#define BCM6358_IRQ_ADSL		29
+#define BCM6358_IRQ_DG			30
+#define BCM6358_IRQ_MPI			31
+
+#define BCM6358_EXTIRQ0_0		0 /* GPIO 34 */
+#define BCM6358_EXTIRQ0_1		1 /* GPIO 35 */
+#define BCM6358_EXTIRQ0_2		2 /* GPIO 36 */
+#define BCM6358_EXTIRQ0_3		3 /* GPIO 37 */
+#define BCM6358_EXTIRQ1_4		0 /* GPIO 32 */
+#define BCM6358_EXTIRQ1_5		1 /* GPIO 33 */
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H */

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h

@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H
+
+#define BCM6362_IRQ_TIMER		0
+#define BCM6362_IRQ_RING_OSC		1
+#define BCM6362_IRQ_LSSPI		2
+#define BCM6362_IRQ_UART0		3
+#define BCM6362_IRQ_UART1		4
+#define BCM6362_IRQ_HSSPI		5
+#define BCM6362_IRQ_WLAN_GPIO		6
+#define BCM6362_IRQ_WLAN		7
+#define BCM6362_IRQ_IPSEC		8
+#define BCM6362_IRQ_OHCI		9
+#define BCM6362_IRQ_EHCI		10
+#define BCM6362_IRQ_USBS		11
+#define BCM6362_IRQ_NAND		12
+#define BCM6362_IRQ_PCM			13
+#define BCM6362_IRQ_EPHY		14
+#define BCM6362_IRQ_DF			15
+#define BCM6362_IRQ_EPHY_EN0		16
+#define BCM6362_IRQ_EPHY_EN1		17
+#define BCM6362_IRQ_EPHY_EN2		18
+#define BCM6362_IRQ_EPHY_EN3		19
+#define BCM6362_IRQ_USB_CTL_RX_DMA	20
+#define BCM6362_IRQ_USB_CTL_TX_DMA	21
+#define BCM6362_IRQ_USB_BULK_RX_DMA	22
+#define BCM6362_IRQ_USB_BULK_TX_DMA	23
+#define BCM6362_IRQ_USB_ISO_RX_DMA	24
+#define BCM6362_IRQ_USB_ISO_TX_DMA	25
+#define BCM6362_IRQ_IPSEC_DMA0		26
+#define BCM6362_IRQ_IPSEC_DMA1		27
+#define BCM6362_IRQ_XDSL		28
+#define BCM6362_IRQ_FAP			29
+#define BCM6362_IRQ_PCIE_RC		30
+#define BCM6362_IRQ_PCIE_EP		31
+#define BCM6362_IRQ_ENETSW_RX_DMA0	32
+#define BCM6362_IRQ_ENETSW_RX_DMA1	33
+#define BCM6362_IRQ_ENETSW_RX_DMA2	34
+#define BCM6362_IRQ_ENETSW_RX_DMA3	35
+#define BCM6362_IRQ_PCM_DMA0		36
+#define BCM6362_IRQ_PCM_DMA1		37
+#define BCM6362_IRQ_DECT0		38
+#define BCM6362_IRQ_DECT1		39
+#define BCM6362_IRQ_EXT0		40
+#define BCM6362_IRQ_EXT1		41
+#define BCM6362_IRQ_EXT2		42
+#define BCM6362_IRQ_EXT3		43
+#define BCM6362_IRQ_ATM_DMA0		44
+#define BCM6362_IRQ_ATM_DMA1		45
+#define BCM6362_IRQ_ATM_DMA2		46
+#define BCM6362_IRQ_ATM_DMA3		47
+#define BCM6362_IRQ_ATM_DMA4		48
+#define BCM6362_IRQ_ATM_DMA5		49
+#define BCM6362_IRQ_ATM_DMA6		50
+#define BCM6362_IRQ_ATM_DMA7		51
+#define BCM6362_IRQ_ATM_DMA8		52
+#define BCM6362_IRQ_ATM_DMA9		53
+#define BCM6362_IRQ_ATM_DMA10		54
+#define BCM6362_IRQ_ATM_DMA11		55
+#define BCM6362_IRQ_ATM_DMA12		56
+#define BCM6362_IRQ_ATM_DMA13		57
+#define BCM6362_IRQ_ATM_DMA14		58
+#define BCM6362_IRQ_ATM_DMA15		59
+#define BCM6362_IRQ_ATM_DMA16		60
+#define BCM6362_IRQ_ATM_DMA17		61
+#define BCM6362_IRQ_ATM_DMA18		62
+#define BCM6362_IRQ_ATM_DMA19		63
+
+#define BCM6362_EXTIRQ_0		0 /* GPIO 24 */
+#define BCM6362_EXTIRQ_1		1 /* GPIO 25 */
+#define BCM6362_EXTIRQ_2		2 /* GPIO 26 */
+#define BCM6362_EXTIRQ_3		3 /* GPIO 27 */
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H */

target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
+
+#define BCM6368_IRQ_TIMER		0
+#define BCM6368_IRQ_SPI			1
+#define BCM6368_IRQ_UART0		2
+#define BCM6368_IRQ_UART1		3
+#define BCM6368_IRQ_XDSL		4
+#define BCM6368_IRQ_OHCI		5
+#define BCM6368_IRQ_IPSEC		6
+#define BCM6368_IRQ_EHCI		7
+#define BCM6368_IRQ_USBS		8
+#define BCM6368_IRQ_RING_OSC		9
+#define BCM6368_IRQ_NAND		10
+#define BCM6368_IRQ_ATM			11
+#define BCM6368_IRQ_PCM			12
+#define BCM6368_IRQ_MPI			13
+#define BCM6368_IRQ_DG			14
+#define BCM6368_IRQ_EPHY		15
+#define BCM6368_IRQ_EPHY_EN0		16
+#define BCM6368_IRQ_EPHY_EN1		17
+#define BCM6368_IRQ_EPHY_EN2		18
+#define BCM6368_IRQ_EPHY_EN3		19
+#define BCM6368_IRQ_EXT0		20
+#define BCM6368_IRQ_EXT1		21
+#define BCM6368_IRQ_EXT2		22
+#define BCM6368_IRQ_EXT3		23
+#define BCM6368_IRQ_EXT4		24
+#define BCM6368_IRQ_EXT5		25
+#define BCM6368_IRQ_USB_CTL_RX_DMA	26
+#define BCM6368_IRQ_USB_CTL_TX_DMA	27
+#define BCM6368_IRQ_USB_BULK_RX_DMA	28
+#define BCM6368_IRQ_USB_BULK_TX_DMA	29
+#define BCM6368_IRQ_USB_ISO_RX_DMA	30
+#define BCM6368_IRQ_USB_ISO_TX_DMA	31
+#define BCM6368_IRQ_ENETSW_RX_DMA0	32
+#define BCM6368_IRQ_ENETSW_RX_DMA1	33
+#define BCM6368_IRQ_ENETSW_RX_DMA2	34
+#define BCM6368_IRQ_ENETSW_RX_DMA3	35
+#define BCM6368_IRQ_ENETSW_TX_DMA0	36
+#define BCM6368_IRQ_ENETSW_TX_DMA1	37
+#define BCM6368_IRQ_ENETSW_TX_DMA2	38
+#define BCM6368_IRQ_ENETSW_TX_DMA3	39
+#define BCM6368_IRQ_ATM_DMA0		40
+#define BCM6368_IRQ_ATM_DMA1		41
+#define BCM6368_IRQ_ATM_DMA2		42
+#define BCM6368_IRQ_ATM_DMA3		43
+#define BCM6368_IRQ_ATM_DMA4		44
+#define BCM6368_IRQ_ATM_DMA5		45
+#define BCM6368_IRQ_ATM_DMA6		46
+#define BCM6368_IRQ_ATM_DMA7		47
+#define BCM6368_IRQ_ATM_DMA8		48
+#define BCM6368_IRQ_ATM_DMA9		49
+#define BCM6368_IRQ_ATM_DMA10		50
+#define BCM6368_IRQ_ATM_DMA11		51
+#define BCM6368_IRQ_ATM_DMA12		52
+#define BCM6368_IRQ_ATM_DMA13		53
+#define BCM6368_IRQ_ATM_DMA14		54
+#define BCM6368_IRQ_ATM_DMA15		55
+#define BCM6368_IRQ_ATM_DMA16		56
+#define BCM6368_IRQ_ATM_DMA17		57
+#define BCM6368_IRQ_ATM_DMA18		58
+#define BCM6368_IRQ_ATM_DMA19		59
+#define BCM6368_IRQ_IPSEC_DMA0		60
+#define BCM6368_IRQ_IPSEC_DMA1		61
+#define BCM6368_IRQ_PCM_DMA0		62
+#define BCM6368_IRQ_PCM_DMA1		63
+
+#define BCM6368_EXTIRQ0_0		0 /* GPIO 34 */
+#define BCM6368_EXTIRQ0_1		1 /* GPIO 35 */
+#define BCM6368_EXTIRQ0_2		2 /* GPIO 36 */
+#define BCM6368_EXTIRQ0_3		3 /* GPIO 37 */
+#define BCM6368_EXTIRQ1_4		0 /* GPIO 32 */
+#define BCM6368_EXTIRQ1_5		1 /* GPIO 33 */
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H */

target/linux/bmips/image/Makefile

@@ -0,0 +1,374 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+KERNEL_LOADADDR := 0x80010000		# RAM start + 64K
+UBOOT_ENTRY := 0x81c00000
+LOADER_ENTRY := 0x81000000		# RAM start + 16M, for relocate
+LZMA_TEXT_START := 0x82000000		# RAM start + 32M
+
+DEVICE_VARS += CFE_BOARD_ID CFE_EXTRAS
+DEVICE_VARS += CFE_PART_FLAGS CFE_PART_ID
+DEVICE_VARS += CFE_RAM_FILE
+DEVICE_VARS += CFE_RAM_JFFS2_NAME CFE_RAM_JFFS2_PAD
+DEVICE_VARS += CFE_WFI_CHIP_ID CFE_WFI_FLASH_TYPE
+DEVICE_VARS += CFE_WFI_FLAGS CFE_WFI_VERSION
+DEVICE_VARS += CHIP_ID DEVICE_LOADADDR
+DEVICE_VARS += FLASH_MB IMAGE_OFFSET
+DEVICE_VARS += SERCOMM_FSVER SERCOMM_HWVER SERCOMM_SWVER
+
+define Build/Compile
+	rm -rf $(KDIR)/relocate
+	$(CP) ../../generic/image/relocate $(KDIR)
+	$(MAKE) -C $(KDIR)/relocate \
+		CACHELINE_SIZE=16 \
+		CROSS_COMPILE=$(TARGET_CROSS) \
+		KERNEL_ADDR=$(KERNEL_LOADADDR) \
+		LZMA_TEXT_START=$(LOADER_ENTRY)
+endef
+
+### Kernel scripts ###
+define Build/loader-lzma
+	@rm -rf $@.src
+	$(MAKE) -C lzma-loader \
+		CHIP_ID=$(CHIP_ID) \
+		KERNEL_ADDR=$(KERNEL_LOADADDR) \
+		KDIR=$(KDIR) \
+		LOADER_ADDR=$(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \
+		LOADER_DATA="$@" \
+		LOADER_NAME="$(notdir $@)" \
+		LZMA_TEXT_START=$(LZMA_TEXT_START) \
+		PKG_BUILD_DIR="$@.src" \
+		TARGET_DIR="$(dir $@)" \
+		compile loader.$(1)
+	@mv "$@.$(1)" "$@"
+	@rm -rf $@.src
+endef
+
+define Build/lzma-cfe
+	# CFE is a LZMA nazi! It took me hours to find out the parameters!
+	# Also I think lzma has a bug cause it generates different output depending on
+	# if you use stdin / stdout or not. Use files instead of stdio here, cause
+	# otherwise CFE will complain and not boot the image.
+	$(call Build/lzma-no-dict,-d22 -fb64 -a1)
+	# Strip out the length, CFE doesn't like this
+	dd if=$@ of=$@.new bs=5 count=1
+	dd if=$@ of=$@.new ibs=13 obs=5 skip=1 seek=1 conv=notrunc
+	@mv $@.new $@
+endef
+
+define Build/relocate-kernel
+	# CFE only allows ~4 MiB for the uncompressed kernels, but uncompressed
+	# kernel might get larger than that, so let CFE unpack and load at a
+	# higher address and make the kernel relocate itself to the expected
+	# location.
+	( \
+		dd if=$(KDIR)/relocate/loader.bin bs=32 conv=sync && \
+		perl -e '@s = stat("$@"); print pack("N", @s[7])' && \
+		cat $@ \
+	) > $@.relocate
+	@mv $@.relocate $@
+endef
+
+### Image scripts ###
+define rootfspad/jffs2-128k
+--align-rootfs
+endef
+define rootfspad/jffs2-64k
+--align-rootfs
+endef
+define rootfspad/squashfs
+endef
+
+define Image/FileSystemStrip
+$(firstword $(subst +,$(space),$(subst root.,,$(notdir $(1)))))
+endef
+
+define Build/cfe-bin
+	$(STAGING_DIR_HOST)/bin/imagetag -i $(IMAGE_KERNEL) -f $(IMAGE_ROOTFS) \
+		--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \
+		--entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \
+		--info1 "$(call ModelNameLimit16,$(DEVICE_NAME))" \
+		--info2 "$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))" \
+		$(call rootfspad/$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))) \
+		$(CFE_EXTRAS) $(1)
+endef
+
+# Build a CFE image with just U-Boot
+define Build/cfe-bin-uboot
+	cp $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.bin $@
+	$(call Build/lzma)
+	mv $@ $@.uboot.lzma
+	echo "dummy" > $@.dummyfs
+	$(STAGING_DIR_HOST)/bin/imagetag -i $@.uboot.lzma -f $@.dummyfs \
+		--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \
+		--entry $(UBOOT_ENTRY) --load-addr $(UBOOT_ENTRY) \
+		--info1 "$(call ModelNameLimit16,$(DEVICE_NAME))" \
+		$(CFE_EXTRAS) $(1)
+	rm $@.uboot.lzma
+	rm $@.dummyfs
+endef
+
+define Build/cfe-jffs2
+	$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
+		--big-endian \
+		--pad \
+		--no-cleanmarkers \
+		--eraseblock=$(patsubst %k,%KiB,$(BLOCKSIZE)) \
+		--root=$(1) \
+		--output=$@ \
+		--compression-mode=none
+
+	$(call Build/pad-to,$(BLOCKSIZE))
+endef
+
+define Build/cfe-jffs2-cferam
+	mv $@ $@.kernel
+
+	rm -rf $@-cferam
+	mkdir -p $@-cferam
+
+	# CFE ROM checks JFFS2 dirent version of cferam.
+	# If version is not > 0 it will ignore the fs entry.
+	# JFFS2 sets version 0 to the first fs entry and increments
+	# it on the following ones, so let's create a dummy file that
+	# will have version 0 and let cferam be the second (version 1).
+	touch $@-cferam/1-openwrt
+	# Add cferam as the last file in the JFFS2 partition
+	cp $(KDIR)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME)
+
+	# The JFFS2 partition creation should result in the following
+	# layout:
+	# 1) 1-openwrt (version 0, ino 2)
+	# 2) cferam.000 (version 1, ino 3)
+	$(call Build/cfe-jffs2,$@-cferam)
+
+	# Some devices need padding between CFE RAM and kernel
+	$(if $(CFE_RAM_JFFS2_PAD),$(call Build/pad-to,$(CFE_RAM_JFFS2_PAD)))
+
+	# Add CFE partition tag
+	$(if $(CFE_PART_ID),$(call Build/cfe-part-tag))
+
+	# Append kernel
+	dd if=$@.kernel >> $@
+	rm -f $@.kernel
+endef
+
+define Build/cfe-jffs2-kernel
+	rm -rf $@-kernel
+	mkdir -p $@-kernel
+
+	# CFE RAM checks JFFS2 dirent version of vmlinux.
+	# If version is not > 0 it will ignore the fs entry.
+	# JFFS2 sets version 0 to the first fs entry and increments
+	# it on the following ones, so let's create a dummy file that
+	# will have version 0 and let cferam be the second (version 1).
+	touch $@-kernel/1-openwrt
+	# vmlinux is located on a different JFFS2 partition, but CFE RAM
+	# ignores it, so let's create another dummy file that will match
+	# the JFFS2 ino of cferam entry on the first JFFS2 partition.
+	# CFE RAM won't be able to find vmlinux if cferam has the same
+	# ino as vmlinux.
+	touch $@-kernel/2-openwrt
+	# Add vmlinux as the last file in the JFFS2 partition
+	$(TOPDIR)/scripts/cfe-bin-header.py \
+		--input-file $@ \
+		--output-file $@-kernel/vmlinux.lz \
+		--load-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \
+		--entry-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY))
+
+	# The JFFS2 partition creation should result in the following
+	# layout:
+	# 1) 1-openwrt (version 0, ino 2)
+	# 2) 2-openwrt (version 1, ino 3)
+	# 3) vmlinux.lz (version 2, ino 4)
+	$(call Build/cfe-jffs2,$@-kernel)
+endef
+
+define Build/cfe-part-tag
+	mv $@ $@.part
+
+	$(TOPDIR)/scripts/cfe-partition-tag.py \
+		--input-file $@.part \
+		--output-file $@ \
+		--flags $(CFE_PART_FLAGS) \
+		--id $(CFE_PART_ID) \
+		--name $(VERSION_CODE) \
+		--version $(DEVICE_NAME)
+
+	$(call Build/pad-to,$(BLOCKSIZE))
+
+	dd if=$@.part >> $@
+endef
+
+define Build/cfe-sercomm-crypto
+	$(TOPDIR)/scripts/sercomm-crypto.py \
+		--input-file $@ \
+		--key-file $@.key \
+		--output-file $@.ser \
+		--version OpenWrt
+	$(STAGING_DIR_HOST)/bin/openssl enc -md md5 -aes-256-cbc \
+		-in $@ -out $@.enc \
+		-K `cat $@.key` \
+		-iv 00000000000000000000000000000000
+	dd if=$@.enc >> $@.ser
+	mv $@.ser $@
+	rm -f $@.enc $@.key
+endef
+
+define Build/cfe-sercomm-load
+	$(TOPDIR)/scripts/sercomm-pid.py \
+		--hw-version $(SERCOMM_HWVER) \
+		--sw-version $(SERCOMM_SWVER) \
+		--extra-padding-size 0x10 \
+		--pid-file $@.pid
+	$(TOPDIR)/scripts/sercomm-payload.py \
+		--input-file $@ \
+		--output-file $@.new \
+		--pid-file $@.pid
+
+	mv $@.new $@
+	rm -f $@.pid
+endef
+
+define Build/cfe-sercomm-part
+	$(TOPDIR)/scripts/sercomm-partition-tag.py \
+		--input-file $@ \
+		--output-file $@.kernel_rootfs \
+		--part-name kernel_rootfs \
+		--part-version OpenWrt \
+		--rootfs-version $(SERCOMM_FSVER)
+
+	rm -rf $@-rootfs_lib
+	mkdir -p $@-rootfs_lib
+	echo $(SERCOMM_FSVER) > $@-rootfs_lib/lib_ver
+	$(call Build/cfe-jffs2,$@-rootfs_lib)
+	$(call Build/pad-to,$(BLOCKSIZE))
+	$(TOPDIR)/scripts/sercomm-partition-tag.py \
+		--input-file $@ \
+		--output-file $@.rootfs_lib \
+		--part-name rootfs_lib \
+		--part-version $(SERCOMM_FSVER)
+
+	mv $@.kernel_rootfs $@
+	dd if=$@.rootfs_lib >> $@
+endef
+
+define Build/cfe-wfi-tag
+	$(TOPDIR)/scripts/cfe-wfi-tag.py \
+		--input-file $@ \
+		--output-file $@.new \
+		--version $(if $(1),$(1),$(CFE_WFI_VERSION)) \
+		--chip-id $(CFE_WFI_CHIP_ID) \
+		--flash-type $(CFE_WFI_FLASH_TYPE) \
+		$(if $(CFE_WFI_FLAGS),--flags $(CFE_WFI_FLAGS))
+	mv $@.new $@
+endef
+
+### Device scripts ###
+define Device/Default
+  PROFILES = Default $$(DEVICE_NAME)
+  KERNEL_DEPENDS = $$(wildcard ../dts/$$(DEVICE_DTS).dts)
+  DEVICE_DTS_DIR := ../dts
+  CHIP_ID :=
+  SOC = bcm$$(CHIP_ID)
+  DEVICE_DTS = $$(SOC)-$(subst _,-,$(1))
+  DEVICE_LOADADDR :=
+endef
+
+define Device/bcm63xx-cfe
+  FILESYSTEMS := squashfs jffs2-64k jffs2-128k
+  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf
+  KERNEL_INITRAMFS_SUFFIX := .elf
+  IMAGES := cfe.bin sysupgrade.bin
+  IMAGE/cfe.bin := \
+    cfe-bin $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2))
+  IMAGE/sysupgrade.bin := cfe-bin | append-metadata
+  BLOCKSIZE := 0x10000
+  IMAGE_OFFSET :=
+  FLASH_MB :=
+  CFE_BOARD_ID :=
+  CFE_EXTRAS = --block-size $$(BLOCKSIZE) \
+    --image-offset $$(if $$(IMAGE_OFFSET),$$(IMAGE_OFFSET),$$(BLOCKSIZE))
+endef
+
+# Legacy CFEs with specific LZMA parameters and no length
+define Device/bcm63xx-cfe-legacy
+  $(Device/bcm63xx-cfe)
+  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe
+endef
+
+# CFE images with U-Boot in front of the kernel, these will execute
+# U-Boot instead of the kernel and U-Boot will then proceed to load
+# the kernel. The reason to do this is that CFE is sometimes unable to
+# load big kernels even with the lzma loader tricks.
+define Device/bcm63xx-cfe-uboot
+  $(Device/bcm63xx-cfe)
+  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma
+  IMAGE/cfe.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-rootfs $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2))
+  IMAGE/sysupgrade.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-rootfs | append-metadata
+endef
+
+# CFE expects a single JFFS2 partition with cferam and kernel. However,
+# it's possible to fool CFE into properly loading both cferam and kernel
+# from two different JFFS2 partitions by adding dummy files (see
+# cfe-jffs2-cferam and cfe-jffs2-kernel).
+# Separate JFFS2 partitions allow upgrading openwrt without reflashing cferam
+# JFFS2 partition, which is much safer in case anything goes wrong.
+define Device/bcm63xx-nand
+  FILESYSTEMS := squashfs ubifs
+  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | cfe-jffs2-kernel
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf
+  KERNEL_INITRAMFS_SUFFIX := .elf
+  IMAGES := cfe.bin sysupgrade.bin
+  IMAGE/cfe.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) |\
+    cfe-jffs2-cferam | append-ubi | cfe-wfi-tag
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  KERNEL_SIZE := 5120k
+  CFE_PART_FLAGS :=
+  CFE_PART_ID :=
+  CFE_RAM_FILE :=
+  CFE_RAM_JFFS2_NAME :=
+  CFE_RAM_JFFS2_PAD :=
+  CFE_WFI_VERSION :=
+  CFE_WFI_CHIP_ID = 0x$$(CHIP_ID)
+  CFE_WFI_FLASH_TYPE :=
+  CFE_WFI_FLAGS :=
+  UBINIZE_OPTS := -E 5
+  DEVICE_PACKAGES += nand-utils
+endef
+
+define Device/bcm63xx-netgear
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := NETGEAR
+  IMAGES := factory.chk sysupgrade.bin
+  IMAGE/factory.chk := cfe-bin | netgear-chk
+  NETGEAR_BOARD_ID :=
+  NETGEAR_REGION :=
+endef
+
+define Device/sercomm-nand
+  $(Device/bcm63xx-nand)
+  IMAGES := factory.img sysupgrade.bin
+  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi |\
+    cfe-sercomm-part | gzip | cfe-sercomm-load | cfe-sercomm-crypto
+  SERCOMM_FSVER :=
+  SERCOMM_HWVER :=
+  SERCOMM_SWVER :=
+endef
+
+### Package helpers ###
+ATH9K_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-mbedtls
+B43_PACKAGES := kmod-b43 wpad-basic-mbedtls
+USB1_PACKAGES := kmod-usb-ohci kmod-usb-ledtrig-usbport
+USB2_PACKAGES := $(USB1_PACKAGES) kmod-usb2
+
+include $(SUBTARGET).mk
+
+$(eval $(call BuildImage))

target/linux/bmips/image/bcm6318.mk

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/comtrend_ar-5315u
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := AR-5315u
+  CHIP_ID := 6318
+  CFE_BOARD_ID := 96318A-1441N1
+  FLASH_MB := 16
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43217-sprom \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += comtrend_ar-5315u

target/linux/bmips/image/bcm63268.mk

@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/comtrend_vg-8050
+  $(Device/bcm63xx-nand)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := VG-8050
+  CHIP_ID := 63268
+  SOC := bcm63169
+  CFE_RAM_FILE := comtrend,vg-8050/cferam.000
+  CFE_RAM_JFFS2_NAME := cferam.000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+  CFE_WFI_FLASH_TYPE := 3
+  CFE_WFI_VERSION := 0x5732
+endef
+TARGET_DEVICES += comtrend_vg-8050
+
+define Device/comtrend_vr-3032u
+  $(Device/bcm63xx-nand)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := VR-3032u
+  CHIP_ID := 63268
+  SOC := bcm63168
+  CFE_RAM_FILE := comtrend,vr-3032u/cferam.000
+  CFE_RAM_JFFS2_NAME := cferam.000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+  CFE_WFI_FLASH_TYPE := 3
+  CFE_WFI_VERSION := 0x5732
+endef
+TARGET_DEVICES += comtrend_vr-3032u
+
+define Device/sagem_fast-3864-op
+  $(Device/bcm63xx-nand)
+  DEVICE_VENDOR := Sagemcom
+  DEVICE_MODEL := F@ST 3864
+  DEVICE_VARIANT := OP
+  CHIP_ID := 63268
+  SOC := bcm63168
+  CFE_RAM_FILE := sagem,fast-3864-op/cferam.000
+  CFE_RAM_JFFS2_NAME := cferam.000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+  CFE_WFI_FLASH_TYPE := 3
+  CFE_WFI_VERSION := 0x5732
+endef
+TARGET_DEVICES += sagem_fast-3864-op
+
+define Device/sercomm_h500-s-lowi
+  $(Device/sercomm-nand)
+  DEVICE_VENDOR := Sercomm
+  DEVICE_MODEL := H500-s
+  DEVICE_VARIANT := lowi
+  DEVICE_LOADADDR := $(KERNEL_LOADADDR)
+  KERNEL := kernel-bin | append-dtb | lzma | cfe-jffs2-kernel
+  CHIP_ID := 63268
+  SOC := bcm63167
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+  SERCOMM_FSVER := 1001
+  SERCOMM_HWVER := 1434b31
+  SERCOMM_SWVER := 3305
+endef
+TARGET_DEVICES += sercomm_h500-s-lowi
+
+define Device/sercomm_h500-s-vfes
+  $(Device/sercomm-nand)
+  DEVICE_VENDOR := Sercomm
+  DEVICE_MODEL := H500-s
+  DEVICE_VARIANT := vfes
+  DEVICE_LOADADDR := $(KERNEL_LOADADDR)
+  KERNEL := kernel-bin | append-dtb | lzma | cfe-jffs2-kernel
+  CHIP_ID := 63268
+  SOC := bcm63167
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+  SERCOMM_FSVER := 1001
+  SERCOMM_HWVER := 142584b
+  SERCOMM_SWVER := 3417
+endef
+TARGET_DEVICES += sercomm_h500-s-vfes
+
+define Device/sercomm_shg2500
+  $(Device/sercomm-nand)
+  DEVICE_VENDOR := Sercomm
+  DEVICE_MODEL := SHG2500
+  DEVICE_LOADADDR := $(KERNEL_LOADADDR)
+  KERNEL := kernel-bin | append-dtb | lzma | cfe-jffs2-kernel
+  CHIP_ID := 63268
+  SOC := bcm63168
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    broadcom-4360-sprom \
+    kmod-i2c-gpio kmod-leds-sercomm-msp430
+  SERCOMM_FSVER := 1001
+  SERCOMM_HWVER := 1424e4a
+  SERCOMM_SWVER := 3207
+endef
+TARGET_DEVICES += sercomm_shg2500
+
+define Device/smartrg_sr505n
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := SmartRG
+  DEVICE_MODEL := SR505n
+  DEVICE_LOADADDR := $(KERNEL_LOADADDR)
+  CHIP_ID := 63268
+  SOC := bcm63168
+  CFE_BOARD_ID := 963168MBV_17AZZ
+  FLASH_MB := 16
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += smartrg_sr505n

target/linux/bmips/image/bcm6328.mk

@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/arcadyan_ar7516
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Arcadyan
+  DEVICE_MODEL := AR7516
+  CHIP_ID := 6328
+  CFE_BOARD_ID := AR7516AAW
+  FLASH_MB := 8
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43227-sprom \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += arcadyan_ar7516
+
+define Device/comtrend_ar-5381u
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := AR-5381u
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328A-1241N
+  FLASH_MB := 16
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43225-sprom \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += comtrend_ar-5381u
+
+define Device/comtrend_ar-5387un
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := AR-5387un
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328A-1441N1
+  FLASH_MB := 16
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43225-sprom \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += comtrend_ar-5387un
+
+define Device/innacomm_w3400v6
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Innacomm
+  DEVICE_MODEL := W3400V6
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328ang
+  FLASH_MB := 8
+  DEVICE_PACKAGES += $(B43_PACKAGES) \
+    broadcom-4318-sprom kmod-leds-bcm6328
+endef
+TARGET_DEVICES += innacomm_w3400v6
+
+define Device/inteno_xg6846
+  $(Device/bcm63xx-cfe-uboot)
+  DEVICE_VENDOR := Inteno
+  DEVICE_MODEL := XG6846
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328avng
+  FLASH_MB := 16
+  DEVICE_PACKAGES := $(USB2_PACKAGES) \
+    kmod-i2c-core kmod-i2c-gpio \
+    kmod-leds-bcm6328 kmod-dsa-mv88e6xxx \
+    kmod-sfp
+endef
+TARGET_DEVICES += inteno_xg6846
+
+define Device/nucom_r5010unv2
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := NuCom
+  DEVICE_MODEL := R5010UNv2
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328ang
+  FLASH_MB := 16
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43217-sprom \
+    kmod-leds-bcm6328
+endef
+TARGET_DEVICES += nucom_r5010unv2
+
+define Device/sercomm_ad1018
+  $(Device/sercomm-nand)
+  DEVICE_VENDOR := Sercomm
+  DEVICE_MODEL := AD1018
+  CHIP_ID := 6328
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43217-sprom \
+    kmod-leds-bcm6328
+  SERCOMM_FSVER := 1001
+  SERCOMM_HWVER := 1415153
+  SERCOMM_SWVER := 3013
+endef
+TARGET_DEVICES += sercomm_ad1018

target/linux/bmips/image/bcm6358.mk

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/huawei_hg556a-b
+  $(Device/bcm63xx-cfe-legacy)
+  DEVICE_VENDOR := Huawei
+  DEVICE_MODEL := EchoLife HG556a
+  DEVICE_VARIANT := B
+  CHIP_ID := 6358
+  CFE_BOARD_ID := HW556
+  CFE_EXTRAS += --rsa-signature "EchoLife_HG556a" --tag-version 8
+  BLOCKSIZE := 0x20000
+  DEVICE_PACKAGES += $(USB2_PACKAGES) $(ATH9K_PACKAGES) \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += huawei_hg556a-b

target/linux/bmips/image/bcm6362.mk

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/huawei_hg253s-v2
+  $(Device/bcm63xx-nand)
+  IMAGES := flash.bin sysupgrade.bin
+  IMAGE/flash.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | cfe-jffs2-cferam | append-ubi
+  DEVICE_VENDOR := Huawei
+  DEVICE_MODEL := HG253s
+  DEVICE_VARIANT := v2
+  CHIP_ID := 6362
+  CFE_PART_FLAGS := 1
+  CFE_PART_ID := 0x0001EFEE
+  CFE_RAM_FILE := huawei,hg253s-v2/cferam.000
+  CFE_RAM_JFFS2_NAME := cferam.000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  VID_HDR_OFFSET := 2048
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    kmod-leds-bcm6328 kmod-leds-gpio
+  CFE_WFI_FLASH_TYPE := 3
+endef
+TARGET_DEVICES += huawei_hg253s-v2
+
+define Device/netgear_dgnd3700-v2
+  $(Device/bcm63xx-nand)
+  DEVICE_VENDOR := NETGEAR
+  DEVICE_MODEL := DGND3700
+  DEVICE_VARIANT := v2
+  CHIP_ID := 6362
+  CFE_RAM_FILE := netgear,dgnd3700-v2/cferam
+  CFE_RAM_JFFS2_NAME := cferam
+  CFE_RAM_JFFS2_PAD := 496k
+  BLOCKSIZE := 16k
+  PAGESIZE := 512
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) \
+    kmod-leds-bcm6328 kmod-leds-gpio
+  CFE_WFI_FLASH_TYPE := 2
+  CFE_WFI_VERSION := 0x5731
+endef
+TARGET_DEVICES += netgear_dgnd3700-v2

target/linux/bmips/image/bcm6368.mk

@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+define Device/actiontec_r1000h
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Actiontec
+  DEVICE_MODEL := R1000H
+  CHIP_ID := 6368
+  CFE_BOARD_ID := 96368VVW
+  BLOCKSIZE := 0x20000
+  FLASH_MB := 32
+  CFE_EXTRAS += --signature "$$(DEVICE_VENDOR)"
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += actiontec_r1000h
+
+define Device/comtrend_vr-3025u
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := VR-3025u
+  CHIP_ID := 6368
+  CFE_BOARD_ID := 96368M-1541N
+  BLOCKSIZE := 0x20000
+  FLASH_MB := 32
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43222-sprom \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += comtrend_vr-3025u
+
+define Device/comtrend_vr-3025un
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := VR-3025un
+  CHIP_ID := 6368
+  CFE_BOARD_ID := 96368M-1341N
+  FLASH_MB := 8
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43222-sprom \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += comtrend_vr-3025un
+
+define Device/comtrend_wap-5813n
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Comtrend
+  DEVICE_MODEL := WAP-5813n
+  CHIP_ID := 6368
+  SOC := bcm6369
+  CFE_BOARD_ID := 96369R-1231N
+  FLASH_MB := 8
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-4322-sprom \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += comtrend_wap-5813n
+
+define Device/netgear_dgnd3700-v1
+  $(Device/bcm63xx-netgear)
+  DEVICE_VENDOR := NETGEAR
+  DEVICE_MODEL := DGND3700
+  DEVICE_VARIANT := v1
+  CFE_BOARD_ID := 96368MVWG
+  CHIP_ID := 6368
+  BLOCKSIZE := 0x20000
+  NETGEAR_BOARD_ID := U12L144T01_NETGEAR_NEWLED
+  NETGEAR_REGION := 1
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += netgear_dgnd3700-v1
+
+define Device/netgear_dgnd3800b
+  $(Device/bcm63xx-netgear)
+  DEVICE_VENDOR := NETGEAR
+  DEVICE_MODEL := DGND3800B
+  CFE_BOARD_ID := 96368MVWG
+  CHIP_ID := 6368
+  BLOCKSIZE := 0x20000
+  NETGEAR_BOARD_ID := U12L144T11_NETGEAR_NEWLED
+  NETGEAR_REGION := 1
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += netgear_dgnd3800b
+
+define Device/netgear_evg2000
+  $(Device/bcm63xx-netgear)
+  DEVICE_MODEL := EVG2000
+  CFE_BOARD_ID := 96369PVG
+  CHIP_ID := 6368
+  SOC := bcm6369
+  BLOCKSIZE := 0x20000
+  NETGEAR_BOARD_ID := U12H154T90_NETGEAR
+  NETGEAR_REGION := 1
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-4322-sprom \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += netgear_evg2000
+
+define Device/observa_vh4032n
+  $(Device/bcm63xx-cfe)
+  DEVICE_VENDOR := Observa
+  DEVICE_MODEL := VH4032N
+  IMAGES += sysupgrade.bin
+  CFE_BOARD_ID := 96368VVW
+  CHIP_ID := 6368
+  BLOCKSIZE := 0x20000
+  FLASH_MB := 32
+  DEVICE_PACKAGES += $(USB2_PACKAGES) \
+    $(B43_PACKAGES) broadcom-43222-sprom \
+    kmod-leds-gpio
+endef
+TARGET_DEVICES += observa_vh4032n

target/linux/bmips/image/lzma-loader/Makefile

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+# Copyright (C) 2011 OpenWrt.org
+# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+#
+
+include $(TOPDIR)/rules.mk
+
+LZMA_TEXT_START	:= 0x80a00000
+LOADER		:= loader.bin
+LOADER_NAME	:= $(basename $(notdir $(LOADER)))
+LOADER_DATA 	:=
+TARGET_DIR	:=
+
+UART_BASE_3329 := 0xb0000100
+UART_BASE_3368 := 0xfff8c100
+UART_BASE_3380 := 0xb4e00200
+UART_BASE_3383 := 0xb4e00500
+UART_BASE_3384 := 0xb4e00500
+UART_BASE_6318 := 0xb0000100
+UART_BASE_6328 := 0xb0000100
+UART_BASE_6338 := 0xfffe0300
+UART_BASE_6345 := 0xfffe0300
+UART_BASE_6348 := 0xfffe0300
+UART_BASE_6358 := 0xfffe0100
+UART_BASE_6362 := 0xb0000100
+UART_BASE_6368 := 0xb0000100
+UART_BASE_63268 := 0xb0000180
+UART_BASE_6816 := 0xb0000100
+UART_BASE_6818 := 0xb0000100
+UART_BASE_6828 := 0xb0000180
+UART_BASE := $(if $(UART_BASE_$(CHIP_ID)),$(UART_BASE_$(CHIP_ID)),0)
+
+ifeq ($(TARGET_DIR),)
+TARGET_DIR	:= $(KDIR)
+endif
+
+LOADER_BIN	:= $(TARGET_DIR)/$(LOADER_NAME).bin
+LOADER_ELF	:= $(TARGET_DIR)/$(LOADER_NAME).elf
+
+PKG_NAME := lzma-loader
+PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)
+
+.PHONY : loader-compile loader.bin loader.elf
+
+$(PKG_BUILD_DIR)/.prepared:
+	mkdir $(PKG_BUILD_DIR)
+	$(CP) ./src/* $(PKG_BUILD_DIR)/
+	touch $@
+
+loader-compile: $(PKG_BUILD_DIR)/.prepared
+	$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \
+		LZMA_TEXT_START=$(LZMA_TEXT_START) \
+		LOADER_DATA=$(LOADER_DATA) \
+		UART_BASE=$(UART_BASE) \
+		clean all
+
+loader.elf: $(PKG_BUILD_DIR)/loader.elf
+	$(CP) $< $(LOADER_ELF)
+
+loader.bin: $(PKG_BUILD_DIR)/loader.bin
+	$(CP) $< $(LOADER_BIN)
+
+download:
+prepare: $(PKG_BUILD_DIR)/.prepared
+compile: loader-compile
+
+install:
+
+clean:
+	rm -rf $(PKG_BUILD_DIR)

target/linux/bmips/image/lzma-loader/src/LzmaDecode.c

@@ -0,0 +1,584 @@
+/*
+  LzmaDecode.c
+  LZMA Decoder (optimized for Speed version)
+  
+  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+  http://www.7-zip.org/
+
+  LZMA SDK is licensed under two licenses:
+  1) GNU Lesser General Public License (GNU LGPL)
+  2) Common Public License (CPL)
+  It means that you can select one of these two licenses and 
+  follow rules of that license.
+
+  SPECIAL EXCEPTION:
+  Igor Pavlov, as the author of this Code, expressly permits you to 
+  statically or dynamically link your Code (or bind by name) to the 
+  interfaces of this file without subjecting your linked Code to the 
+  terms of the CPL or GNU LGPL. Any modifications or additions 
+  to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#include "LzmaDecode.h"
+
+#define kNumTopBits 24
+#define kTopValue ((UInt32)1 << kNumTopBits)
+
+#define kNumBitModelTotalBits 11
+#define kBitModelTotal (1 << kNumBitModelTotalBits)
+#define kNumMoveBits 5
+
+#define RC_READ_BYTE (*Buffer++)
+
+#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
+  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
+
+#ifdef _LZMA_IN_CB
+
+#define RC_TEST { if (Buffer == BufferLim) \
+  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
+  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
+
+#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
+
+#else
+
+#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
+
+#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
+ 
+#endif
+
+#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
+
+#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
+#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
+#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
+
+#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
+  { UpdateBit0(p); mi <<= 1; A0; } else \
+  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } 
+  
+#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               
+
+#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
+  { int i = numLevels; res = 1; \
+  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
+  res -= (1 << numLevels); }
+
+
+#define kNumPosBitsMax 4
+#define kNumPosStatesMax (1 << kNumPosBitsMax)
+
+#define kLenNumLowBits 3
+#define kLenNumLowSymbols (1 << kLenNumLowBits)
+#define kLenNumMidBits 3
+#define kLenNumMidSymbols (1 << kLenNumMidBits)
+#define kLenNumHighBits 8
+#define kLenNumHighSymbols (1 << kLenNumHighBits)
+
+#define LenChoice 0
+#define LenChoice2 (LenChoice + 1)
+#define LenLow (LenChoice2 + 1)
+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
+#define kNumLenProbs (LenHigh + kLenNumHighSymbols) 
+
+
+#define kNumStates 12
+#define kNumLitStates 7
+
+#define kStartPosModelIndex 4
+#define kEndPosModelIndex 14
+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
+
+#define kNumPosSlotBits 6
+#define kNumLenToPosStates 4
+
+#define kNumAlignBits 4
+#define kAlignTableSize (1 << kNumAlignBits)
+
+#define kMatchMinLen 2
+
+#define IsMatch 0
+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
+#define IsRepG0 (IsRep + kNumStates)
+#define IsRepG1 (IsRepG0 + kNumStates)
+#define IsRepG2 (IsRepG1 + kNumStates)
+#define IsRep0Long (IsRepG2 + kNumStates)
+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
+#define LenCoder (Align + kAlignTableSize)
+#define RepLenCoder (LenCoder + kNumLenProbs)
+#define Literal (RepLenCoder + kNumLenProbs)
+
+#if Literal != LZMA_BASE_SIZE
+StopCompilingDueBUG
+#endif
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
+{
+  unsigned char prop0;
+  if (size < LZMA_PROPERTIES_SIZE)
+    return LZMA_RESULT_DATA_ERROR;
+  prop0 = propsData[0];
+  if (prop0 >= (9 * 5 * 5))
+    return LZMA_RESULT_DATA_ERROR;
+  {
+    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
+    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
+    propsRes->lc = prop0;
+    /*
+    unsigned char remainder = (unsigned char)(prop0 / 9);
+    propsRes->lc = prop0 % 9;
+    propsRes->pb = remainder / 5;
+    propsRes->lp = remainder % 5;
+    */
+  }
+
+  #ifdef _LZMA_OUT_READ
+  {
+    int i;
+    propsRes->DictionarySize = 0;
+    for (i = 0; i < 4; i++)
+      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
+    if (propsRes->DictionarySize == 0)
+      propsRes->DictionarySize = 1;
+  }
+  #endif
+  return LZMA_RESULT_OK;
+}
+
+#define kLzmaStreamWasFinishedId (-1)
+
+int LzmaDecode(CLzmaDecoderState *vs,
+    #ifdef _LZMA_IN_CB
+    ILzmaInCallback *InCallback,
+    #else
+    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+    #endif
+    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
+{
+  CProb *p = vs->Probs;
+  SizeT nowPos = 0;
+  Byte previousByte = 0;
+  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
+  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
+  int lc = vs->Properties.lc;
+
+  #ifdef _LZMA_OUT_READ
+  
+  UInt32 Range = vs->Range;
+  UInt32 Code = vs->Code;
+  #ifdef _LZMA_IN_CB
+  const Byte *Buffer = vs->Buffer;
+  const Byte *BufferLim = vs->BufferLim;
+  #else
+  const Byte *Buffer = inStream;
+  const Byte *BufferLim = inStream + inSize;
+  #endif
+  int state = vs->State;
+  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
+  int len = vs->RemainLen;
+  UInt32 globalPos = vs->GlobalPos;
+  UInt32 distanceLimit = vs->DistanceLimit;
+
+  Byte *dictionary = vs->Dictionary;
+  UInt32 dictionarySize = vs->Properties.DictionarySize;
+  UInt32 dictionaryPos = vs->DictionaryPos;
+
+  Byte tempDictionary[4];
+
+  #ifndef _LZMA_IN_CB
+  *inSizeProcessed = 0;
+  #endif
+  *outSizeProcessed = 0;
+  if (len == kLzmaStreamWasFinishedId)
+    return LZMA_RESULT_OK;
+
+  if (dictionarySize == 0)
+  {
+    dictionary = tempDictionary;
+    dictionarySize = 1;
+    tempDictionary[0] = vs->TempDictionary[0];
+  }
+
+  if (len == kLzmaNeedInitId)
+  {
+    {
+      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+      UInt32 i;
+      for (i = 0; i < numProbs; i++)
+        p[i] = kBitModelTotal >> 1; 
+      rep0 = rep1 = rep2 = rep3 = 1;
+      state = 0;
+      globalPos = 0;
+      distanceLimit = 0;
+      dictionaryPos = 0;
+      dictionary[dictionarySize - 1] = 0;
+      #ifdef _LZMA_IN_CB
+      RC_INIT;
+      #else
+      RC_INIT(inStream, inSize);
+      #endif
+    }
+    len = 0;
+  }
+  while(len != 0 && nowPos < outSize)
+  {
+    UInt32 pos = dictionaryPos - rep0;
+    if (pos >= dictionarySize)
+      pos += dictionarySize;
+    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
+    if (++dictionaryPos == dictionarySize)
+      dictionaryPos = 0;
+    len--;
+  }
+  if (dictionaryPos == 0)
+    previousByte = dictionary[dictionarySize - 1];
+  else
+    previousByte = dictionary[dictionaryPos - 1];
+
+  #else /* if !_LZMA_OUT_READ */
+
+  int state = 0;
+  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
+  int len = 0;
+  const Byte *Buffer;
+  const Byte *BufferLim;
+  UInt32 Range;
+  UInt32 Code;
+
+  #ifndef _LZMA_IN_CB
+  *inSizeProcessed = 0;
+  #endif
+  *outSizeProcessed = 0;
+
+  {
+    UInt32 i;
+    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+    for (i = 0; i < numProbs; i++)
+      p[i] = kBitModelTotal >> 1;
+  }
+  
+  #ifdef _LZMA_IN_CB
+  RC_INIT;
+  #else
+  RC_INIT(inStream, inSize);
+  #endif
+
+  #endif /* _LZMA_OUT_READ */
+
+  while(nowPos < outSize)
+  {
+    CProb *prob;
+    UInt32 bound;
+    int posState = (int)(
+        (nowPos 
+        #ifdef _LZMA_OUT_READ
+        + globalPos
+        #endif
+        )
+        & posStateMask);
+
+    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
+    IfBit0(prob)
+    {
+      int symbol = 1;
+      UpdateBit0(prob)
+      prob = p + Literal + (LZMA_LIT_SIZE * 
+        (((
+        (nowPos 
+        #ifdef _LZMA_OUT_READ
+        + globalPos
+        #endif
+        )
+        & literalPosMask) << lc) + (previousByte >> (8 - lc))));
+
+      if (state >= kNumLitStates)
+      {
+        int matchByte;
+        #ifdef _LZMA_OUT_READ
+        UInt32 pos = dictionaryPos - rep0;
+        if (pos >= dictionarySize)
+          pos += dictionarySize;
+        matchByte = dictionary[pos];
+        #else
+        matchByte = outStream[nowPos - rep0];
+        #endif
+        do
+        {
+          int bit;
+          CProb *probLit;
+          matchByte <<= 1;
+          bit = (matchByte & 0x100);
+          probLit = prob + 0x100 + bit + symbol;
+          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
+        }
+        while (symbol < 0x100);
+      }
+      while (symbol < 0x100)
+      {
+        CProb *probLit = prob + symbol;
+        RC_GET_BIT(probLit, symbol)
+      }
+      previousByte = (Byte)symbol;
+
+      outStream[nowPos++] = previousByte;
+      #ifdef _LZMA_OUT_READ
+      if (distanceLimit < dictionarySize)
+        distanceLimit++;
+
+      dictionary[dictionaryPos] = previousByte;
+      if (++dictionaryPos == dictionarySize)
+        dictionaryPos = 0;
+      #endif
+      if (state < 4) state = 0;
+      else if (state < 10) state -= 3;
+      else state -= 6;
+    }
+    else             
+    {
+      UpdateBit1(prob);
+      prob = p + IsRep + state;
+      IfBit0(prob)
+      {
+        UpdateBit0(prob);
+        rep3 = rep2;
+        rep2 = rep1;
+        rep1 = rep0;
+        state = state < kNumLitStates ? 0 : 3;
+        prob = p + LenCoder;
+      }
+      else
+      {
+        UpdateBit1(prob);
+        prob = p + IsRepG0 + state;
+        IfBit0(prob)
+        {
+          UpdateBit0(prob);
+          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
+          IfBit0(prob)
+          {
+            #ifdef _LZMA_OUT_READ
+            UInt32 pos;
+            #endif
+            UpdateBit0(prob);
+            
+            #ifdef _LZMA_OUT_READ
+            if (distanceLimit == 0)
+            #else
+            if (nowPos == 0)
+            #endif
+              return LZMA_RESULT_DATA_ERROR;
+            
+            state = state < kNumLitStates ? 9 : 11;
+            #ifdef _LZMA_OUT_READ
+            pos = dictionaryPos - rep0;
+            if (pos >= dictionarySize)
+              pos += dictionarySize;
+            previousByte = dictionary[pos];
+            dictionary[dictionaryPos] = previousByte;
+            if (++dictionaryPos == dictionarySize)
+              dictionaryPos = 0;
+            #else
+            previousByte = outStream[nowPos - rep0];
+            #endif
+            outStream[nowPos++] = previousByte;
+            #ifdef _LZMA_OUT_READ
+            if (distanceLimit < dictionarySize)
+              distanceLimit++;
+            #endif
+
+            continue;
+          }
+          else
+          {
+            UpdateBit1(prob);
+          }
+        }
+        else
+        {
+          UInt32 distance;
+          UpdateBit1(prob);
+          prob = p + IsRepG1 + state;
+          IfBit0(prob)
+          {
+            UpdateBit0(prob);
+            distance = rep1;
+          }
+          else 
+          {
+            UpdateBit1(prob);
+            prob = p + IsRepG2 + state;
+            IfBit0(prob)
+            {
+              UpdateBit0(prob);
+              distance = rep2;
+            }
+            else
+            {
+              UpdateBit1(prob);
+              distance = rep3;
+              rep3 = rep2;
+            }
+            rep2 = rep1;
+          }
+          rep1 = rep0;
+          rep0 = distance;
+        }
+        state = state < kNumLitStates ? 8 : 11;
+        prob = p + RepLenCoder;
+      }
+      {
+        int numBits, offset;
+        CProb *probLen = prob + LenChoice;
+        IfBit0(probLen)
+        {
+          UpdateBit0(probLen);
+          probLen = prob + LenLow + (posState << kLenNumLowBits);
+          offset = 0;
+          numBits = kLenNumLowBits;
+        }
+        else
+        {
+          UpdateBit1(probLen);
+          probLen = prob + LenChoice2;
+          IfBit0(probLen)
+          {
+            UpdateBit0(probLen);
+            probLen = prob + LenMid + (posState << kLenNumMidBits);
+            offset = kLenNumLowSymbols;
+            numBits = kLenNumMidBits;
+          }
+          else
+          {
+            UpdateBit1(probLen);
+            probLen = prob + LenHigh;
+            offset = kLenNumLowSymbols + kLenNumMidSymbols;
+            numBits = kLenNumHighBits;
+          }
+        }
+        RangeDecoderBitTreeDecode(probLen, numBits, len);
+        len += offset;
+      }
+
+      if (state < 4)
+      {
+        int posSlot;
+        state += kNumLitStates;
+        prob = p + PosSlot +
+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << 
+            kNumPosSlotBits);
+        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
+        if (posSlot >= kStartPosModelIndex)
+        {
+          int numDirectBits = ((posSlot >> 1) - 1);
+          rep0 = (2 | ((UInt32)posSlot & 1));
+          if (posSlot < kEndPosModelIndex)
+          {
+            rep0 <<= numDirectBits;
+            prob = p + SpecPos + rep0 - posSlot - 1;
+          }
+          else
+          {
+            numDirectBits -= kNumAlignBits;
+            do
+            {
+              RC_NORMALIZE
+              Range >>= 1;
+              rep0 <<= 1;
+              if (Code >= Range)
+              {
+                Code -= Range;
+                rep0 |= 1;
+              }
+            }
+            while (--numDirectBits != 0);
+            prob = p + Align;
+            rep0 <<= kNumAlignBits;
+            numDirectBits = kNumAlignBits;
+          }
+          {
+            int i = 1;
+            int mi = 1;
+            do
+            {
+              CProb *prob3 = prob + mi;
+              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
+              i <<= 1;
+            }
+            while(--numDirectBits != 0);
+          }
+        }
+        else
+          rep0 = posSlot;
+        if (++rep0 == (UInt32)(0))
+        {
+          /* it's for stream version */
+          len = kLzmaStreamWasFinishedId;
+          break;
+        }
+      }
+
+      len += kMatchMinLen;
+      #ifdef _LZMA_OUT_READ
+      if (rep0 > distanceLimit) 
+      #else
+      if (rep0 > nowPos)
+      #endif
+        return LZMA_RESULT_DATA_ERROR;
+
+      #ifdef _LZMA_OUT_READ
+      if (dictionarySize - distanceLimit > (UInt32)len)
+        distanceLimit += len;
+      else
+        distanceLimit = dictionarySize;
+      #endif
+
+      do
+      {
+        #ifdef _LZMA_OUT_READ
+        UInt32 pos = dictionaryPos - rep0;
+        if (pos >= dictionarySize)
+          pos += dictionarySize;
+        previousByte = dictionary[pos];
+        dictionary[dictionaryPos] = previousByte;
+        if (++dictionaryPos == dictionarySize)
+          dictionaryPos = 0;
+        #else
+        previousByte = outStream[nowPos - rep0];
+        #endif
+        len--;
+        outStream[nowPos++] = previousByte;
+      }
+      while(len != 0 && nowPos < outSize);
+    }
+  }
+  RC_NORMALIZE;
+
+  #ifdef _LZMA_OUT_READ
+  vs->Range = Range;
+  vs->Code = Code;
+  vs->DictionaryPos = dictionaryPos;
+  vs->GlobalPos = globalPos + (UInt32)nowPos;
+  vs->DistanceLimit = distanceLimit;
+  vs->Reps[0] = rep0;
+  vs->Reps[1] = rep1;
+  vs->Reps[2] = rep2;
+  vs->Reps[3] = rep3;
+  vs->State = state;
+  vs->RemainLen = len;
+  vs->TempDictionary[0] = tempDictionary[0];
+  #endif
+
+  #ifdef _LZMA_IN_CB
+  vs->Buffer = Buffer;
+  vs->BufferLim = BufferLim;
+  #else
+  *inSizeProcessed = (SizeT)(Buffer - inStream);
+  #endif
+  *outSizeProcessed = nowPos;
+  return LZMA_RESULT_OK;
+}

target/linux/bmips/image/lzma-loader/src/LzmaDecode.h

@@ -0,0 +1,113 @@
+/* 
+  LzmaDecode.h
+  LZMA Decoder interface
+
+  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+  http://www.7-zip.org/
+
+  LZMA SDK is licensed under two licenses:
+  1) GNU Lesser General Public License (GNU LGPL)
+  2) Common Public License (CPL)
+  It means that you can select one of these two licenses and 
+  follow rules of that license.
+
+  SPECIAL EXCEPTION:
+  Igor Pavlov, as the author of this code, expressly permits you to 
+  statically or dynamically link your code (or bind by name) to the 
+  interfaces of this file without subjecting your linked code to the 
+  terms of the CPL or GNU LGPL. Any modifications or additions 
+  to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifndef __LZMADECODE_H
+#define __LZMADECODE_H
+
+#include "LzmaTypes.h"
+
+/* #define _LZMA_IN_CB */
+/* Use callback for input data */
+
+/* #define _LZMA_OUT_READ */
+/* Use read function for output data */
+
+/* #define _LZMA_PROB32 */
+/* It can increase speed on some 32-bit CPUs, 
+   but memory usage will be doubled in that case */
+
+/* #define _LZMA_LOC_OPT */
+/* Enable local speed optimizations inside code */
+
+#ifdef _LZMA_PROB32
+#define CProb UInt32
+#else
+#define CProb UInt16
+#endif
+
+#define LZMA_RESULT_OK 0
+#define LZMA_RESULT_DATA_ERROR 1
+
+#ifdef _LZMA_IN_CB
+typedef struct _ILzmaInCallback
+{
+  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
+} ILzmaInCallback;
+#endif
+
+#define LZMA_BASE_SIZE 1846
+#define LZMA_LIT_SIZE 768
+
+#define LZMA_PROPERTIES_SIZE 5
+
+typedef struct _CLzmaProperties
+{
+  int lc;
+  int lp;
+  int pb;
+  #ifdef _LZMA_OUT_READ
+  UInt32 DictionarySize;
+  #endif
+}CLzmaProperties;
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
+
+#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
+
+#define kLzmaNeedInitId (-2)
+
+typedef struct _CLzmaDecoderState
+{
+  CLzmaProperties Properties;
+  CProb *Probs;
+
+  #ifdef _LZMA_IN_CB
+  const unsigned char *Buffer;
+  const unsigned char *BufferLim;
+  #endif
+
+  #ifdef _LZMA_OUT_READ
+  unsigned char *Dictionary;
+  UInt32 Range;
+  UInt32 Code;
+  UInt32 DictionaryPos;
+  UInt32 GlobalPos;
+  UInt32 DistanceLimit;
+  UInt32 Reps[4];
+  int State;
+  int RemainLen;
+  unsigned char TempDictionary[4];
+  #endif
+} CLzmaDecoderState;
+
+#ifdef _LZMA_OUT_READ
+#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
+#endif
+
+int LzmaDecode(CLzmaDecoderState *vs,
+    #ifdef _LZMA_IN_CB
+    ILzmaInCallback *inCallback,
+    #else
+    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+    #endif
+    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
+
+#endif

target/linux/bmips/image/lzma-loader/src/LzmaTypes.h

@@ -0,0 +1,45 @@
+/* 
+LzmaTypes.h 
+
+Types for LZMA Decoder
+
+This file written and distributed to public domain by Igor Pavlov.
+This file is part of LZMA SDK 4.40 (2006-05-01)
+*/
+
+#ifndef __LZMATYPES_H
+#define __LZMATYPES_H
+
+#ifndef _7ZIP_BYTE_DEFINED
+#define _7ZIP_BYTE_DEFINED
+typedef unsigned char Byte;
+#endif 
+
+#ifndef _7ZIP_UINT16_DEFINED
+#define _7ZIP_UINT16_DEFINED
+typedef unsigned short UInt16;
+#endif 
+
+#ifndef _7ZIP_UINT32_DEFINED
+#define _7ZIP_UINT32_DEFINED
+#ifdef _LZMA_UINT32_IS_ULONG
+typedef unsigned long UInt32;
+#else
+typedef unsigned int UInt32;
+#endif
+#endif 
+
+/* #define _LZMA_NO_SYSTEM_SIZE_T */
+/* You can use it, if you don't want <stddef.h> */
+
+#ifndef _7ZIP_SIZET_DEFINED
+#define _7ZIP_SIZET_DEFINED
+#ifdef _LZMA_NO_SYSTEM_SIZE_T
+typedef UInt32 SizeT;
+#else
+#include <stddef.h>
+typedef size_t SizeT;
+#endif
+#endif
+
+#endif

target/linux/bmips/image/lzma-loader/src/Makefile

@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Makefile for the LZMA compressed kernel loader for BMIPS based boards
+#
+# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+#
+# Some parts of this file was based on the OpenWrt specific lzma-loader
+# for the BCM47xx and ADM5120 based boards:
+#	Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
+#	Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>
+#	Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
+#
+
+LOADER_ADDR	:=
+KERNEL_ADDR	:=
+LZMA_TEXT_START	:= 0x80a00000
+LOADER_DATA	:=
+
+CC		:= $(CROSS_COMPILE)gcc
+LD		:= $(CROSS_COMPILE)ld
+OBJCOPY		:= $(CROSS_COMPILE)objcopy
+OBJDUMP		:= $(CROSS_COMPILE)objdump
+
+BIN_FLAGS	:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \
+		   -R .MIPS.abiflags -S
+
+CFLAGS		= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
+		  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \
+		  -mno-abicalls -fno-pic -ffunction-sections -pipe \
+		  -ffreestanding -fhonour-copts \
+		  -mabi=32 -march=mips32 \
+		  -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap
+CFLAGS		+= -D_LZMA_PROB32
+CFLAGS		+= -DUART_BASE=$(UART_BASE)
+
+ASFLAGS		= $(CFLAGS) -D__ASSEMBLY__
+
+LDFLAGS		= -static --gc-sections -no-warn-mismatch
+LDFLAGS		+= -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)
+
+O_FORMAT 	= $(shell $(OBJDUMP) -i | head -2 | grep elf32)
+
+OBJECTS		:= head.o loader.o cache.o board.o printf.o LzmaDecode.o
+
+ifneq ($(strip $(LOADER_DATA)),)
+OBJECTS		+= data.o
+CFLAGS		+= -DLZMA_WRAPPER=1 -DLOADADDR=$(KERNEL_ADDR)
+endif
+
+
+all: loader.elf
+
+# Don't build dependencies, this may die if $(CC) isn't gcc
+dep:
+
+install:
+
+%.o : %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+%.o : %.S
+	$(CC) $(ASFLAGS) -c -o $@ $<
+
+data.o: $(LOADER_DATA)
+	$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<
+
+loader: $(OBJECTS)
+	$(LD) $(LDFLAGS) -o $@ $(OBJECTS)
+
+loader.bin: loader
+	$(OBJCOPY) $(BIN_FLAGS) $< $@
+
+loader2.o: loader.bin
+	$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<
+
+loader.elf: loader2.o
+	$(LD) -e startup -T loader2.lds -Ttext $(LOADER_ADDR) -o $@ $<
+
+mrproper: clean
+
+clean:
+	rm -f loader *.elf *.bin *.o

target/linux/bmips/image/lzma-loader/src/board.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * BCM63XX specific implementation parts
+ *
+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+ */
+
+#include <stddef.h>
+#include "config.h"
+
+#define READREG(r)	*(volatile unsigned int *)(r)
+#define WRITEREG(r,v)	*(volatile unsigned int *)(r) = v
+
+#define UART_IR_REG	0x10
+#define UART_FIFO_REG	0x14
+
+static void wait_xfered(void)
+{
+        unsigned int val;
+
+        do {
+                val = READREG(UART_BASE + UART_IR_REG);
+                if (val & (1 << 5))
+                        break;
+        } while (1);
+}
+
+void board_putc(int ch)
+{
+	if (!UART_BASE)
+		return;
+
+	wait_xfered();
+	WRITEREG(UART_BASE + UART_FIFO_REG, ch);
+	wait_xfered();
+}

target/linux/bmips/image/lzma-loader/src/cache.c

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * The cache manipulation routine has been taken from the U-Boot project.
+ *	(C) Copyright 2003
+ *	Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ */
+
+#include "cache.h"
+#include "cacheops.h"
+#include "config.h"
+#include "printf.h"
+
+#define cache_op(op,addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noreorder				\n"	\
+	"	.set	mips3\n\t				\n"	\
+	"	cache	%0, %1					\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+	unsigned long lsize = CONFIG_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size + (lsize - 1)) & ~(lsize - 1);
+
+	printf("blasting from 0x%08x to 0x%08x (0x%08x - 0x%08x)\n", start_addr, size, addr, aend);
+
+	while (1) {
+		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(Hit_Invalidate_I, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}

target/linux/bmips/image/lzma-loader/src/cache.h

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+void flush_cache(unsigned long start_addr, unsigned long size);
+
+#endif /* __CACHE_H */

target/linux/bmips/image/lzma-loader/src/cacheops.h

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Cache operations for the cache instruction.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef	__ASM_CACHEOPS_H
+#define	__ASM_CACHEOPS_H
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Load_Tag_I	0x04
+#define Index_Load_Tag_D	0x05
+#define Index_Store_Tag_I	0x08
+#define Index_Store_Tag_D	0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I	0x00
+#else
+#define Hit_Invalidate_I	0x10
+#endif
+#define Hit_Invalidate_D	0x11
+#define Hit_Writeback_Inv_D	0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D	0x0d
+#define Fill			0x14
+#define Hit_Writeback_I		0x18
+#define Hit_Writeback_D		0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_SI	0x06
+#define Index_Load_Tag_SD	0x07
+#define Index_Store_Tag_SI	0x0A
+#define Index_Store_Tag_SD	0x0B
+#define Create_Dirty_Excl_SD	0x0f
+#define Hit_Invalidate_SI	0x12
+#define Hit_Invalidate_SD	0x13
+#define Hit_Writeback_Inv_SD	0x17
+#define Hit_Writeback_SD	0x1b
+#define Hit_Set_Virtual_SI	0x1e
+#define Hit_Set_Virtual_SD	0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S	0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T	0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S	0x03
+#define Index_Load_Tag_S	0x07
+#define Index_Store_Tag_S	0x0B
+#define Hit_Invalidate_S	0x13
+#define Cache_Barrier		0x14
+#define Hit_Writeback_Inv_S	0x17
+#define Index_Load_Data_I	0x18
+#define Index_Load_Data_D	0x19
+#define Index_Load_Data_S	0x1b
+#define Index_Store_Data_I	0x1c
+#define Index_Store_Data_D	0x1d
+#define Index_Store_Data_S	0x1f
+
+#endif	/* __ASM_CACHEOPS_H */

target/linux/bmips/image/lzma-loader/src/config.h

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
+ *
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef _CONFIG_H_
+#define _CONFIG_H_
+
+#define CONFIG_ICACHE_SIZE	(32 * 1024)
+#define CONFIG_DCACHE_SIZE	(32 * 1024)
+#define CONFIG_CACHELINE_SIZE	16
+
+#endif /* _CONFIG_H_ */