Initial commit

target/linux/mpc85xx/Makefile

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2010 OpenWrt.org
+
+include $(TOPDIR)/rules.mk
+
+ARCH:=powerpc
+BOARD:=mpc85xx
+BOARDNAME:=Freescale MPC85xx
+CPU_TYPE:=8548
+FEATURES:=squashfs ramdisk nand
+SUBTARGETS:=p1010 p1020 p2020
+
+KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
+
+KERNELNAME:=zImage
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+	kmod-input-core kmod-input-gpio-keys kmod-button-hotplug \
+	kmod-leds-gpio swconfig kmod-ath9k wpad-basic-mbedtls kmod-usb2 \
+	uboot-envtools
+
+$(eval $(call BuildTarget))

target/linux/mpc85xx/base-files/etc/board.d/01_leds

@@ -0,0 +1,26 @@
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board=$(board_name)
+boardname="${board##*,}"
+
+board_config_update
+
+case $board in
+enterasys,ws-ap3715i)
+	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth0"
+	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth1"
+	;;
+extreme-networks,ws-ap3825i)
+	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
+	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth0"
+	;;
+hpe,msm460)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/mpc85xx/base-files/etc/board.d/02_network

@@ -0,0 +1,45 @@
+# Copyright (C) 2014-2015 OpenWrt.org
+
+. /lib/functions/uci-defaults.sh
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+aerohive,br200-wp)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	;;
+aerohive,hiveap-330|\
+enterasys,ws-ap3715i)
+	ucidef_set_interfaces_lan_wan "eth1" "eth0"
+	;;
+enterasys,ws-ap3710i)
+	ucidef_set_interface_lan "eth0"
+	ucidef_set_label_macaddr "$(mtd_get_mac_ascii cfg1 ethaddr)"
+	;;
+hpe,msm460)
+	ucidef_set_interface_lan "eth0"
+	;;	
+ocedo,panda)
+	ucidef_set_interface_wan "eth1"
+	ucidef_add_switch "switch0" \
+		"0:lan" "1:lan" "2:lan" "3:lan" "4:lan" "5:lan" "6:lan" "7:lan" "8u@eth0"
+	;;
+tplink,tl-wdr4900-v1)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
+	ucidef_set_interface_macaddr "wan" "$(macaddr_add $(mtd_get_mac_binary u-boot 0x4fc00) 1)"
+	;;
+watchguard,firebox-t10)
+	ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
+	;;
+*)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/mpc85xx/base-files/etc/board.d/05_compat-version

@@ -0,0 +1,15 @@
+
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+	tplink,tl-wdr4900-v1)
+		ucidef_set_compat_version "1.1"
+		;;
+esac
+
+board_config_flush
+
+exit 0

target/linux/mpc85xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+[ -e /lib/firmware/$FIRMWARE ] && exit 0
+
+. /lib/functions/caldata.sh
+
+board=$(board_name)
+
+case "$FIRMWARE" in
+"pci_wmac0.eeprom")
+	case $board in
+	tplink,tl-wdr4900-v1)
+		caldata_extract "caldata" 0x1000 0x800
+		ath9k_patch_mac $(mtd_get_mac_binary u-boot 0x4fc00)
+		;;
+	*)
+		caldata_die "board $board is not supported yet"
+		;;
+	esac
+	;;
+
+"pci_wmac1.eeprom")
+	case $board in
+	tplink,tl-wdr4900-v1)
+		caldata_extract "caldata" 0x5000 0x800
+		ath9k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x4fc00) -1)
+		;;
+	*)
+		caldata_die "board $board is not supported yet"
+		;;
+	esac
+	;;
+esac

target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/05-wifi-migrate

@@ -0,0 +1,63 @@
+#!/bin/sh
+
+# This must run before 10-wifi-detect
+
+
+[ "${ACTION}" = "add" ] || return
+
+
+. /lib/functions.sh
+
+
+check_radio()
+{
+	local cfg="$1" to="$2"
+
+	config_get path "$cfg" path
+
+	[ "$path" = "$to" ] && PATH_EXISTS=true
+}
+
+do_migrate_radio()
+{
+	local cfg="$1" from="$2" to="$3"
+
+	config_get path "$cfg" path
+
+	[ "$path" = "$from" ] || return
+
+	uci set "wireless.${cfg}.path=${to}"
+	WIRELESS_CHANGED=true
+
+	logger -t wifi-migrate "Updated path of wireless.${cfg} from '${from}' to '${to}'"
+}
+
+migrate_radio()
+{
+	local from="$1" to="$2"
+
+	config_load wireless
+
+	# Check if there is already a section with the target path: In this case, the system
+	# was already upgraded to a version without this migration script before; better bail out,
+	# as we can't be sure we don't break more than we fix.
+	PATH_EXISTS=false
+	config_foreach check_radio wifi-device "$to"
+	$PATH_EXISTS && return
+
+	config_foreach do_migrate_radio wifi-device "$from" "$to"
+}
+
+
+WIRELESS_CHANGED=false
+
+case "$(board_name)" in
+tplink,tl-wdr4900-v1)
+	migrate_radio 'ffe09000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0' 'ffe09000.pcie/pci9000:00/9000:00:00.0/9000:01:00.0'
+	migrate_radio 'ffe0a000.pcie/pci0001:02/0001:02:00.0/0001:03:00.0' 'ffe0a000.pcie/pcia000:02/a000:02:00.0/a000:03:00.0'
+	;;
+esac
+
+$WIRELESS_CHANGED && uci commit wireless
+
+exit 0

target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac

@@ -0,0 +1,34 @@
+#!/bin/ash
+
+[ "$ACTION" = "add" ] || exit 0
+
+PHYNBR=${DEVPATH##*/phy}
+
+[ -n "$PHYNBR" ] || exit 0
+
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+board=$(board_name)
+
+case "$board" in
+enterasys,ws-ap3715i)
+	[ "$PHYNBR" -eq 0 ] && mtd_get_mac_ascii cfg2 RADIOADDR1 > /sys${DEVPATH}/macaddress
+	[ "$PHYNBR" -eq 1 ] && mtd_get_mac_ascii cfg2 RADIOADDR0 > /sys${DEVPATH}/macaddress
+	;;
+enterasys,ws-ap3710i|\
+extreme-networks,ws-ap3825i)
+	mtd_get_mac_ascii cfg2 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress
+	;;
+hpe,msm460)
+	wifi_mac=$(mtd_get_mac_binary colubris-bid 0x1f9bd)
+	[ "$PHYNBR" -eq 0 ] && echo "$wifi_mac" > /sys${DEVPATH}/macaddress
+	[ "$PHYNBR" -eq 1 ] && echo "$(macaddr_add $wifi_mac 16)" > /sys${DEVPATH}/macaddress
+	;;
+ocedo,panda)
+	mtd_get_mac_ascii uboot-env0 wmac$(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress
+	;;
+sophos,red-15w-rev1)
+	mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress
+	;;
+esac

target/linux/mpc85xx/base-files/etc/uci-defaults/05_fix-compat-version

@@ -0,0 +1,11 @@
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+case "$(board_name)" in
+aerohive,hiveap-330)
+	uci set system.@system[0].compat_version="2.0"
+	uci commit system
+	;;
+esac
+
+exit 0

target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx

@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+
+mpc85xx_set_preinit_iface() {
+	ifname=eth0
+}
+
+boot_hook_add preinit_main mpc85xx_set_preinit_iface

target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh

@@ -0,0 +1,22 @@
+. /lib/functions.sh
+. /lib/functions/system.sh
+
+preinit_set_mac_address() {
+	case $(board_name) in
+	enterasys,ws-ap3710i)
+		ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)
+		;;
+	enterasys,ws-ap3715i|\
+	extreme-networks,ws-ap3825i)
+		ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)
+		ip link set dev eth1 address $(mtd_get_mac_ascii cfg1 eth1addr)
+		;;
+	watchguard,firebox-t10)
+		ip link set dev eth0 address "$(mtd_get_mac_text "device_id" 0x1830)"
+		ip link set dev eth1 address "$(mtd_get_mac_text "device_id" 0x1844)"
+		ip link set dev eth2 address "$(mtd_get_mac_text "device_id" 0x1858)"
+		;;
+	esac
+}
+
+boot_hook_add preinit_main preinit_set_mac_address

target/linux/mpc85xx/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+#
+
+PART_NAME=firmware
+REQUIRE_IMAGE_METADATA=1
+
+platform_check_image() {
+	return 0
+}
+
+platform_do_upgrade() {
+	local board=$(board_name)
+
+	case "$board" in
+	hpe,msm460|\
+	ocedo,panda|\
+	sophos,red-15w-rev1|\
+	watchguard,firebox-t10)
+		nand_do_upgrade "$1"
+		;;
+	*)
+		default_do_upgrade "$1"
+		;;
+	esac
+}

target/linux/mpc85xx/config-6.1

@@ -0,0 +1,295 @@
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_ADVANCED_OPTIONS is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=11
+CONFIG_ARCH_MMAP_RND_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SPLIT_ARG64=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
+CONFIG_ASN1=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOOKE=y
+CONFIG_BOOKE_OR_40x=y
+CONFIG_BOOKE_WDT=y
+# CONFIG_BR200_WP is not set
+# CONFIG_BSC9131_RDB is not set
+# CONFIG_BSC9132_QDS is not set
+# CONFIG_C293_PCIE is not set
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_COMMON_CLK is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_CORENET_GENERIC is not set
+# CONFIG_CPM2 is not set
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CRYPTO_AES_PPC_SPE is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+# CONFIG_CRYPTO_MD5_PPC is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_SHA1_PPC is not set
+# CONFIG_CRYPTO_SHA1_PPC_SPE is not set
+# CONFIG_CRYPTO_SHA256_PPC_SPE is not set
+CONFIG_DATA_SHIFT=24
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_E500_CPU=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_FIREBOX_T10 is not set
+CONFIG_FIXED_PHY=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_FSL_FMAN is not set
+CONFIG_FSL_LBC=y
+CONFIG_FSL_PCI=y
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_SOC_BOOKE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GEN_RTC=y
+# CONFIG_GE_IMP3A is not set
+CONFIG_GIANFAR=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HIVEAP_330 is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_MPC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_KERNEL_START=0xc0000000
+# CONFIG_KSI8560 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOWMEM_CAM_NUM=9
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_LXT_PHY=y
+# CONFIG_MATH_EMULATION is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_PAGE_SIZE=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MPC8536_DS is not set
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_DS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_RDB is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_MSGR is not set
+CONFIG_MPIC_TIMER=y
+CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MVME2500 is not set
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=1
+CONFIG_NR_IRQS=512
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_QORIQ_EFUSE is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND=y
+# CONFIG_P1010_RDB is not set
+# CONFIG_P1022_DS is not set
+# CONFIG_P1022_RDK is not set
+# CONFIG_P1023_RDB is not set
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANDA is not set
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYSICAL_ALIGN=0x04000000
+CONFIG_PHYSICAL_START=0x00000000
+# CONFIG_PHYS_64BIT is not set
+# CONFIG_PMU_SYSFS is not set
+# CONFIG_PPA8548 is not set
+CONFIG_PPC=y
+CONFIG_PPC32=y
+# CONFIG_PPC64 is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+CONFIG_PPC_ADV_DEBUG_DACS=2
+CONFIG_PPC_ADV_DEBUG_DVCS=0
+CONFIG_PPC_ADV_DEBUG_IACS=2
+CONFIG_PPC_ADV_DEBUG_REGS=y
+CONFIG_PPC_BARRIER_NOSPEC=y
+# CONFIG_PPC_BOOK3S_32 is not set
+CONFIG_PPC_DOORBELL=y
+CONFIG_PPC_E500=y
+# CONFIG_PPC_E500MC is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PPC_KUAP=y
+# CONFIG_PPC_KUAP_DEBUG is not set
+CONFIG_PPC_KUEP=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_PAGE_SHIFT=12
+# CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT is not set
+# CONFIG_PPC_QEMU_E500 is not set
+CONFIG_PPC_SMP_MUXED_IPI=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_PPC_WERROR=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QE_GPIO=y
+CONFIG_QUICC_ENGINE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+# CONFIG_RED_15W_REV1 is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SCOM_DEBUGFS is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_QE is not set
+# CONFIG_SOCRATES is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPE=y
+CONFIG_SPE_POSSIBLE=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_ESPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+# CONFIG_STATIC_CALL_SELFTEST is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_STX_GP3 is not set
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_TARGET_CPU="8540"
+CONFIG_TARGET_CPU_BOOL=y
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SHIFT=13
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+# CONFIG_TL_WDR4900_V1 is not set
+# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8548 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_TWR_P102x is not set
+CONFIG_UCC=y
+CONFIG_UCC_FAST=y
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_TX_ON_DEMAND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_VDSO32=y
+# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WS_AP3710I is not set
+# CONFIG_WS_AP3715I is not set
+# CONFIG_WS_AP3825I is not set
+# CONFIG_XES_MPC85xx is not set
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_POWERPC=y

target/linux/mpc85xx/config-6.6

@@ -0,0 +1,308 @@
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_ADVANCED_OPTIONS is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_DEFAULT_COHERENT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=11
+CONFIG_ARCH_MMAP_RND_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_BITS_MIN=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SPLIT_ARG64=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
+CONFIG_ASN1=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOOKE=y
+CONFIG_BOOKE_OR_40x=y
+CONFIG_BOOKE_WDT=y
+# CONFIG_BR200_WP is not set
+# CONFIG_BSC9131_RDB is not set
+# CONFIG_BSC9132_QDS is not set
+# CONFIG_C293_PCIE is not set
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_COMMON_CLK is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_CORENET_GENERIC is not set
+# CONFIG_CPM2 is not set
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CRYPTO_AES_PPC_SPE is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+# CONFIG_CRYPTO_MD5_PPC is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_SHA1_PPC is not set
+# CONFIG_CRYPTO_SHA1_PPC_SPE is not set
+# CONFIG_CRYPTO_SHA256_PPC_SPE is not set
+CONFIG_DATA_SHIFT=24
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_E500_CPU=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_FIREBOX_T10 is not set
+CONFIG_FIXED_PHY=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_FSL_FMAN is not set
+CONFIG_FSL_LBC=y
+CONFIG_FSL_PCI=y
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_SOC_BOOKE=y
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GEN_RTC=y
+# CONFIG_GE_IMP3A is not set
+CONFIG_GIANFAR=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HIVEAP_330 is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_MPC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_KERNEL_START=0xc0000000
+# CONFIG_KSI8560 is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOWMEM_CAM_NUM=9
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_LXT_PHY=y
+# CONFIG_MATH_EMULATION is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_PAGE_SIZE=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MPC8536_DS is not set
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_DS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_RDB is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_MSGR is not set
+CONFIG_MPIC_TIMER=y
+CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MVME2500 is not set
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=1
+CONFIG_NR_IRQS=512
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_QORIQ_EFUSE is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_GPIO_MM_GPIOCHIP=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND=y
+# CONFIG_P1010_RDB is not set
+# CONFIG_P1022_DS is not set
+# CONFIG_P1022_RDK is not set
+# CONFIG_P1023_RDB is not set
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANDA is not set
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYSICAL_ALIGN=0x04000000
+CONFIG_PHYSICAL_START=0x00000000
+# CONFIG_PHYS_64BIT is not set
+# CONFIG_PMU_SYSFS is not set
+# CONFIG_PPA8548 is not set
+CONFIG_PPC=y
+CONFIG_PPC32=y
+# CONFIG_PPC64 is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+CONFIG_PPC_ADV_DEBUG_DACS=2
+CONFIG_PPC_ADV_DEBUG_DVCS=0
+CONFIG_PPC_ADV_DEBUG_IACS=2
+CONFIG_PPC_ADV_DEBUG_REGS=y
+CONFIG_PPC_BARRIER_NOSPEC=y
+# CONFIG_PPC_BOOK3S_32 is not set
+CONFIG_PPC_DOORBELL=y
+CONFIG_PPC_E500=y
+# CONFIG_PPC_E500MC is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PPC_KUAP=y
+# CONFIG_PPC_KUAP_DEBUG is not set
+CONFIG_PPC_KUEP=y
+CONFIG_PPC_MMU_NOHASH=y
+# CONFIG_PPC_P2020 is not set
+CONFIG_PPC_PAGE_SHIFT=12
+# CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT is not set
+# CONFIG_PPC_QEMU_E500 is not set
+CONFIG_PPC_SMP_MUXED_IPI=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_PPC_WERROR=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QE_GPIO=y
+CONFIG_QUICC_ENGINE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+# CONFIG_RED_15W_REV1 is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SCOM_DEBUGFS is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_QE is not set
+CONFIG_SMT_NUM_THREADS_DYNAMIC=y
+# CONFIG_SOCRATES is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPE=y
+CONFIG_SPE_POSSIBLE=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_ESPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_STATIC_CALL_SELFTEST is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_STX_GP3 is not set
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_TARGET_CPU="8540"
+CONFIG_TARGET_CPU_BOOL=y
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SHIFT=13
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+# CONFIG_TL_WDR4900_V1 is not set
+# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8548 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_TWR_P102x is not set
+CONFIG_UCC=y
+CONFIG_UCC_FAST=y
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_TX_ON_DEMAND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_VDSO32=y
+# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WS_AP3710I is not set
+# CONFIG_WS_AP3715I is not set
+# CONFIG_WS_AP3825I is not set
+# CONFIG_XES_MPC85xx is not set
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_POWERPC=y

target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts

@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Device Tree Source
+ *
+ * Based on: Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+/ {
+	model = "Aerohive BR200-WP";
+	compatible = "aerohive,br200-wp";
+
+	chosen {
+		bootargs = "console=ttyS0,9600";
+		bootargs-override = "console=ttyS0,9600 noinitrd";
+	};
+
+	aliases {
+		led-boot = &led_attention;
+		led-failsafe = &led_attention;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					reg = <0x40000 0x40000>;
+					label = "initramfs";
+				};
+
+				partition@80000 {
+					reg = <0x80000 0x27c0000>;
+					label = "rootfs";
+				};
+
+				partition@2840000 {
+					reg = <0x2840000 0x800000>;
+					label = "kernel";
+				};
+
+				partition@3040000 {
+					reg = <0x3040000 0xec0000>;
+					label = "stock-jffs2";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_0: macaddr@0 {
+							compatible = "mac-base";
+							reg = <0x0 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				firmware@0 {
+					reg = <0x0 0x3040000>;
+					label = "firmware";
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				reg = <0x10>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&phy_port1>;
+						nvmem-cells = <&macaddr_hwinfo_0 2>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&phy_port2>;
+						nvmem-cells = <&macaddr_hwinfo_0 3>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&phy_port3>;
+						nvmem-cells = <&macaddr_hwinfo_0 4>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan4";
+						phy-handle = <&phy_port4>;
+						nvmem-cells = <&macaddr_hwinfo_0 5>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "wan";
+						phy-handle = <&phy_port5>;
+						nvmem-cells = <&macaddr_hwinfo_0 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@6 {
+						reg = <6>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 0>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+				  0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000
+				  0x2000000 0x0 0xc0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			ath9k: wifi@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				nvmem-cells = <&macaddr_hwinfo_0 16>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: led-0 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_status: led-1 {
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "/soc@ffe00000/serial@4500";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			clock-frequency = <0x2756cd00>;
+			bus-frequency = <0x13ab6680>;
+			timebase-frequency = <0x2756cd0>;
+		};
+	};
+
+	memory {
+		reg = <0x00 0x00 0x00 0x10000000>;
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <0x13ab668>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <0x13ab6680>;
+
+		serial@4500 {
+			clock-frequency = <0x13ab6680>;
+		};
+
+		serial@4600 {
+			clock-frequency = <0x13ab6680>;
+		};
+	};
+
+	pcie@ffe09000 {
+		clock-frequency = <0x1fca055>;
+	};
+
+	pcie@ffe0a000 {
+		clock-frequency = <0x1fca055>;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts

@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Watchguard Firebox T10";
+	compatible = "watchguard,firebox-t10";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		bootargs-override = "console=ttyS0,115200";
+	};
+
+	aliases {
+		spi0 = &spi0;
+		led-boot = &led_mode;
+		led-failsafe = &led_failover;
+		led-running = &led_mode;
+		led-upgrade = &led_attention;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: attention_orange {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			label = "orange:attention";
+		};
+
+		status_red {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led_mode: mode_green {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "green:mode";
+		};
+
+		led_failover: failover_green {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "green:failover";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			rtc@30 {
+				compatible = "sii,s35390a";
+				reg = <0x30>;
+			};
+		};
+
+		spi0: spi@7000 {
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					uboot: partition@0 {
+						reg = <0x0 0x90000>;
+						label = "u-boot";
+						read-only;
+					};
+
+					partition@90000 {
+						reg = <0x90000 0x10000>;
+						label = "u-boot-env";
+					};
+
+					partition@a0000 {
+						reg = <0xa0000 0x20000>;
+						label = "cfgxxx";
+						read-only;
+					};
+
+					partition@c0000 {
+						reg = <0xc0000 0x40000>;
+						label = "device_id";
+						read-only;
+					};
+				};
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+			phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			phy3: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy1: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		mdio@26000 {
+			tbi_phy2: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@b1000 {
+			tbi-handle = <&tbi_phy1>;
+			phy-handle = <&phy2>;
+			phy-connection-type = "sgmii";
+		};
+
+		enet2: ethernet@b2000 {
+			tbi-handle = <&tbi_phy2>;
+			phy-handle = <&phy3>;
+			phy-connection-type = "sgmii";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			status = "disabled";
+		};
+
+		can0: can@1c000 {
+			status = "disabled";
+		};
+
+		can1: can@1d000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		status = "disabled";
+	};
+
+	ifc: ifc@ffe1e000 {
+		reg = <0x0 0xffe1e000 0 0x2000>;
+
+		/* NOR, NAND Flashes and CPLD on board */
+		ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+			0x1 0x0 0x0 0xff800000 0x00010000
+			0x3 0x0 0x0 0xffb00000 0x00000020>;
+
+		nand@100000000 {
+			compatible = "fsl,ifc-nand";
+			reg = <0x1 0x0 0x10000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/*
+				 * Original partition layout:
+				 * 0x000000000000-0x000000020000 : "NAND (RW) WG DTB Image"
+				 * 0x000000020000-0x000000520000 : "NAND (RW) WG SYSA Kernel"
+				 * 0x000000520000-0x000007f00000 : "NAND (RW) WG SYSA_CODE"
+				 * 0x000007f00000-0x000008400000 : "NAND (RW) WG SYSB Kernel"
+				 * 0x000008400000-0x000009c00000 : "NAND (RW) WG SYSB_CODE"
+				 * 0x000009c00000-0x00000a100000 : "NAND (RW) WG SYSA2 Kernel"
+				 * 0x00000a100000-0x000011ae0000 : "NAND (RW) WG SYSA_CODE2"
+				 * 0x000011ae0000-0x000020000000 : "NAND (RW) WG SYSA_DATA"
+				 */
+
+				partition@0 {
+					reg = <0x0 0x20000>;
+					label = "wg-dtb";
+					read-only;
+				};
+
+				partition@20000 {
+					reg = <0x20000 0x500000>;
+					label = "kernel";
+				};
+
+				partition@520000 {
+					reg = <0x520000 0x79e0000>;
+					label = "wg-sysa-rootfs";
+					read-only;
+				};
+
+				partition@7f00000 {
+					reg = <0x7f00000 0x500000>;
+					label = "wg-sysb-kernel";
+					read-only;
+				};
+
+				partition@8400000 {
+					reg = <0x8400000 0x1800000>;
+					label = "wg-sysb-rootfs";
+					read-only;
+				};
+
+				partition@9c00000 {
+					reg = <0x9c00000 0x500000>;
+					label = "wg-sysa2-kernel";
+					read-only;
+				};
+
+				partition@a100000 {
+					reg = <0xa100000 0x79e0000>;
+					label = "wg-sysa2-rootfs";
+					read-only;
+				};
+
+				partition@11ae0000 {
+					reg = <0x11ae0000 0xe520000>;
+					label = "ubi";
+				};
+			};
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"

target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts

@@ -0,0 +1,424 @@
+/*
+ * Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Aerohive HiveAP-330";
+	compatible = "aerohive,hiveap-330";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_fault_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_fault_red;
+		label-mac-device = &enet0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		/*
+		 * not yet implemented.
+		 * stdout-path = &serial0 ":9600n8";
+		 * <https://www.spinics.net/lists/devicetree-compiler/msg02487.html>
+		 *
+		 * this should work... but it doesn't because CONFIG_CMDLINE in our
+		 * OpenWrt's target config sets "console=ttyS0,115200"
+		 * stdout-path = "/soc@ffe00000/serial@4500:9600n8";
+		 */
+
+		bootargs = "console=ttyS0,9600n8";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			status = "okay";
+			clock-frequency = <533333328>; /* 533.33 MHz */
+			bus-frequency = <266666664>;  /* 266.66 MHz */
+			timebase-frequency = <33333333>; /* 33.33 MHz */
+		};
+
+		PowerPC,P1020@1 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			cpu-release-addr = <0x00 0xffff240>;
+			enable-method = "spin-table";
+			status = "disabled";
+			clock-frequency = <533333328>;
+			bus-frequency = <266666664>;
+			timebase-frequency = <33333333>;
+		};
+	};
+
+	memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		reg = <0x00 0x00 0x00 0x10000000>;
+		device_type = "memory";
+	};
+
+	/*
+	 * Usually, u-boot provided /memreserve/ properties by adding them during boot.
+	 * these have been converted to reserved-memory entries.
+	 */
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * /memreserve/   0x0000000000ffa000 0x0000000000004000;
+		 * The kernel complains when booting:
+		 *
+		 * | OF: fdt: Reserved memory: failed to reserve memory for node
+		 *		'firmware@ffa000': base 0x00ffa000, size 0 MiB
+		 *
+		 * But this likely uboot's bootargs + modified DTB. And if so, we don't care.
+		 * This is because we rely on our own dtb that's in the simpleImage.
+		 *
+		 * Note: This is backed up by u-boot. just before the kernel executes
+		 *	 it prints this final line:
+		 *	 |  Loading Device Tree to 00ff9000, end 00fff1c4 ... OK
+		 *
+		 * firmware@ffa000 {
+		 *	reg = <0x0 0xffa000 0x0 0x4000>;
+		 *	no-map;
+		 * };
+		 */
+
+		// /memreserve/   0x000000000fe2f000 0x0000000000000021;
+		firmware@fe2f000 {
+			reg = <0x0 0xfe2f000 0x0 0x21>;
+			no-map;
+		};
+
+		/*
+		 * /memreserve/   0x000000000ffff000 0x0000000000001000;
+		 * that's the spin-table - see second CPU core binding.
+		 */
+		firmware@ffff000 {
+			reg = <0x0 0xffff000 0x0 0x1000>;
+			no-map;
+		};
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		bus-frequency = <16666666>; /* 16.66 MHz */
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				firmware@0 {
+					reg = <0x0 0x3f00000>;
+					label = "firmware";
+					/*
+					 * This unknown/invalid compatible prevents
+					 * openwrt's mtdsplit_fit to go off a tangent if it
+					 * finds a magic value inside the uncompressed kernel
+					 * at a blocksized aligned place.
+					 */
+					compatible = "areohive,hiveap-330-image";
+				};
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					compatible = "openwrt,uimage", "denx,uimage";
+					reg = <0x40000 0x3ec0000>;
+					label = "kernel";
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_0: macaddr@0 {
+							compatible = "mac-base";
+							reg = <0x0 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+		bus-frequency = <266666664>;
+
+		spi0: spi@7000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			temperature-sensor@1 {
+				compatible = "ti,tmp125";
+				reg = <1>;
+				spi-max-frequency = <5000000>;
+			};
+		};
+
+		i2c@3100 {
+			tpm@29 {
+				compatible = "atmel,at97sc3204t";
+				reg = <0x29>;
+			};
+
+			lp5521@32 {
+				compatible = "national,lp5521";
+				reg = <0x32>;
+				clock-mode = /bits/ 8 <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+#if 1
+				led_fault_red: led@0 {
+					reg = <0>;
+					chan-name = "fault:red";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_RED>;
+					function = LED_FUNCTION_FAULT;
+				};
+				led_power_green: led@1 {
+					reg = <1>;
+					chan-name = "power:green";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_POWER;
+				};
+				led@2{
+					reg = <2>;
+					chan-name = "blue";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_BLUE>;
+				};
+#else
+				/*
+				 * openwrt isn't ready to handle multi-intensity leds yet
+				 * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
+				 * # echo 255 > /sys/class/leds/tricolor/brightness
+				 */
+
+				rgbled-0 {
+					function = LED_FUNCTION_POWER;
+					color = <LED_COLOR_ID_RGB>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_RED>;
+					};
+					led@1 {
+						reg = <1>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_GREEN>;
+					};
+					led@2{
+						reg = <2>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_BLUE>;
+					};
+				};
+#endif
+			};
+
+			eeprom@51 {
+				/*
+				 * 1Kbit I2C/SMBus EEPROM with SHA-1 Engine
+				 * Aerohive calls it "dallas".
+				 */
+				compatible = "adi,ds28cn01";
+				reg = <0x51>;
+				read-only;
+			};
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				/* interrupts = <3 1 0 0>; */
+				reg = <0x1>;
+			};
+
+			phy1: ethernet-phy@1 {
+				/* interrupts = <2 1 0 0>; */
+				reg = <0x2>;
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			rx-stash-idx = <0x00>;
+			rx-stash-len = <0x60>;
+			bd-stash;
+			status = "okay";
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 0>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			rx-stash-idx = <0x00>;
+			rx-stash-len = <0x60>;
+			bd-stash;
+			status = "okay";
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 1>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>,
+			 <0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000>,
+				 <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
+			 <0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000>,
+				 <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+&serial0 {
+	clock-frequency = <266666664>;
+};
+
+&serial1 {
+	clock-frequency = <266666664>;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/msm460.dts

@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Hewlett-Packard MSM460";
+	compatible = "hpe,msm460";
+
+	aliases {
+		led-boot = &system_green;
+		led-failsafe = &system_green;
+		led-running = &system_green;
+		led-upgrade = &system_green;
+		label-mac-device = &enet0;
+	};
+
+	chosen {
+		/* Needed for initramfs */
+		bootargs-override = "console=ttyS0,115200 ubi.mtd=5,2048";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+		nand@1,0 {
+			compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+			reg = <0x1 0x0 0x40000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xc0000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@c0000 {
+					reg = <0xc0000 0x40000>;
+					label = "colubris-bid";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_1f822: macaddr@1f822 {
+							/* ETH */
+							compatible = "mac-base";
+							reg = <0x1f822 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_hwinfo_1f9bd: macaddr@1f9bd {
+							/* WLAN */
+							compatible = "mac-base";
+							reg = <0x1f9bd 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				/* uenv{0,1} and ubi occupy kernel and slash partitions */
+
+				partition@100000 {
+					reg = <0x100000 0x80000>;
+					label = "uboot-env0";
+				};
+
+				partition@180000 {
+					reg = <0x180000 0x80000>;
+					label = "uboot-env1";
+				};
+
+				partition@200000 {
+					reg = <0x200000 0x300000>;
+					label = "reserved";
+				};
+
+				partition@500000 {
+					reg = <0x500000 0x5f00000>;
+					label = "ubi";
+				};
+
+				partition@6500000 {
+					reg = <0x6500000 0x400000>;
+					label = "pool";
+					read-only;
+				};
+
+				partition@6900000 {
+					reg = <0x6900000 0x15e0000>;
+					label = "flash";
+					read-only;
+				};
+
+				partition@7ee0000 {
+					reg = <0x7ee0000 0x20000>;
+					label = "pf";
+					read-only;
+				};
+
+				/* BBT is at the end of the flash - 100000@7f00000 */
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x0>;
+				reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&phy0>;
+			nvmem-cells = <&macaddr_hwinfo_1f822 0>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: power {
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			default-state = "on";
+		};
+
+		lan {
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+		};
+
+		radio1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <1>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		radio2 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <2>;
+			linux,default-trigger = "phy1tpt";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset-btn";
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+/include/ "fsl/p1020si-post.dtsi"

target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts

@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "OCEDO Panda";
+	compatible = "ocedo,panda";
+
+	aliases {
+		led-boot = &system_blue;
+		led-failsafe = &system_blue;
+		led-running = &system_blue;
+		led-upgrade = &system_blue;
+	};
+
+	chosen {
+		/* Needed for initramfs */
+		bootargs-override = "console=ttyS0,115200 ubi.mtd=3,2048";
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+		nand@100000000 {
+			compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+			reg = <0x1 0x0 0x40000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xa0000>;
+					label = "uboot";
+					read-only;
+				};
+
+				partition@a0000 {
+					reg = <0xa0000 0x20000>;
+					label = "uboot-env0";
+				};
+
+				partition@c0000 {
+					reg = <0xc0000 0x40000>;
+					label = "uboot-env1";
+				};
+
+				partition@100000 {
+					reg = <0x100000 0xff00000>;
+					label = "ubi";
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			rtc@68 {
+				compatible = "dallas,ds1339";
+				reg = <0x68>;
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@8 {
+				reg = <0x8>;
+			};
+
+			phy1: ethernet-phy@9 {
+				reg = <0x9>;
+			};
+
+			switch0: ethernet-phy@0 {
+				reg = <0x0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						label = "lan1";
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "lan2";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan3";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan4";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan5";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "lan6";
+					};
+
+					port@6 {
+						reg = <6>;
+						label = "lan7";
+					};
+
+					port@7 {
+						reg = <7>;
+						label = "lan8";
+					};
+
+					port@8 {
+						reg = <8>;
+						label = "cpu";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy0: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			tbi_phy1: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&switch0>;
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-connection-type = "sgmii";
+			phy-handle = <&phy0>;
+
+			tbi-handle = <&tbi_phy0>;
+		};
+
+		enet2: ethernet@b2000 {
+			phy-connection-type = "sgmii";
+			phy-handle = <&phy1>;
+
+			tbi-handle = <&tbi_phy1>;
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power {
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+			label = "panda:green:power";
+			default-state = "on";
+		};
+
+		wlan0 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "panda:yellow:wlan0";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wlan1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+			label = "panda:red:wlan1";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		tbd_orange {
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			label = "panda:orange:tbd";
+		};
+
+		system_blue: system {
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "panda:blue:system";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+/include/ "fsl/p1020si-post.dtsi"
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Sophos RED 15w Rev.1";
+	compatible = "sophos,red-15w-rev1";
+
+	aliases {
+		led-boot = &system_green;
+		led-failsafe = &system_red;
+		led-running = &system_green;
+		led-upgrade = &system_red;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: system_green {
+			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+			label = "red-15w-rev1:green:system";
+		};
+
+		system_red: system_red {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "red-15w-rev1:red:system";
+		};
+
+		router {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:router";
+		};
+
+		internet {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:internet";
+		};
+
+		tunnel {
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:tunnel";
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			eeprom@50 {
+				compatible = "st,24c256";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@3100 {
+			eeprom@52 {
+				compatible = "atmel,24c01";
+				reg = < 0x52 >;
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy0>;
+			phy-connection-type = "sgmii";
+
+			tbi-handle = <&tbi_phy>;
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+		reg = <0x0 0xffe1e000 0 0x2000>;
+
+		/* NOR, NAND Flashes and CPLD on board */
+		ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+			0x1 0x0 0x0 0xff800000 0x00010000
+			0x3 0x0 0x0 0xffb00000 0x00000020>;
+
+		nand@100000000 {
+			compatible = "fsl,ifc-nand";
+			reg = <0x1 0x0 0x10000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/*
+				 * Original partition layout:
+				 * 0x000000000000-0x000000100000 : "NAND U-Boot Image"
+				 * 0x000000100000-0x000000200000 : "NAND U-Boot Environment"
+				 * 0x000000200000-0x000000300000 : "Provisioning"
+				 *  - OS-Image 1
+				 * 0x000000300000-0x000000400000 : "fdt1"
+				 * 0x000000400000-0x000000c00000 : "uimage1"
+				 * 0x000000c00000-0x000001c00000 : "rootfs1"
+				 *  - OS-Image 2
+				 * 0x000001c00000-0x000001d00000 : "fdt2"
+				 * 0x000001d00000-0x000002500000 : "uimage2"
+				 * 0x000002500000-0x000003500000 : "rootfs2"
+				 *  - Empty
+				 * 0x000003500000-0x000008000000 : "data"
+				 */
+
+				partition@0 {
+					reg = <0x0 0x100000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@100000 {
+					reg = <0x100000 0x100000>;
+					label = "u-boot-env";
+				};
+
+				partition@200000 {
+					reg = <0x200000 0x100000>;
+					label = "provisioning";
+					read-only;
+				};
+
+				oem-partition@300000 {
+					reg = <0x300000 0x1900000>;
+					label = "sophos-os1";
+
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						reg = <0x0 0x800000>;
+						label = "kernel";
+					};
+
+					partition@800000 {
+						reg = <0x800000 0x7500000>;
+						label = "ubi";
+					};
+				};
+
+				oem-partition@1c00000 {
+					reg = <0x1c00000 0x1900000>;
+					label = "sophos-os2";
+				};
+
+				oem-partition@3500000 {
+					reg = <0x3500000 0x4b00000>;
+					label = "sophos-data";
+				};
+			};
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts

@@ -0,0 +1,379 @@
+/*
+ * TP-Link TL-WDR4900 v1 Device Tree Source
+ *
+ * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "TP-Link TL-WDR4900 v1";
+	compatible = "tplink,tl-wdr4900-v1";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+/*
+		stdout-path = "/soc@ffe00000/serial@4500";
+*/
+	};
+
+	aliases {
+		spi0 = &spi0;
+		led-boot = &system_green;
+		led-failsafe = &system_green;
+		led-running = &system_green;
+		led-upgrade = &system_green;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		spi0: spi@7000 {
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					uboot: partition@0 {
+						reg = <0x0 0x0050000>;
+						label = "u-boot";
+						read-only;
+
+						nvmem-layout {
+							compatible = "fixed-layout";
+							#address-cells = <1>;
+							#size-cells = <1>;
+
+							macaddr_uboot_4fc00: macaddr@4fc00 {
+								reg = <0x4fc00 0x6>;
+							};
+						};
+					};
+
+					partition@50000 {
+						reg = <0x00050000 0x00010000>;
+						label = "dtb";
+						read-only;
+					};
+
+					partition@60000 {
+						compatible = "tplink,firmware";
+						reg = <0x00060000 0x00f80000>;
+						label = "firmware";
+					};
+
+					partition@fe0000 {
+						reg = <0x00fe0000 0x00010000>;
+						label = "config";
+						read-only;
+					};
+
+					partition@ff0000 {
+						reg = <0x00ff0000 0x00010000>;
+						label = "caldata";
+						read-only;
+					};
+				};
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				reg = <0x10>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "wan";
+						phy-handle = <&phy_port1>;
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan1";
+						phy-handle = <&phy_port2>;
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan2";
+						phy-handle = <&phy_port3>;
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan3";
+						phy-handle = <&phy_port4>;
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "lan4";
+						phy-handle = <&phy_port5>;
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_uboot_4fc00>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			status = "disabled";
+		};
+
+		can0: can@1c000 {
+			status = "disabled";
+		};
+
+		can1: can@1d000 {
+			status = "disabled";
+		};
+
+		ptp_clock@b0e00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0xb0e00 0xb0>;
+			interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+			fsl,cksel       = <1>;
+			fsl,tclk-period	= <5>;
+			fsl,tmr-prsc	= <2>;
+			fsl,tmr-add	= <0xcccccccd>;
+			fsl,tmr-fiper1	= <0x3b9ac9fb>; /* 1PPS */
+			fsl,tmr-fiper2	= <0x00018696>;
+			fsl,max-adj	= <249999999>;
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0 0xffe09000 0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+		status = "disabled";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: system {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			label = "tp-link:blue:system";
+		};
+
+		usb1 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			label = "tp-link:green:usb1";
+		};
+
+		usb2 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "tp-link:green:usb2";
+		};
+
+		usbpower {
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			label = "tp-link:usb:power";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		rfkill {
+			label = "RFKILL switch";
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1010@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <49999999>;
+			clock-frequency = <799999992>;
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x8000000>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+};
+
+/*
+ * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
+ * related to the P1010.
+ *
+ * NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
+ * datasheet states that the P1014 does not include the accelerated crypto
+ * module (CAAM/SEC4) which is present in the P1010.
+ *
+ * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
+ * SEC4 module, but states that SoCs with System Version Register values
+ * 0x80F10110 or 0x80F10120 do not have the security feature.
+ *
+ * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
+ * as: core rev 1.0, "P1014 (without security)".
+ *
+ * The SVR value is reported by uboot on the serial console.
+ */
+
+/ {
+	soc: soc@ffe00000 {
+		/delete-node/ crypto@30000; /* Pulled in by p1010si-post */
+	};
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts

@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Enterasys WS-AP3710i";
+	compatible = "enterasys,ws-ap3710i";
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:radio1";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wifi2 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:radio2";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:power";
+		};
+
+		led_power_red: power_red {
+			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:red:power";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xee000000 0x2000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x2000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					compatible = "denx,uimage";
+					reg = <0x0 0x1d80000>;
+					label = "firmware";
+				};
+
+				partition@1d80000 {
+					reg = <0x1d80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@1e00000 {
+					reg = <0x1e00000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+
+				partition@1f00000 {
+					reg = <0x1f00000 0x20000>;
+					label = "cfg2";
+					read-only;
+				};
+
+				partition@1f20000 {
+					reg = <0x1f20000 0x20000>;
+					label = "cfg1";
+					read-only;
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy4: ethernet-phy@4 {
+				reg = <0x4>;
+				reset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&phy4>;
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+			      0x00 0x100000 0x42000000 0x00 0x00 0x00
+			      0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+			      0xffe00000 0x00 0x100000 0x42000000
+			      0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+};
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1020@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff280>;
+			status = "okay";
+			enable-method = "spin-table";
+		};
+
+		PowerPC,P1020@1 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff2a0>;
+			status = "disabled";
+			enable-method = "spin-table";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpu1-bootpage@ff00000 {
+			/* Reserve upper 1 MB for second-core-bootpage */
+			reg = <0x0 0xff00000 0x0 0x100000>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <24999999>;
+	};
+};
+
+&enet0 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+&enet2 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts

@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Enterasys WS-AP3715i";
+	compatible = "enterasys,ws-ap3715i";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+	
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "green:radio1";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		wifi2 {
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "green:radio2";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_power_red: power_red {
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		lan1_red {
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
+			label = "red:lan1";
+		};
+
+		lan1_green {
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
+			label = "green:lan1";
+		};
+
+		lan2_red {
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
+			label = "red:lan2";
+		};
+
+		lan2_green {
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
+			label = "green:lan2";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x1>;
+			};
+
+			phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+
+			label = "lan1";
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy2>;
+			phy-connection-type = "sgmii";
+
+			tbi-handle = <&tbi_phy>;
+
+			label = "lan2";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0 0xffe09000 0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			wifi@0,0 {
+				compatible = "pci168c,0033";
+				reg = <0x0 0 0 0 0>;
+				ieee80211-freq-limit = <2400000 2500000>;
+			};
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+			
+			wifi@0,0 {
+				compatible = "pci168c,0033";
+				reg = <0x0 0 0 0 0>;
+				ieee80211-freq-limit = <5000000 6000000>;
+			};
+		};
+	};
+};
+
+&soc {
+	led_spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <100000>;
+		};
+	};
+
+	spi0: spi@7000 {
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <25000000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xa0000>;
+					label = "boot-bak";
+					read-only;
+				};
+
+				partition@a0000 {
+					reg = <0xa0000 0xa0000>;
+					label = "boot-pri";
+					read-only;
+				};
+
+				partition@120000 {
+					reg = <0x120000 0x10000>;
+					label = "cfg1";
+					read-only;
+				};
+
+				partition@130000 {
+					reg = <0x130000 0x10000>;
+					label = "cfg2";
+					read-only;
+				};
+
+				partition@140000 {
+					compatible = "denx,uimage";
+					reg = <0x140000 0x1d80000>;
+					label = "firmware";
+				};
+
+				partition@1ec0000 {
+					reg = <0x1ec0000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+			};
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1010@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+			status = "disabled";
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts

@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Extreme Networks WS-AP3825i";
+	compatible = "extreme-networks,ws-ap3825i";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "green:radio1";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wifi2 {
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "green:radio2";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_power_red: power_red {
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		lan1_red {
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
+			label = "red:lan1";
+		};
+
+		lan1_green {
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
+			label = "green:lan1";
+		};
+
+		lan2_red {
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
+			label = "red:lan2";
+		};
+
+		lan2_green {
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
+			label = "green:lan2";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					compatible = "denx,fit";
+					reg = <0x0 0x3d60000>;
+					label = "firmware";
+				};
+
+				partition@3d60000 {
+					reg = <0x3d60000 0x20000>;
+					label = "calib";
+					read-only;
+				};
+
+				partition@3d80000{
+					reg = <0x3d80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@3e00000{
+					reg = <0x3e00000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "cfg2";
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "cfg1";
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				/* interrupts = <3 1 0 0>; */
+				reg = <0x5>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+
+			phy2: ethernet-phy@2 {
+				/* interrupts = <1 1 0 0>; */
+				reg = <0x6>;
+				reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "okay";
+			phy-handle = <&phy2>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+			      0x00 0x100000 0x42000000 0x00 0x00 0x00
+			      0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+			      0xffe00000 0x00 0x100000 0x42000000
+			      0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&soc {
+	led_spi {
+		/*
+		 * This is currently non-functioning because the spi-gpio
+		 * driver refuses to register when presented with this node.
+		 */
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <100000>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1020@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff280>;
+			status = "okay";
+			enable-method = "spin-table";
+		};
+
+		PowerPC,P1020@1 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff2a0>;
+			status = "disabled";
+			enable-method = "spin-table";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpu1-bootpage@ff00000 {
+			/* Reserve upper 1 MB for second-core-bootpage */
+			reg = <0x0 0xff00000 0x0 0x100000>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <24999999>;
+	};
+};
+
+&enet0 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+&enet2 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Board Setup
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ *
+ * Based on:
+ *   hiveap-330.c:
+ *      Aerohive HiveAP-330 Board Setup
+ *      Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init br200_wp_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init br200_wp_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("br200_wp_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	pr_info("br200-wp board from Aerohive\n");
+}
+
+machine_arch_initcall(br200_wp, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init br200_wp_probe(void)
+{
+	if (of_machine_is_compatible("aerohive,br200-wp"))
+		return 1;
+	return 0;
+}
+
+define_machine(br200_wp) {
+	.name			= "P1020 RDB",
+	.probe			= br200_wp_probe,
+	.setup_arch		= br200_wp_setup_arch,
+	.init_IRQ		= br200_wp_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/firebox_t10.c

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Watchguard Firebox T10 Board Setup
+ *
+ * Copyright (C) 2023 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   p1010rdb.c:
+ *      P1010 RDB Board Setup
+ *      Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init firebox_t10_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init firebox_t10_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("firebox_t10_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	pr_info("Firebox T10 from Watchguard\n");
+}
+
+machine_arch_initcall(firebox_t10, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init firebox_t10_probe(void)
+{
+	if (of_machine_is_compatible("watchguard,firebox-t10"))
+		return 1;
+	return 0;
+}
+
+define_machine(firebox_t10) {
+	.name			= "P1010 RDB",
+	.probe			= firebox_t10_probe,
+	.setup_arch		= firebox_t10_setup_arch,
+	.init_IRQ		= firebox_t10_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c

@@ -0,0 +1,89 @@
+/*
+ * Aerohive HiveAP-330 Board Setup
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init hiveap_330_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init hiveap_330_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("hiveap_330_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "HiveAP-330 board from Aerohive\n");
+}
+
+machine_arch_initcall(hiveap_330, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init hiveap_330_probe(void)
+{
+	if (of_machine_is_compatible("aerohive,hiveap-330"))
+		return 1;
+	return 0;
+}
+
+define_machine(hiveap_330) {
+	.name			= "P1020 RDB",
+	.probe			= hiveap_330_probe,
+	.setup_arch		= hiveap_330_setup_arch,
+	.init_IRQ		= hiveap_330_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/msm460.c

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * HPE MSM460 Board Setup
+ *
+ * Copyright (C) 2022 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init msm_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init msm_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("msm_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("MSM460 board from HPE\n");
+}
+
+machine_arch_initcall(msm, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init msm_probe(void)
+{
+	if (of_machine_is_compatible("hpe,msm460"))
+		return 1;
+	return 0;
+}
+
+define_machine(msm) {
+	.name			= "P1020 RDB",
+	.probe			= msm_probe,
+	.setup_arch		= msm_setup_arch,
+	.init_IRQ		= msm_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/panda.c

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * OCEDO Panda Board Setup
+ *
+ * Copyright (C) 2019 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init panda_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init panda_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("panda_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("Panda board from OCEDO\n");
+}
+
+machine_arch_initcall(panda, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init panda_probe(void)
+{
+	if (of_machine_is_compatible("ocedo,panda"))
+		return 1;
+	return 0;
+}
+
+define_machine(panda) {
+	.name			= "P1020 RDB",
+	.probe			= panda_probe,
+	.setup_arch		= panda_setup_arch,
+	.init_IRQ		= panda_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/red15w_rev1.c

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Sophos RED 15w Rev.1 Board Setup
+ *
+ * Copyright (C) 2019 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   p1010rdb.c:
+ *      P1010 RDB Board Setup
+ *      Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init red_15w_rev1_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init red_15w_rev1_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("red_15w_rev1_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	pr_info("RED 15w Rev.1 from Sophos\n");
+}
+
+machine_arch_initcall(red_15w_rev1, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init red_15w_rev1_probe(void)
+{
+	if (of_machine_is_compatible("sophos,red-15w-rev1"))
+		return 1;
+	return 0;
+}
+
+define_machine(red_15w_rev1) {
+	.name			= "P1010 RDB",
+	.probe			= red_15w_rev1_probe,
+	.setup_arch		= red_15w_rev1_setup_arch,
+	.init_IRQ		= red_15w_rev1_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c

@@ -0,0 +1,140 @@
+/*
+ * TL-WDR4900 v1 board setup
+ *
+ * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Based on:
+ *   p1010rdb.c:
+ *      P1010RDB Board Setup
+ *      Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/ath9k_platform.h>
+#include <linux/leds.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init tl_wdr4900_v1_pic_init(void)
+{
+	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+
+	mpic_init(mpic);
+}
+
+#ifdef CONFIG_PCI
+static struct gpio_led tl_wdr4900_v1_wmac_leds_gpio[] = {
+	{
+		.name		= "tp-link:blue:wps",
+		.gpio		= 1,
+		.active_low	= 1,
+	},
+};
+
+static struct ath9k_platform_data tl_wdr4900_v1_wmac0_data = {
+	.led_pin = 0,
+	.eeprom_name = "pci_wmac0.eeprom",
+	.leds = tl_wdr4900_v1_wmac_leds_gpio,
+	.num_leds = ARRAY_SIZE(tl_wdr4900_v1_wmac_leds_gpio),
+};
+
+static struct ath9k_platform_data tl_wdr4900_v1_wmac1_data = {
+	.led_pin = 0,
+	.eeprom_name = "pci_wmac1.eeprom",
+};
+
+static void tl_wdr4900_v1_pci_wmac_fixup(struct pci_dev *dev)
+{
+	if (!machine_is(tl_wdr4900_v1))
+		return;
+
+	if (dev->bus->number == 1 &&
+	    PCI_SLOT(dev->devfn) == 0) {
+		dev->dev.platform_data = &tl_wdr4900_v1_wmac0_data;
+		return;
+	}
+
+	if (dev->bus->number == 3 &&
+	    PCI_SLOT(dev->devfn) == 0 &&
+	    dev->device == 0xabcd) {
+		dev->dev.platform_data = &tl_wdr4900_v1_wmac1_data;
+
+		/*
+		 * The PCI header of the AR9381 chip is not programmed
+		 * correctly by the bootloader and the device uses wrong
+		 * data due to that. Replace the broken values with the
+		 * correct ones.
+		 */
+		dev->device = 0x30;
+		dev->class = 0x028000;
+
+		pr_info("pci %s: AR9381 fixup applied\n", pci_name(dev));
+	}
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
+			tl_wdr4900_v1_pci_wmac_fixup);
+#endif /* CONFIG_PCI */
+
+/*
+ * Setup the architecture
+ */
+static void __init tl_wdr4900_v1_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("tl_wdr4900_v1_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	printk(KERN_INFO "TL-WDR4900 v1 board from TP-Link\n");
+}
+
+machine_arch_initcall(tl_wdr4900_v1, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init tl_wdr4900_v1_probe(void)
+{
+	if (of_machine_is_compatible("tplink,tl-wdr4900-v1"))
+		return 1;
+	return 0;
+}
+
+define_machine(tl_wdr4900_v1) {
+	.name			= "Freescale P1014",
+	.probe			= tl_wdr4900_v1_probe,
+	.setup_arch		= tl_wdr4900_v1_setup_arch,
+	.init_IRQ		= tl_wdr4900_v1_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3710i.c

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Enterasys WS-AP3710i Board Setup
+ *
+ * Copyright (C) 2019 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init ws_ap3710i_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init ws_ap3710i_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("ws_ap3710i_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("WS-AP3710i board from Enterasys\n");
+}
+
+machine_arch_initcall(ws_ap3710i, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ws_ap3710i_probe(void)
+{
+	if (of_machine_is_compatible("enterasys,ws-ap3710i"))
+		return 1;
+	return 0;
+}
+
+define_machine(ws_ap3710i) {
+	.name			= "P1020 RDB",
+	.probe			= ws_ap3710i_probe,
+	.setup_arch		= ws_ap3710i_setup_arch,
+	.init_IRQ		= ws_ap3710i_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3715i.c

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Enterasys WS-AP3715i Board Setup
+ *
+ * Copyright (C) 2023 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   p1010rdb.c:
+ *      P1010 RDB Board Setup
+ *      Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init wsap3715i_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init wsap3715i_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("wsap3715i_setup_arch()", 0);
+
+	fsl_pci_assign_primary();
+
+	pr_info("WS-AP3715i from Enterasys\n");
+}
+
+machine_arch_initcall(wsap3715i, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init wsap3715i_probe(void)
+{
+	if (of_machine_is_compatible("enterasys,ws-ap3715i"))
+		return 1;
+	return 0;
+}
+
+define_machine(wsap3715i) {
+	.name			= "P1010 RDB",
+	.probe			= wsap3715i_probe,
+	.setup_arch		= wsap3715i_setup_arch,
+	.init_IRQ		= wsap3715i_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3825i.c

@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Extreme Networks WS-AP3825i Board Setup
+ *
+ * Copyright (C) 2021 Martin Kennedy <hurricos@gmail.com>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init ws_ap3825i_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init ws_ap3825i_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("ws_ap3825i_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("WS-AP3825i board from Extreme Networks\n");
+}
+
+machine_arch_initcall(ws_ap3825i, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ws_ap3825i_probe(void)
+{
+	if (of_machine_is_compatible("extreme-networks,ws-ap3825i"))
+		return 1;
+	return 0;
+}
+
+define_machine(ws_ap3825i) {
+	.name			= "P1020 RDB",
+	.probe			= ws_ap3825i_probe,
+	.setup_arch		= ws_ap3825i_setup_arch,
+	.init_IRQ		= ws_ap3825i_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};

target/linux/mpc85xx/image/Makefile

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+DEVICE_VARS += DTB_SIZE
+
+define Build/pad-dtb
+	$(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$(dir $@)/image-$(DEVICE_DTS).dtb,,--space $(DTB_SIZE))
+endef
+
+define Device/Default
+  PROFILES := Default
+  DEVICE_DTS := $(lastword $(subst _, ,$(1)))
+  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
+  KERNEL_ENTRY := 0x00000000
+  KERNEL_LOADADDR := 0x00000000
+  KERNEL := kernel-bin
+endef
+
+include $(SUBTARGET).mk
+
+$(eval $(call BuildImage))

target/linux/mpc85xx/image/p1010.mk

@@ -0,0 +1,96 @@
+DEVICE_VARS += TPLINK_HWID TPLINK_HWREV TPLINK_FLASHLAYOUT TPLINK_HEADER_VERSION
+
+define Build/spi-loader-okli-compile
+	rm -rf $@.spi-loader-okli
+	$(CP) spi-loader $@.spi-loader-okli
+	$(MAKE) -C $@.spi-loader-okli \
+		CROSS_COMPILE="$(TARGET_CROSS)" CONFIG="$(DEVICE_NAME)"
+	cp "$@.spi-loader-okli/out/uImage" "$@"
+	rm -rf $@.spi-loader-okli
+endef
+
+define Build/spi-loader-okli
+	cat $(KDIR)/loader-$(1) "$@" > "$@.new"
+	mv "$@.new" "$@"
+endef
+
+define Device/aerohive_br200-wp
+  DEVICE_VENDOR := Aerohive
+  DEVICE_MODEL := BR200-WP
+  BLOCKSIZE := 128k
+  KERNEL_NAME := simpleImage.br200-wp
+  KERNEL := kernel-bin | uImage none
+  KERNEL_INITRAMFS := kernel-bin | uImage none
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  KERNEL_SIZE := 8m
+  IMAGES := fdt.bin sysupgrade.bin
+  IMAGE/fdt.bin := append-dtb
+  IMAGE/sysupgrade.bin := append-dtb | pad-to 256k | check-size 256k | \
+	append-uImage-fakehdr ramdisk | pad-to 256k | check-size 512k | \
+	append-rootfs | pad-rootfs $$(BLOCKSIZE) | pad-to 41216k | check-size 41216k | \
+	append-kernel | append-metadata
+  IMAGE_SIZE = 63m
+endef
+TARGET_DEVICES += aerohive_br200-wp
+
+define Device/enterasys_ws-ap3715i
+  DEVICE_VENDOR := Enterasys
+  DEVICE_MODEL := WS-AP3715i
+  BLOCKSIZE := 64k
+  KERNEL_NAME := simpleImage.ws-ap3715i
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  KERNEL = kernel-bin | lzma | uImage lzma
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += enterasys_ws-ap3715i
+
+define Device/tplink_tl-wdr4900-v1
+  DEVICE_VENDOR := TP-Link
+  DEVICE_MODEL := TL-WDR4900
+  DEVICE_VARIANT := v1
+  DEVICE_COMPAT_VERSION := 1.1
+  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
+  TPLINK_HEADER_VERSION := 1
+  TPLINK_HWID := 0x49000001
+  TPLINK_HWREV := 1
+  TPLINK_FLASHLAYOUT := 16Mppc
+  KERNEL_NAME := simpleImage.tl-wdr4900-v1
+  KERNEL_INITRAMFS :=
+  KERNEL := kernel-bin | uImage none -M 0x4f4b4c49 | spi-loader-okli $(1)
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  SUPPORTED_DEVICES += tl-wdr4900-v1
+  COMPILE := loader-$(1)
+  COMPILE/loader-$(1) := spi-loader-okli-compile
+  ARTIFACTS := fdt.bin
+  ARTIFACT/fdt.bin := append-dtb
+  IMAGES := factory.bin sysupgrade.bin
+  IMAGE/sysupgrade.bin := tplink-v1-image sysupgrade | append-metadata
+  IMAGE/factory.bin := tplink-v1-image factory
+endef
+TARGET_DEVICES += tplink_tl-wdr4900-v1
+
+define Device/watchguard_firebox-t10
+  DEVICE_VENDOR := Watchguard
+  DEVICE_MODEL := Firebox T10
+  DEVICE_PACKAGES := kmod-rtc-s35390a kmod-eeprom-at24
+  KERNEL = kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += watchguard_firebox-t10
+
+define Device/sophos_red-15w-rev1
+  DEVICE_VENDOR := Sophos
+  DEVICE_MODEL := RED 15w
+  DEVICE_VARIANT := Rev.1
+  # Original firmware uses a dedicated DTB-partition.
+  # The bootloader however supports FIT-images.
+  KERNEL = kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += sophos_red-15w-rev1

target/linux/mpc85xx/image/p1020.mk

@@ -0,0 +1,124 @@
+define Build/MultiImage
+        rm -rf $@.fakerd $@.new
+
+        dd if=/dev/zero of=$@.fakerd bs=32 count=1 conv=sync
+
+        -$(STAGING_DIR_HOST)/bin/mkimage -A $(LINUX_KARCH) -O linux -T multi -C $(1)  \
+		-a $(KERNEL_LOADADDR) -e $(KERNEL_ENTRY) -n '$(BOARD_NAME) initramfs' \
+		-d $@:$@.fakerd:$(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb $@.new
+        mv $@.new $@
+        rm -rf $@.fakerd
+endef
+
+define Device/aerohive_hiveap-330
+  DEVICE_VENDOR := Aerohive
+  DEVICE_MODEL := HiveAP-330
+  DEVICE_ALT0_VENDOR := Aerohive
+  DEVICE_ALT0_MODEL := HiveAP-350
+  DEVICE_PACKAGES := kmod-tpm-i2c-atmel kmod-hwmon-lm70
+  BLOCKSIZE := 128k
+  KERNEL := kernel-bin | uImage none
+  KERNEL_INITRAMFS := kernel-bin | uImage none
+  KERNEL_NAME := simpleImage.hiveap-330
+  KERNEL_SIZE := 16m
+  IMAGES := sysupgrade.bin
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  # append-dtb is still needed, as otherwise u-boot bootm complains
+  # about not having a FDT to edit.
+  IMAGE/sysupgrade.bin := append-dtb | pad-to 256k | append-kernel | \
+	append-rootfs | pad-rootfs | check-size | append-metadata
+  IMAGE_SIZE = 63m
+  DEVICE_COMPAT_VERSION := 2.0
+  DEVICE_COMPAT_MESSAGE := \n$\
+    !The partitioning of the HiveAP 330 has changed! \n$\
+    To upgrade, please take a look at the install instructions over \
+    at the device's wiki: <https://openwrt.org/toh/aerohive/hiveap-330> \n$\
+    An abridged version for the console is provided here for comfort. \n$\
+    Run the following script into a shell on the device and retry this \
+    sysupgrade again: \n$\
+    cat <<- "EOF" > /tmp/uboot-fix.sh; sh /tmp/uboot-fix.sh \n$\
+    . /lib/functions.sh \n$\
+    . /lib/functions/system.sh \n$\
+    opkg update && opkg install uboot-envtools kmod-mtd-rw || exit 2 \n$\
+    insmod mtd-rw i_want_a_brick=y || exit 3 \n$\
+    echo "/dev/mtd$$$$(find_mtd_index u-boot-env) 0x0 0x20000 0x10000" > "/etc/fw_env.config" \n$\
+    fw_setenv owrt_boot 'setenv bootargs console=ttyS0,9600;bootm 0xEC040000 - 0xEC000000' \n$\
+    cp "/dev/mtd$$$$(find_mtd_index 'u-boot')" /tmp/uboot \n$\
+    cp /tmp/uboot /tmp/uboot_patched \n$\
+    strings -td < /tmp/uboot | grep '^ *[0-9]* *\\(run owrt_boot\\|setenv bootargs\\).*cp\\.l' | \n$\
+       awk '{print $$$$1}' | \n$\
+       while read offset; do \n$\
+         echo -n "run owrt_boot;            " | dd of=/tmp/uboot_patched bs=1 seek=$$$${offset} conv=notrunc \n$\
+       done \n$\
+       mtd write /tmp/uboot_patched u-boot \n$\
+       uci set system.@system[0].compat_version=2.0; uci commit; \n$\
+    EOF \n$\
+    \n$\
+    Note that if this fails, you will need to use the serial console \n$\
+    to re-install OpenWrt. \n$\
+    Note that after this sysupgrade, the AP will be unavailable for 7 \n$\
+    minutes to reformat flash."
+
+endef
+TARGET_DEVICES += aerohive_hiveap-330
+
+define Device/enterasys_ws-ap3710i
+  DEVICE_VENDOR := Enterasys
+  DEVICE_MODEL := WS-AP3710i
+  BLOCKSIZE := 128k
+  KERNEL_NAME := simpleImage.ws-ap3710i
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  KERNEL = kernel-bin | uImage none
+  KERNEL_INITRAMFS := kernel-bin | uImage none
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += enterasys_ws-ap3710i
+
+define Device/extreme-networks_ws-ap3825i
+  DEVICE_VENDOR := Extreme Networks
+  DEVICE_MODEL := WS-AP3825i
+  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct
+  BLOCKSIZE := 128k
+  KERNEL_NAME := simpleImage.ws-ap3825i
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += extreme-networks_ws-ap3825i
+
+define Device/hpe_msm460
+  DEVICE_VENDOR := Hewlett-Packard
+  DEVICE_MODEL := MSM460
+  KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
+  KERNEL_NAME := zImage.la3000000
+  KERNEL_ENTRY := 0x3000000
+  KERNEL_LOADADDR := 0x3000000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  UBINIZE_OPTS := -E 5
+  IMAGES := factory.bin sysupgrade.bin
+  IMAGE/factory.bin := append-ubi
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += hpe_msm460
+
+define Device/ocedo_panda
+  DEVICE_VENDOR := OCEDO
+  DEVICE_MODEL := Panda
+  DEVICE_PACKAGES := kmod-rtc-ds1307
+  KERNEL = kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb
+  PAGESIZE := 2048
+  SUBPAGESIZE := 512
+  BLOCKSIZE := 128k
+  IMAGES := fdt.bin sysupgrade.bin
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  IMAGE/fdt.bin := append-dtb
+endef
+TARGET_DEVICES += ocedo_panda

target/linux/mpc85xx/image/p2020.mk

@@ -0,0 +1,15 @@
+define Device/freescale_p2020rdb
+  DEVICE_VENDOR := Freescale
+  DEVICE_MODEL := P2020RDB
+  DEVICE_DTS_DIR := $(DTS_DIR)/fsl
+  DEVICE_PACKAGES := kmod-hwmon-lm90 kmod-rtc-ds1307 \
+	kmod-gpio-pca953x kmod-eeprom-at24
+  BLOCKSIZE := 128k
+  KERNEL := kernel-bin | gzip | \
+	fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  SUPPORTED_DEVICES := fsl,P2020RDB
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
+	pad-rootfs $$(BLOCKSIZE) | append-metadata
+endef
+TARGET_DEVICES += freescale_p2020rdb

target/linux/mpc85xx/image/spi-loader/.gitignore

@@ -0,0 +1 @@
+/out

target/linux/mpc85xx/image/spi-loader/Makefile

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+
+CONFIG     ?= $(error No configuration set)
+
+include config/$(CONFIG).mk
+
+MKIMAGE    := mkimage
+KARCH      := powerpc
+CC         := $(CROSS_COMPILE)gcc
+LD         := $(CROSS_COMPILE)ld
+OBJCOPY    := $(CROSS_COMPILE)objcopy
+
+PROGRAM_NAME := MPC85xx SPI loader
+
+BIN_FLAGS  := -O binary --pad-to=$(PAD_TO)
+
+CFLAGS     += -std=gnu17 -Os -Wall -Wstrict-prototypes \
+		-fomit-frame-pointer -ffreestanding \
+		-ffunction-sections -fno-pic \
+		-Iinclude -include ../config/$(CONFIG).h \
+		-DCONFIG_PROGRAM_NAME='"$(PROGRAM_NAME)"' \
+		-DCONFIG_IMAGE_OFFSET=$(IMAGE_OFFSET)
+ASFLAGS    := $(CFLAGS)
+
+LDS        := loader.lds
+LDFLAGS    := -static --gc-sections -T $(LDS) -Ttext $(TEXT_START)
+
+OBJECTS    := head.o loader.o string.o stdio.o  drivers/serial/ns16550.o \
+		drivers/spi/fsl_espi.o drivers/spi/spi-nor.o
+
+OUTDIR     := out
+
+all: $(OUTDIR)/uImage
+
+-include $(OBJECTS:%.o=$(OUTDIR)/%.d)
+
+$(OUTDIR)/%.o: %.c Makefile config/$(CONFIG).mk
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) -c -o $@ -MD -MP $<
+
+$(OUTDIR)/%.o: %.S Makefile config/$(CONFIG).mk
+	@mkdir -p $(dir $@)
+	$(CC) $(ASFLAGS) -c -o $@ -MD -MP $<
+
+$(OUTDIR)/loader.elf: $(OBJECTS:%=$(OUTDIR)/%) $(LDS)
+	$(LD) $(LDFLAGS) -o $@ $(OBJECTS:%=$(OUTDIR)/%)
+
+$(OUTDIR)/loader.bin: $(OUTDIR)/loader.elf
+	$(OBJCOPY) $(BIN_FLAGS) $< $@
+
+$(OUTDIR)/uImage: $(OUTDIR)/loader.bin
+	$(MKIMAGE) -A $(KARCH) -O linux -T kernel -C none \
+		-a $(TEXT_START) -e $(TEXT_START) -n '$(PROGRAM_NAME)' -d $< $@
+
+clean:
+	rm -rf $(OUTDIR)
+
+.PHONY: all clean

target/linux/mpc85xx/image/spi-loader/config/tplink_tl-wdr4900-v1.h

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#define CONFIG_FREQ_SYSTEMBUS 399999996
+#define CONFIG_SPI_MAX_HZ 25000000
+
+#define CONFIG_SERIAL_NS16550_REG_BASE 0xffe04500
+#define CONFIG_SERIAL_NS16550_REG_SHIFT 0
+
+#define CONFIG_SPI_FSL_ESPI_REG_BASE 0xffe07000

target/linux/mpc85xx/image/spi-loader/config/tplink_tl-wdr4900-v1.mk

@@ -0,0 +1,13 @@
+TEXT_START   := 0x800000
+
+# It seems that the TP-Link TL-WDR4900 U-Boot does not flush the cache before
+# jumping into the uImage. Padding the image to 32k seems make the boot work
+# reliably.
+#
+# We leave 0x40 for the uImage header, which allows us to append the kernel
+# uImage after the loader and read with an added offset 0x8000 from the
+# SPI flash.
+PAD_TO       := 0x807fc0
+
+# Kernel begins at 0x60200 in flash, loader adds 0x8000
+IMAGE_OFFSET := 0x68200

target/linux/mpc85xx/image/spi-loader/drivers/serial/ns16550.c

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * 16550 serial console support.
+ *
+ * Original copied from <file:arch/ppc/boot/common/ns16550.c>
+ * (which had no copyright)
+ * Modifications: 2006 (c) MontaVista Software, Inc.
+ *
+ * Modified by: Mark A. Greer <mgreer@mvista.com>
+ *
+ * Adapted by:
+ *
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#include <io.h>
+#include <serial.h>
+
+#define UART_DLL	0	/* Out: Divisor Latch Low */
+#define UART_DLM	1	/* Out: Divisor Latch High */
+#define UART_FCR	2	/* Out: FIFO Control Register */
+#define UART_LCR	3	/* Out: Line Control Register */
+#define UART_MCR	4	/* Out: Modem Control Register */
+#define UART_LSR	5	/* In:  Line Status Register */
+#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
+#define UART_LSR_DR	0x01	/* Receiver data ready */
+#define UART_MSR	6	/* In:  Modem Status Register */
+#define UART_SCR	7	/* I/O: Scratch Register */
+
+static uint8_t *const reg_base = (uint8_t *)CONFIG_SERIAL_NS16550_REG_BASE;
+static const int reg_shift = CONFIG_SERIAL_NS16550_REG_SHIFT;
+
+void serial_console_putchar(char c)
+{
+	while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0);
+	out_8(reg_base, c);
+}
+
+int serial_console_getc(void)
+{
+	while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
+	return in_8(reg_base);
+}
+
+int serial_console_tstc(void)
+{
+	return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
+}
+
+void serial_console_init(void)
+{
+	out_8(reg_base + (UART_FCR << reg_shift), 0x06);
+}

target/linux/mpc85xx/image/spi-loader/drivers/spi/fsl_espi.c

@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * eSPI controller driver.
+ *
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ *
+ * Based on U-Boot code:
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ * Author: Mingkai Hu (Mingkai.hu@freescale.com)
+ *	   Chuanhua Han (chuanhua.han@nxp.com)
+ */
+
+#include <io.h>
+#include <stdio.h>
+#include <spi.h>
+
+/* eSPI Registers */
+typedef struct ccsr_espi {
+	uint32_t mode;       /* eSPI mode */
+	uint32_t event;      /* eSPI event */
+	uint32_t mask;       /* eSPI mask */
+	uint32_t com;        /* eSPI command */
+	uint32_t tx;         /* eSPI transmit FIFO access */
+	uint32_t rx;         /* eSPI receive FIFO access */
+	uint8_t  res1[8];    /* reserved */
+	uint32_t csmode[4];  /* 0x2c: sSPI CS0/1/2/3 mode */
+	uint8_t  res2[4048]; /* fill up to 0x1000 */
+} ccsr_espi_t;
+
+struct fsl_spi {
+	ccsr_espi_t	*espi;
+	uint32_t	cs;
+	uint32_t	div16;
+	uint32_t	pm;
+	uint32_t	mode;
+};
+
+#define ESPI_MAX_CS_NUM		4
+#define ESPI_FIFO_WIDTH_BIT	32
+
+#define ESPI_EV_RNE		BIT(9)
+#define ESPI_EV_TNF		BIT(8)
+#define ESPI_EV_DON		BIT(14)
+#define ESPI_EV_TXE		BIT(15)
+#define ESPI_EV_RFCNT_SHIFT	24
+#define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
+
+#define ESPI_MODE_EN		BIT(31)	/* Enable interface */
+#define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
+#define ESPI_MODE_RXTHR(x)	((x) << 0)	/* Rx FIFO threshold */
+
+#define ESPI_COM_CS(x)		((x) << 30)
+#define ESPI_COM_TRANLEN(x)	((x) << 0)
+
+#define ESPI_CSMODE_CI_INACTIVEHIGH	BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK	BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST	BIT(29)
+#define ESPI_CSMODE_DIV16		BIT(28)
+#define ESPI_CSMODE_PM(x)		((x) << 24)
+#define ESPI_CSMODE_POL_ASSERTED_LOW	BIT(20)
+#define ESPI_CSMODE_LEN(x)		((x) << 16)
+#define ESPI_CSMODE_CSBEF(x)		((x) << 12)
+#define ESPI_CSMODE_CSAFT(x)		((x) << 8)
+#define ESPI_CSMODE_CSCG(x)		((x) << 3)
+
+#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
+		ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
+		ESPI_CSMODE_CSCG(1))
+
+#define ESPI_MAX_DATA_TRANSFER_LEN 0x10000
+
+static int espi_xfer(struct fsl_spi *fsl, const struct spi_transfer *msg, int n)
+{
+	ccsr_espi_t *espi = fsl->espi;
+	size_t len = spi_message_len(msg, n);
+
+	if (len > ESPI_MAX_DATA_TRANSFER_LEN)
+		return -1;
+
+	/* clear the RXCNT and TXCNT */
+	out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
+	out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
+	out_be32(&espi->com, ESPI_COM_CS(fsl->cs) | ESPI_COM_TRANLEN(len - 1));
+
+	int last_msg = n - 1;
+	int tx_msg = -1, rx_msg = -1;
+	size_t tx_len = 0, rx_len = 0, tx_pos = 0, rx_pos = 0;
+
+	while (true) {
+		if (tx_pos == tx_len && tx_msg < last_msg) {
+			tx_msg++;
+			tx_pos = 0;
+			tx_len = msg[tx_msg].len;
+		}
+		if (rx_pos == rx_len && rx_msg < last_msg) {
+			rx_msg++;
+			rx_pos = 0;
+			rx_len = msg[rx_msg].len;
+		}
+		if (rx_pos == rx_len)
+			break;
+
+		const uint8_t *tx_buf = msg[tx_msg].tx_buf;
+		uint8_t *rx_buf = msg[rx_msg].rx_buf;
+
+		uint32_t event = in_be32(&espi->event);
+
+		/* TX */
+		if ((event & ESPI_EV_TNF) && tx_len > 0) {
+			uint8_t v = 0;
+			if (tx_buf)
+				v = tx_buf[tx_pos];
+			out_8((uint8_t *)&espi->tx, v);
+			tx_pos++;
+		}
+
+		/* RX */
+		if (event & ESPI_EV_RNE) {
+			uint8_t v = in_8((uint8_t *)&espi->rx);
+			if (rx_buf)
+				rx_buf[rx_pos] = v;
+			rx_pos++;
+		}
+	}
+
+	return 0;
+}
+
+static void espi_claim_bus(struct fsl_spi *fsl)
+{
+	ccsr_espi_t *espi = fsl->espi;
+	uint32_t csmode;
+	int i;
+
+	/* Enable eSPI interface */
+	out_be32(&espi->mode, ESPI_MODE_RXTHR(3)
+			| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);
+
+	out_be32(&espi->mask, 0x00000000); /* Mask  all eSPI interrupts */
+
+	/* Init CS mode interface */
+	for (i = 0; i < ESPI_MAX_CS_NUM; i++)
+		out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);
+
+	csmode = ESPI_CSMODE_INIT_VAL;
+
+	/* Set eSPI BRG clock source */
+	csmode |= ESPI_CSMODE_PM(fsl->pm) | fsl->div16;
+
+	/* Set eSPI mode */
+	if (fsl->mode & SPI_CPHA)
+		csmode |= ESPI_CSMODE_CP_BEGIN_EDGCLK;
+	if (fsl->mode & SPI_CPOL)
+		csmode |= ESPI_CSMODE_CI_INACTIVEHIGH;
+
+	/* Character bit order: msb first */
+	csmode |= ESPI_CSMODE_REV_MSB_FIRST;
+
+	/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */
+	csmode |= ESPI_CSMODE_LEN(7);
+
+	out_be32(&espi->csmode[fsl->cs], csmode);
+}
+
+static void espi_release_bus(struct fsl_spi *fsl)
+{
+	/* Disable the SPI hardware */
+	out_be32(&fsl->espi->mode,
+		in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));
+}
+
+static void espi_setup_spi(struct fsl_spi *fsl, unsigned int max_hz)
+{
+	unsigned long spibrg;
+	uint32_t pm;
+
+	spibrg = CONFIG_FREQ_SYSTEMBUS / 2;
+	fsl->div16 = 0;
+	if ((spibrg / max_hz) > 32) {
+		fsl->div16 = ESPI_CSMODE_DIV16;
+		pm = spibrg / (max_hz * 16 * 2);
+		if (pm > 16) {
+			/* max_hz too low */
+			pm = 16;
+		}
+	} else {
+		pm = spibrg / (max_hz * 2);
+	}
+	if (pm)
+		pm--;
+	fsl->pm = pm;
+}
+
+static struct fsl_spi spi;
+
+int spi_init(unsigned int cs, unsigned int max_hz, unsigned int mode)
+{
+	if (cs >= ESPI_MAX_CS_NUM)
+		return -1;
+
+	spi.espi = (ccsr_espi_t *)CONFIG_SPI_FSL_ESPI_REG_BASE;
+	spi.cs = cs;
+	spi.mode = mode;
+
+	espi_setup_spi(&spi, max_hz);
+
+	return 0;
+}
+
+int spi_claim_bus(void)
+{
+	espi_claim_bus(&spi);
+
+	return 0;
+}
+
+void spi_release_bus(void)
+{
+	espi_release_bus(&spi);
+}
+
+int spi_xfer(const struct spi_transfer *msg, int n)
+{
+	return espi_xfer(&spi, msg, n);
+}
+
+size_t spi_max_xfer(void)
+{
+	return ESPI_MAX_DATA_TRANSFER_LEN;
+}

target/linux/mpc85xx/image/spi-loader/drivers/spi/spi-nor.c

@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#include <spi.h>
+#include <spi-nor.h>
+#include <stdio.h>
+
+#define CMD_READ 0x03
+#define CMD_READ_ID 0x9F
+
+int spi_nor_read_id(void)
+{
+	int ret;
+
+	const uint8_t tx_buf[1] = {CMD_READ_ID};
+	uint8_t rx_buf[3] = {};
+	struct spi_transfer t[2] = {{
+		.tx_buf = tx_buf,
+		.rx_buf = NULL,
+		.len = sizeof(tx_buf),
+	}, {
+		.tx_buf = NULL,
+		.rx_buf = rx_buf,
+		.len = sizeof(rx_buf),
+	}};
+
+	ret = spi_xfer(t, ARRAY_SIZE(t));
+	if (ret) {
+		puts("SPI transfer failed\n");
+		return ret;
+	}
+
+	puts("Flash JECED ID: ");
+	put_array(rx_buf, sizeof(rx_buf));
+
+	return 0;
+}
+
+int spi_nor_read_data(void *dest, size_t pos, size_t len)
+{
+	int ret;
+
+	while (len > 0) {
+		uint8_t cmd[4] = {CMD_READ, pos >> 16, pos >> 8, pos};
+		size_t block_len = min(len, spi_max_xfer() - sizeof(cmd));
+
+		struct spi_transfer t[2] = {{
+			.tx_buf = cmd,
+			.rx_buf = NULL,
+			.len = sizeof(cmd),
+		}, {
+			.tx_buf = NULL,
+			.rx_buf = dest,
+			.len = block_len,
+		}};
+
+		ret = spi_xfer(t, ARRAY_SIZE(t));
+		if (ret) {
+			puts("SPI transfer failed\n");
+			return ret;
+		}
+
+		pos += block_len;
+		dest += block_len;
+		len -= block_len;
+	}
+
+	return 0;
+}
+

target/linux/mpc85xx/image/spi-loader/head.S

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ *
+ * Based on Linux arch/powerpc/boot/crt0.S, which is:
+ *
+ * Copyright (C) Paul Mackerras 1997.
+ */
+
+#include <ppc_asm.h>
+
+	.text
+	.global _start
+_start:
+	/* Do a cache flush for our text, in case the loader didn't */
+	lis	r3,_text_start@ha
+	addi	r3,r3,_text_start@l
+	li	r4,_text_len
+	bl	flush_cache
+
+	/* Clear the BSS */
+	lis	r3,_bss_start@ha
+	addi	r3,r3,_bss_start@l
+	li	r4,0
+	li	r5,_bss_len
+	bl	memset
+
+	/* Set up stack */
+	lis	r1,_stack_top@ha
+	addi	r1,r1,_stack_top@l
+	/* Establish a stack frame */
+	li	r0,0
+	stwu	r0,-16(r1)
+
+	/* Call start */
+	b	start

target/linux/mpc85xx/image/spi-loader/include/image.h

@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Derived from U-Boot include/image.h:
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#pragma once
+
+#include <types.h>
+
+/*
+ * Compression Types
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
+ */
+enum {
+	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
+	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
+	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
+	IH_COMP_LZMA,			/* lzma  Compression Used	*/
+	IH_COMP_LZO,			/* lzo   Compression Used	*/
+	IH_COMP_LZ4,			/* lz4   Compression Used	*/
+	IH_COMP_ZSTD,			/* zstd   Compression Used	*/
+
+	IH_COMP_COUNT,
+};
+
+#define IH_MAGIC	0x27051956	/* Image Magic Number		*/
+#define IH_MAGIC_OKLI	0x4f4b4c49	/* 'OKLI' Magic Number */
+#define IH_NMLEN		32	/* Image Name Length		*/
+
+/*
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
+ */
+typedef struct image_header {
+	uint32_t	ih_magic;	/* Image Header Magic Number	*/
+	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
+	uint32_t	ih_time;	/* Image Creation Timestamp	*/
+	uint32_t	ih_size;	/* Image Data Size		*/
+	uint32_t	ih_load;	/* Data	 Load  Address		*/
+	uint32_t	ih_ep;		/* Entry Point Address		*/
+	uint32_t	ih_dcrc;	/* Image Data CRC Checksum	*/
+	uint8_t		ih_os;		/* Operating System		*/
+	uint8_t		ih_arch;	/* CPU architecture		*/
+	uint8_t		ih_type;	/* Image Type			*/
+	uint8_t		ih_comp;	/* Compression Type		*/
+	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
+} image_header_t;

target/linux/mpc85xx/image/spi-loader/include/init.h

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#pragma once
+
+void start(void);

target/linux/mpc85xx/image/spi-loader/include/io.h

@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#pragma once
+
+#include <stdint.h>
+
+/*
+ * Low-level I/O routines.
+ *
+ * Copied from <file:arch/powerpc/include/asm/io.h> (which has no copyright)
+ */
+static inline uint8_t in_8(const volatile uint8_t *addr)
+{
+	int ret;
+
+	__asm__ __volatile__("lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
+			     : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_8(volatile uint8_t *addr, uint8_t val)
+{
+	__asm__ __volatile__("stb%U0%X0 %1,%0; sync"
+			     : "=m" (*addr) : "r" (val));
+}
+
+static inline uint16_t in_le16(const volatile uint16_t *addr)
+{
+	uint32_t ret;
+
+	__asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync"
+			     : "=r" (ret) : "r" (addr), "m" (*addr));
+
+	return ret;
+}
+
+static inline uint16_t in_be16(const volatile uint16_t *addr)
+{
+	uint32_t ret;
+
+	__asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
+			     : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_le16(volatile uint16_t *addr, uint16_t val)
+{
+	__asm__ __volatile__("sthbrx %1,0,%2; sync" : "=m" (*addr)
+			     : "r" (val), "r" (addr));
+}
+
+static inline void out_be16(volatile uint16_t *addr, uint16_t val)
+{
+	__asm__ __volatile__("sth%U0%X0 %1,%0; sync"
+			     : "=m" (*addr) : "r" (val));
+}
+
+static inline uint32_t in_le32(const volatile uint32_t *addr)
+{
+	uint32_t ret;
+
+	__asm__ __volatile__("lwbrx %0,0,%1; twi 0,%0,0; isync"
+			     : "=r" (ret) : "r" (addr), "m" (*addr));
+	return ret;
+}
+
+static inline uint32_t in_be32(const volatile uint32_t *addr)
+{
+	uint32_t ret;
+
+	__asm__ __volatile__("lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
+			     : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_le32(volatile uint32_t *addr, uint32_t val)
+{
+	__asm__ __volatile__("stwbrx %1,0,%2; sync" : "=m" (*addr)
+			     : "r" (val), "r" (addr));
+}
+
+static inline void out_be32(volatile uint32_t *addr, uint32_t val)
+{
+	__asm__ __volatile__("stw%U0%X0 %1,%0; sync"
+			     : "=m" (*addr) : "r" (val));
+}
+
+static inline void sync(void)
+{
+	asm volatile("sync" : : : "memory");
+}
+
+static inline void eieio(void)
+{
+	asm volatile("eieio" : : : "memory");
+}
+
+static inline void barrier(void)
+{
+	asm volatile("" : : : "memory");
+}

target/linux/mpc85xx/image/spi-loader/include/ppc_asm.h

@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#pragma once
+/*
+ *
+ * Definitions used by various bits of low-level assembly code on PowerPC.
+ *
+ * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
+ */
+
+/* Condition Register Bit Fields */
+
+#define	cr0	0
+#define	cr1	1
+#define	cr2	2
+#define	cr3	3
+#define	cr4	4
+#define	cr5	5
+#define	cr6	6
+#define	cr7	7
+
+/* General Purpose Registers (GPRs) */
+
+#define	r0	0
+#define	r1	1
+#define	r2	2
+#define	r3	3
+#define	r4	4
+#define	r5	5
+#define	r6	6
+#define	r7	7
+#define	r8	8
+#define	r9	9
+#define	r10	10
+#define	r11	11
+#define	r12	12
+#define	r13	13
+#define	r14	14
+#define	r15	15
+#define	r16	16
+#define	r17	17
+#define	r18	18
+#define	r19	19
+#define	r20	20
+#define	r21	21
+#define	r22	22
+#define	r23	23
+#define	r24	24
+#define	r25	25
+#define	r26	26
+#define	r27	27
+#define	r28	28
+#define	r29	29
+#define	r30	30
+#define	r31	31

target/linux/mpc85xx/image/spi-loader/include/serial.h

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: BSD-2-Clause
+
+#pragma once
+
+int serial_console_getchar(void);
+int serial_console_tstc(void);
+void serial_console_putchar(char c);
+void serial_console_init(void);
+

target/linux/mpc85xx/image/spi-loader/include/spi-nor.h

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#pragma once
+
+#include <types.h>
+
+int spi_nor_read_id(void);
+int spi_nor_read_data(void *dest, size_t pos, size_t len);

target/linux/mpc85xx/image/spi-loader/include/spi.h

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Common SPI Interface: Controller-specific definitions
+ *
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ *
+ * Based on U-boot's spi.h:
+ *
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ */
+
+#pragma once
+
+#include <types.h>
+
+/* SPI mode flags */
+#define SPI_CPHA	BIT(0)	/* clock phase (1 = SPI_CLOCK_PHASE_SECOND) */
+#define SPI_CPOL	BIT(1)	/* clock polarity (1 = SPI_POLARITY_HIGH) */
+#define SPI_MODE_0	(0|0)			/* (original MicroWire) */
+#define SPI_MODE_1	(0|SPI_CPHA)
+#define SPI_MODE_2	(SPI_CPOL|0)
+#define SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
+
+struct spi_transfer {
+	const void *tx_buf;
+	void *rx_buf;
+	size_t len;
+};
+
+static inline size_t spi_message_len(const struct spi_transfer *msg, int n) {
+	size_t total = 0;
+	for (int i = 0; i < n; i++) {
+		total += msg[i].len;
+	}
+	return total;
+}
+
+int spi_init(unsigned int cs, unsigned int max_hz, unsigned int mode);
+int spi_claim_bus(void);
+void spi_release_bus(void);
+int spi_xfer(const struct spi_transfer *msg, int n);
+size_t spi_max_xfer(void);

target/linux/mpc85xx/image/spi-loader/include/stdio.h

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#pragma once
+
+#include <serial.h>
+#include <types.h>
+
+static inline int getchar(void)
+{
+	return serial_console_getchar();
+}
+
+static inline int tstc(void)
+{
+	return serial_console_tstc();
+}
+
+static inline int putchar(char c)
+{
+	if (c == '\n')
+		serial_console_putchar('\r');
+	serial_console_putchar(c);
+	return 0;
+}
+
+int puts(const char *s);
+
+/* Utility functions */
+void put_u4(uint8_t v);
+void put_u8(uint8_t v);
+void put_u16(uint16_t v);
+void put_u32(uint32_t v);
+void put_ptr(const void *p);
+void put_array(const void *p, size_t l);
+
+#define put_with_label(label, put, value) do { \
+		puts(label); \
+		put(value); \
+		puts("\n"); \
+	} while (0)

target/linux/mpc85xx/image/spi-loader/include/string.h

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#pragma once
+
+#include <stddef.h>
+
+extern char *strcpy(char *dest, const char *src);
+extern char *strncpy(char *dest, const char *src, size_t n);
+extern char *strcat(char *dest, const char *src);
+extern char *strchr(const char *s, int c);
+extern char *strrchr(const char *s, int c);
+extern int strcmp(const char *s1, const char *s2);
+extern int strncmp(const char *s1, const char *s2, size_t n);
+extern size_t strlen(const char *s);
+extern size_t strnlen(const char *s, size_t count);
+
+extern void *memset(void *s, int c, size_t n);
+extern void *memmove(void *dest, const void *src, unsigned long n);
+extern void *memcpy(void *dest, const void *src, unsigned long n);
+extern void *memchr(const void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t n);
+
+extern void flush_cache(void *, unsigned long);

target/linux/mpc85xx/image/spi-loader/include/types.h

@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Code originates from Linux kernel arch/powerpc/boot
+ * (types.h, swab.h, of.h)
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#define BIT(nr)	(1UL << (nr))
+
+#define min(x,y) ({ \
+	typeof(x) _x = (x);	\
+	typeof(y) _y = (y);	\
+	(void) (&_x == &_y);	\
+	_x < _y ? _x : _y; })
+
+#define max(x,y) ({ \
+	typeof(x) _x = (x);	\
+	typeof(y) _y = (y);	\
+	(void) (&_x == &_y);	\
+	_x > _y ? _x : _y; })
+
+#define min_t(type, a, b) min(((type) a), ((type) b))
+#define max_t(type, a, b) max(((type) a), ((type) b))
+
+static inline uint16_t swab16(uint16_t x)
+{
+	return  ((x & (uint16_t)0x00ffU) << 8) |
+		((x & (uint16_t)0xff00U) >> 8);
+}
+
+static inline uint32_t swab32(uint32_t x)
+{
+	return  ((x & (uint32_t)0x000000ffUL) << 24) |
+		((x & (uint32_t)0x0000ff00UL) <<  8) |
+		((x & (uint32_t)0x00ff0000UL) >>  8) |
+		((x & (uint32_t)0xff000000UL) >> 24);
+}
+
+static inline uint64_t swab64(uint64_t x)
+{
+	return  (uint64_t)((x & (uint64_t)0x00000000000000ffULL) << 56) |
+		(uint64_t)((x & (uint64_t)0x000000000000ff00ULL) << 40) |
+		(uint64_t)((x & (uint64_t)0x0000000000ff0000ULL) << 24) |
+		(uint64_t)((x & (uint64_t)0x00000000ff000000ULL) <<  8) |
+		(uint64_t)((x & (uint64_t)0x000000ff00000000ULL) >>  8) |
+		(uint64_t)((x & (uint64_t)0x0000ff0000000000ULL) >> 24) |
+		(uint64_t)((x & (uint64_t)0x00ff000000000000ULL) >> 40) |
+		(uint64_t)((x & (uint64_t)0xff00000000000000ULL) >> 56);
+}
+
+#ifdef __LITTLE_ENDIAN__
+#define cpu_to_be16(x) swab16(x)
+#define be16_to_cpu(x) swab16(x)
+#define cpu_to_be32(x) swab32(x)
+#define be32_to_cpu(x) swab32(x)
+#define cpu_to_be64(x) swab64(x)
+#define be64_to_cpu(x) swab64(x)
+#else
+#define cpu_to_be16(x) (x)
+#define be16_to_cpu(x) (x)
+#define cpu_to_be32(x) (x)
+#define be32_to_cpu(x) (x)
+#define cpu_to_be64(x) (x)
+#define be64_to_cpu(x) (x)
+#endif

target/linux/mpc85xx/image/spi-loader/loader.c

@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#include <image.h>
+#include <init.h>
+#include <spi.h>
+#include <spi-nor.h>
+#include <stdio.h>
+#include <string.h>
+
+static bool check_image_header(const image_header_t *header)
+{
+	if (header->ih_magic != cpu_to_be32(IH_MAGIC_OKLI)) {
+		puts("Invalid image magic\n");
+		return false;
+	}
+
+	if (header->ih_comp != cpu_to_be32(IH_COMP_NONE)) {
+		puts("Unsupported compressed image\n");
+		return false;
+	}
+
+	return true;
+}
+
+static uint32_t do_load(void)
+{
+	image_header_t header;
+	uint32_t ih_size, ih_load, ih_ep;
+
+	if (spi_nor_read_id())
+		return UINT32_MAX;
+
+	puts("Reading image header...\n");
+	if (spi_nor_read_data(&header, CONFIG_IMAGE_OFFSET, sizeof(header)))
+		return UINT32_MAX;
+
+	if (!check_image_header(&header))
+		return UINT32_MAX;
+
+	header.ih_name[sizeof(header.ih_name) - 1] = 0;
+	ih_size = be32_to_cpu(header.ih_size);
+	ih_load = be32_to_cpu(header.ih_load);
+	ih_ep = be32_to_cpu(header.ih_ep);
+
+	put_with_label("Image Name:   ", puts, (const char *)header.ih_name);
+	put_with_label("Data Size:    ", put_u32, ih_size);
+	put_with_label("Load Address: ", put_u32, ih_load);
+	put_with_label("Entry Point:  ", put_u32, ih_ep);
+
+	puts("Reading image data...\n");
+	void *loadaddr = (void *)ih_load;
+	if (spi_nor_read_data(loadaddr, CONFIG_IMAGE_OFFSET + sizeof(header),
+			      ih_size))
+		return false;
+
+	flush_cache(loadaddr, ih_size);
+
+	return ih_ep;
+}
+
+static void enter_image(uint32_t addr)
+{
+	typedef void (*entry_t)(void);
+	entry_t entry = (entry_t)addr;
+
+	puts("Starting image...\n");
+	entry();
+}
+
+static void load(void)
+{
+	uint32_t addr;
+	int ret;
+
+	ret = spi_init(0, CONFIG_SPI_MAX_HZ, SPI_MODE_0);
+	if (ret) {
+		puts("Failed to initialize SPI controller\n");
+		return;
+	}
+
+	ret = spi_claim_bus();
+	if (ret) {
+		puts("Failed to enable SPI controller\n");
+		return;
+	}
+
+	addr = do_load();
+
+	spi_release_bus();
+
+	if (addr != UINT32_MAX)
+		enter_image(addr);
+}
+
+void start(void)
+{
+	serial_console_init();
+	puts("=== " CONFIG_PROGRAM_NAME " ===\n");
+
+	load();
+
+	puts("Halting execution.\n");
+	while (true) {}
+}

target/linux/mpc85xx/image/spi-loader/loader.lds

@@ -0,0 +1,31 @@
+OUTPUT_ARCH(powerpc:common)
+ENTRY(_start)
+EXTERN(_start)
+SECTIONS {
+	.text :
+	{
+		_text_start = .;
+		*(.text*)
+		_text_len = ABSOLUTE(. - _text_start);
+	}
+	.data :
+	{
+		_data_start = .;
+		*(.rodata*)
+		*(.data*)
+		*(.sdata*)
+		_data_len = ABSOLUTE(. - _data_start);
+	}
+	. = ALIGN(4096);
+	.bss :
+	{
+		_bss_start = .;
+		. += 4K;
+		_stack_top = .;
+		*(.bss*)
+		*(.sbss*)
+		_bss_len = ABSOLUTE(. - _bss_start);
+	}
+	. = ALIGN(4096);
+	_end = .;
+}

target/linux/mpc85xx/image/spi-loader/stdio.c

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2022 Matthias Schiffer <mschiffer@universe-factory.net>
+ */
+
+#include <stdio.h>
+
+int puts(const char *s)
+{
+	while (*s)
+		putchar(*s++);
+	return 0;
+}
+
+void put_u4(uint8_t v)
+{
+	v &= 0xf;
+	switch (v) {
+	case 0x0 ... 0x9:
+		putchar('0' + v);
+		break;
+	case 0xa ... 0xf:
+		putchar('a' + (v - 0xa));
+	}
+}
+
+void put_u8(uint8_t v)
+{
+	put_u4(v >> 4);
+	put_u4(v);
+}
+
+void put_u16(uint16_t v)
+{
+	put_u8(v >> 8);
+	put_u8(v);
+}
+
+void put_u32(uint32_t v)
+{
+	put_u16(v >> 16);
+	put_u16(v);
+}
+
+void put_ptr(const void *p)
+{
+	put_u32((uint32_t)p);
+}
+
+void put_array(const void *p, size_t l)
+{
+	const uint8_t *c = p;
+	size_t i;
+	for (i = 0; i < l; i++) {
+		put_u8(c[i]);
+		putchar(' ');
+	}
+	putchar('\n');
+}

target/linux/mpc85xx/image/spi-loader/string.S

@@ -0,0 +1,265 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) Paul Mackerras 1997.
+ *
+ * NOTE: this code runs in 32 bit mode and is packaged as ELF32.
+ */
+
+#include <ppc_asm.h>
+
+	.text
+	.globl	strcpy
+strcpy:
+	addi	r5,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r0,1(r4)
+	cmpwi	0,r0,0
+	stbu	r0,1(r5)
+	bne	1b
+	blr
+
+	.globl	strncpy
+strncpy:
+	cmpwi	0,r5,0
+	beqlr
+	mtctr	r5
+	addi	r6,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r0,1(r4)
+	cmpwi	0,r0,0
+	stbu	r0,1(r6)
+	bdnzf	2,1b		/* dec ctr, branch if ctr != 0 && !cr0.eq */
+	blr
+
+	.globl	strcat
+strcat:
+	addi	r5,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r0,1(r5)
+	cmpwi	0,r0,0
+	bne	1b
+	addi	r5,r5,-1
+1:	lbzu	r0,1(r4)
+	cmpwi	0,r0,0
+	stbu	r0,1(r5)
+	bne	1b
+	blr
+
+	.globl	strchr
+strchr:
+	addi	r3,r3,-1
+1:	lbzu	r0,1(r3)
+	cmpw	0,r0,r4
+	beqlr
+	cmpwi	0,r0,0
+	bne	1b
+	li	r3,0
+	blr
+
+	.globl	strcmp
+strcmp:
+	addi	r5,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r3,1(r5)
+	cmpwi	1,r3,0
+	lbzu	r0,1(r4)
+	subf.	r3,r0,r3
+	beqlr	1
+	beq	1b
+	blr
+
+	.globl	strncmp
+strncmp:
+	mtctr	r5
+	addi	r5,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r3,1(r5)
+	cmpwi	1,r3,0
+	lbzu	r0,1(r4)
+	subf.	r3,r0,r3
+	beqlr	1
+	bdnzt	eq,1b
+	blr
+
+	.globl	strlen
+strlen:
+	addi	r4,r3,-1
+1:	lbzu	r0,1(r4)
+	cmpwi	0,r0,0
+	bne	1b
+	subf	r3,r3,r4
+	blr
+
+	.globl	memset
+memset:
+	rlwimi	r4,r4,8,16,23
+	rlwimi	r4,r4,16,0,15
+	addi	r6,r3,-4
+	cmplwi	0,r5,4
+	blt	7f
+	stwu	r4,4(r6)
+	beqlr
+	andi.	r0,r6,3
+	add	r5,r0,r5
+	subf	r6,r0,r6
+	rlwinm	r0,r5,32-2,2,31
+	mtctr	r0
+	bdz	6f
+1:	stwu	r4,4(r6)
+	bdnz	1b
+6:	andi.	r5,r5,3
+7:	cmpwi	0,r5,0
+	beqlr
+	mtctr	r5
+	addi	r6,r6,3
+8:	stbu	r4,1(r6)
+	bdnz	8b
+	blr
+
+	.globl	memmove
+memmove:
+	cmplw	0,r3,r4
+	bgt	backwards_memcpy
+	/* fall through */
+
+	.globl	memcpy
+memcpy:
+	rlwinm.	r7,r5,32-3,3,31		/* r7 = r5 >> 3 */
+	addi	r6,r3,-4
+	addi	r4,r4,-4
+	beq	3f			/* if less than 8 bytes to do */
+	andi.	r0,r6,3			/* get dest word aligned */
+	mtctr	r7
+	bne	5f
+	andi.	r0,r4,3			/* check src word aligned too */
+	bne	3f
+1:	lwz	r7,4(r4)
+	lwzu	r8,8(r4)
+	stw	r7,4(r6)
+	stwu	r8,8(r6)
+	bdnz	1b
+	andi.	r5,r5,7
+2:	cmplwi	0,r5,4
+	blt	3f
+	lwzu	r0,4(r4)
+	addi	r5,r5,-4
+	stwu	r0,4(r6)
+3:	cmpwi	0,r5,0
+	beqlr
+	mtctr	r5
+	addi	r4,r4,3
+	addi	r6,r6,3
+4:	lbzu	r0,1(r4)
+	stbu	r0,1(r6)
+	bdnz	4b
+	blr
+5:	subfic	r0,r0,4
+	cmpw	cr1,r0,r5
+	add	r7,r0,r4
+	andi.	r7,r7,3			/* will source be word-aligned too? */
+	ble	cr1,3b
+	bne	3b			/* do byte-by-byte if not */
+	mtctr	r0
+6:	lbz	r7,4(r4)
+	addi	r4,r4,1
+	stb	r7,4(r6)
+	addi	r6,r6,1
+	bdnz	6b
+	subf	r5,r0,r5
+	rlwinm.	r7,r5,32-3,3,31
+	beq	2b
+	mtctr	r7
+	b	1b
+
+	.globl	backwards_memcpy
+backwards_memcpy:
+	rlwinm.	r7,r5,32-3,3,31		/* r7 = r5 >> 3 */
+	add	r6,r3,r5
+	add	r4,r4,r5
+	beq	3f
+	andi.	r0,r6,3
+	mtctr	r7
+	bne	5f
+	andi.	r0,r4,3
+	bne	3f
+1:	lwz	r7,-4(r4)
+	lwzu	r8,-8(r4)
+	stw	r7,-4(r6)
+	stwu	r8,-8(r6)
+	bdnz	1b
+	andi.	r5,r5,7
+2:	cmplwi	0,r5,4
+	blt	3f
+	lwzu	r0,-4(r4)
+	subi	r5,r5,4
+	stwu	r0,-4(r6)
+3:	cmpwi	0,r5,0
+	beqlr
+	mtctr	r5
+4:	lbzu	r0,-1(r4)
+	stbu	r0,-1(r6)
+	bdnz	4b
+	blr
+5:	cmpw	cr1,r0,r5
+	subf	r7,r0,r4
+	andi.	r7,r7,3
+	ble	cr1,3b
+	bne	3b
+	mtctr	r0
+6:	lbzu	r7,-1(r4)
+	stbu	r7,-1(r6)
+	bdnz	6b
+	subf	r5,r0,r5
+	rlwinm.	r7,r5,32-3,3,31
+	beq	2b
+	mtctr	r7
+	b	1b
+
+	.globl	memchr
+memchr:
+	cmpwi	0,r5,0
+	blelr
+	mtctr	r5
+	addi	r3,r3,-1
+1:	lbzu	r0,1(r3)
+	cmpw	r0,r4
+	beqlr
+	bdnz	1b
+	li	r3,0
+	blr
+
+	.globl	memcmp
+memcmp:
+	cmpwi	0,r5,0
+	ble	2f
+	mtctr	r5
+	addi	r6,r3,-1
+	addi	r4,r4,-1
+1:	lbzu	r3,1(r6)
+	lbzu	r0,1(r4)
+	subf.	r3,r0,r3
+	bdnzt	2,1b
+	blr
+2:	li	r3,0
+	blr
+
+
+/*
+ * Flush the dcache and invalidate the icache for a range of addresses.
+ *
+ * flush_cache(addr, len)
+ */
+	.global	flush_cache
+flush_cache:
+	addi	4,4,0x1f	/* len = (len + 0x1f) / 0x20 */
+	rlwinm.	4,4,27,5,31
+	mtctr	4
+	beqlr
+1:	dcbf	0,3
+	icbi	0,3
+	addi	3,3,0x20
+	bdnz	1b
+	sync
+	isync
+	blr
+

target/linux/mpc85xx/p1010/config-default

@@ -0,0 +1,31 @@
+CONFIG_AT803X_PHY=y
+CONFIG_BR200_WP=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_FIREBOX_T10=y
+# CONFIG_FSL_CORENET_CF is not set
+CONFIG_GPIO_74X164=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K=y
+CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
+CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_PHYLINK=y
+CONFIG_REALTEK_PHY=y
+CONFIG_RED_15W_REV1=y
+CONFIG_REGMAP=y
+CONFIG_REGULATOR=y
+CONFIG_SPI_GPIO=y
+CONFIG_TL_WDR4900_V1=y
+CONFIG_UBIFS_FS=y
+CONFIG_WS_AP3715I=y

target/linux/mpc85xx/p1010/profiles/00-default.mk

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+define Profile/Default
+  NAME:=Default Profile
+  PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most P1010 boards.
+endef
+
+$(eval $(call Profile,Default))

target/linux/mpc85xx/p1010/target.mk

@@ -0,0 +1,7 @@
+BOARDNAME:=P1010
+KERNEL_IMAGES:=simpleImage.br200-wp simpleImage.tl-wdr4900-v1 simpleImage.ws-ap3715i
+
+define Target/Description
+	Build firmware images for P1010 based boards.
+endef
+

target/linux/mpc85xx/p1020/config-default

@@ -0,0 +1,57 @@
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_AT803X_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_CPU_RMAP=y
+CONFIG_EEPROM_LEGACY=y
+# CONFIG_FSL_CORENET_CF is not set
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_GPIO_74X164=y
+# CONFIG_GPIO_MAX77620 is not set
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_HIVEAP_330=y
+CONFIG_PANDA=y
+CONFIG_MSM460=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_LEDS_LP5521=y
+CONFIG_LEDS_LP55XX_COMMON=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+# CONFIG_MAX77620_THERMAL is not set
+# CONFIG_MAX77620_WATCHDOG is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGULATOR=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_RTC_DRV_MAX77686 is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SMP=y
+CONFIG_SPI_GPIO=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_B53=y
+# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
+CONFIG_SWCONFIG_B53_PHY_DRIVER=y
+# CONFIG_SWCONFIG_B53_PHY_FIXUP is not set
+# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set
+# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_WS_AP3710I=y
+CONFIG_WS_AP3825I=y
+CONFIG_XPS=y

target/linux/mpc85xx/p1020/profiles/00-default.mk

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+define Profile/Default
+  NAME:=Default Profile
+  PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most P1020 boards.
+endef
+
+$(eval $(call Profile,Default))

target/linux/mpc85xx/p1020/target.mk

@@ -0,0 +1,6 @@
+BOARDNAME:=P1020
+KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330 zImage.la3000000
+
+define Target/Description
+	Build firmware images for Freescale P1020 based boards.
+endef

target/linux/mpc85xx/p2020/config-default

@@ -0,0 +1,45 @@
+CONFIG_BLK_DEV_NVME=y
+CONFIG_CPU_RMAP=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_FSL_ULI1575=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAX63XX_WATCHDOG=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MPC85xx_RDB=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NR_CPUS=2
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_PADATA=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PPC_I8259=y
+CONFIG_PPC_MSI_BITMAP=y
+CONFIG_PPC_P2020=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SMP=y
+CONFIG_SWIOTLB=y
+CONFIG_TARGET_CPU="8540"
+CONFIG_TARGET_CPU_BOOL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_XPS=y

target/linux/mpc85xx/p2020/profiles/00-default.mk

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+define Profile/Default
+  NAME:=Default Profile
+  PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most P2020 boards.
+endef
+
+$(eval $(call Profile,Default))

target/linux/mpc85xx/p2020/target.mk

@@ -0,0 +1,5 @@
+BOARDNAME:=P2020
+
+define Target/Description
+	Build firmware images for Freescale P2020 based boards.
+endef

target/linux/mpc85xx/patches-6.1/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch

@@ -0,0 +1,10 @@
+--- a/arch/powerpc/platforms/85xx/common.c
++++ b/arch/powerpc/platforms/85xx/common.c
+@@ -30,6 +30,7 @@ static const struct of_device_id mpc85xx
+ 	{ .compatible = "fsl,mpc8548-guts", },
+ 	/* Probably unnecessary? */
+ 	{ .compatible = "gpio-leds", },
++	{ .compatible = "gpio-keys", },
+ 	/* For all PCI controllers */
+ 	{ .compatible = "fsl,mpc8540-pci", },
+ 	{ .compatible = "fsl,mpc8548-pcie", },

target/linux/mpc85xx/patches-6.1/010-powerpc-add-compressed-zImage-for-mpc85xx.patch

@@ -0,0 +1,61 @@
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper  | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -175,6 +175,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot
+ src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
+ src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
+ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
++src-plat-$(CONFIG_PPC_ZIMAGE_LA3000000) += fixed-head.S
+ src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+@@ -345,6 +346,7 @@ image-$(CONFIG_MPC836x_MDS)		+= cuImage.
+ image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
+ 
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-$(CONFIG_PPC_ZIMAGE_LA3000000)   += zImage.la3000000
+ image-$(CONFIG_MPC8540_ADS)		+= cuImage.mpc8540ads
+ image-$(CONFIG_MPC8560_ADS)		+= cuImage.mpc8560ads
+ image-$(CONFIG_MPC85xx_CDS)		+= cuImage.mpc8541cds \
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -254,6 +254,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+ 
+ case "$platform" in
++la3000000)
++    binary=y
++    platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++    link_address='0x3000000'
++    ;;
+ of)
+     platformo="$object/of.o $object/epapr.o"
+     make_space=n
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -74,6 +74,10 @@ config NMI_IPI
+ 	depends on SMP && (DEBUGGER || KEXEC_CORE || HARDLOCKUP_DETECTOR)
+ 	default y
+ 
++config PPC_ZIMAGE_LA3000000
++       bool
++       default n
++
+ config PPC_WATCHDOG
+ 	bool
+ 	depends on HARDLOCKUP_DETECTOR

target/linux/mpc85xx/patches-6.1/100-powerpc-85xx-tl-wdr4900-v1-support.patch

@@ -0,0 +1,83 @@
+From 1d9f596e572917772b87a2a37e1680902964782f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 20 Feb 2013 08:40:33 +0100
+Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1
+ board
+
+This patch adds support for the TP-Link TL-WDR4900 v1
+concurrent dual-band wireless router. The devices uses
+the Freescale P1014 SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/Makefile           |  3 ++-
+ arch/powerpc/boot/wrapper            |  5 +++++
+ arch/powerpc/platforms/85xx/Kconfig  | 12 ++++++++++++
+ arch/powerpc/platforms/85xx/Makefile |  1 +
+ 4 files changed, 20 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -361,7 +362,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+-
++image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -346,6 +346,11 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-tl-wdr4900-v1)
++    platformo="$object/fixed-head.o $object/simpleboot.o"
++    link_address='0x1500000'
++    binary=y
++    ;;
+ simpleboot-*)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     binary=y
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -163,6 +163,18 @@ config STX_GP3
+ 	select CPM2
+ 	select DEFAULT_UIMAGE
+ 
++config TL_WDR4900_V1
++    bool "TP-Link TL-WDR4900 v1"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    select SWIOTLB
++    help
++      This option enables support for the TP-Link TL-WDR4900 v1 board.
++
++      This board is a Concurrent Dual-Band wireless router with a
++      Freescale P1014 SoC.
++
+ config TQM8540
+ 	bool "TQ Components TQM8540"
+ 	help
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
++obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
+ obj-$(CONFIG_TQM85xx)	  += tqm85xx.o
+ obj-$(CONFIG_PPA8548)     += ppa8548.o
+ obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o

target/linux/mpc85xx/patches-6.1/101-powerpc-85xx-hiveap-330-support.patch

@@ -0,0 +1,58 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -40,6 +40,17 @@ config BSC9132_QDS
+ 	  and dual StarCore SC3850 DSP cores.
+ 	  Manufacturer : Freescale Semiconductor, Inc
+ 
++config HIVEAP_330
++    bool "Aerohive HiveAP-330"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    help
++      This option enables support for the Aerohive HiveAP-330 board.
++
++      This board is a Concurrent Dual-Band wireless access point with a
++      Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -12,6 +12,7 @@ obj-y += common.o
+ obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+ obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
+ obj-$(CONFIG_C293_PCIE)   += c293pcie.o
++obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
+ obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
+ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
+ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -362,6 +363,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
++image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -346,6 +346,7 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'

target/linux/mpc85xx/patches-6.1/102-powerpc-add-cmdline-override.patch

@@ -0,0 +1,37 @@
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -958,6 +958,14 @@ config CMDLINE_FORCE
+ 
+ endchoice
+ 
++config CMDLINE_OVERRIDE
++    bool "Use alternative cmdline from device tree"
++    help
++      Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++      be used, this is not a good option for kernels that are shared across
++      devices. This setting enables using "chosen/cmdline-override" as the
++      cmdline if it exists in the device tree.
++
+ config EXTRA_TARGETS
+ 	string "Additional default image types"
+ 	help
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
+ 	if (p != NULL && l > 0)
+ 		strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
+ 
++    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++     * device tree option of chosen/bootargs-override. This is
++     * helpful on boards where u-boot sets bootargs, and is unable
++     * to be modified.
++     */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++	if (p != NULL && l > 0)
++		strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ handle_cmdline:
+ 	/*
+ 	 * CONFIG_CMDLINE is meant to be a default in case nothing else

target/linux/mpc85xx/patches-6.1/103-powerpc-85xx-red-15w-rev1.patch

@@ -0,0 +1,29 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -166,6 +166,16 @@ config XES_MPC85xx
+ 	  Manufacturer: Extreme Engineering Solutions, Inc.
+ 	  URL: <https://www.xes-inc.com/>
+ 
++config RED_15W_REV1
++	bool "Sophos RED 15w Rev.1"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Sophos RED 15w Rev.1 board.
++
++	  This board is a wireless VPN router with a Freescale P1010 SoC.
++
+ config STX_GP3
+ 	bool "Silicon Turnkey Express GP3"
+ 	help
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
++obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+ obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
+ obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
+ obj-$(CONFIG_TQM85xx)	  += tqm85xx.o

target/linux/mpc85xx/patches-6.1/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch

@@ -0,0 +1,170 @@
+From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Sun, 30 Dec 2018 23:24:41 +0100
+Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
+
+This patch apply chages for OpenWRT in P2020RDB
+dts file.
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
+ 1 file changed, 63 insertions(+), 35 deletions(-)
+
+--- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
++++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
+@@ -5,10 +5,15 @@
+  * Copyright 2009-2012 Freescale Semiconductor Inc.
+  */
+ 
++/dts-v1/;
++
+ /include/ "p2020si-pre.dtsi"
+ 
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
+ / {
+-	model = "fsl,P2020RDB";
++	model = "Freescale P2020RDB";
+ 	compatible = "fsl,P2020RDB";
+ 
+ 	aliases {
+@@ -34,48 +39,38 @@
+ 			  0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 
+ 		nor@0,0 {
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+ 			compatible = "cfi-flash";
+ 			reg = <0x0 0x0 0x1000000>;
+ 			bank-width = <2>;
+ 			device-width = <1>;
+ 
+-			partition@0 {
+-				/* This location must not be altered  */
+-				/* 256KB for Vitesse 7385 Switch firmware */
+-				reg = <0x0 0x00040000>;
+-				label = "NOR (RO) Vitesse-7385 Firmware";
+-				read-only;
+-			};
+-
+-			partition@40000 {
+-				/* 256KB for DTB Image */
+-				reg = <0x00040000 0x00040000>;
+-				label = "NOR (RO) DTB Image";
+-				read-only;
+-			};
++			partitions {
++				compatible = "fixed-partitions";
++				#address-cells = <1>;
++				#size-cells = <1>;
+ 
+-			partition@80000 {
+-				/* 3.5 MB for Linux Kernel Image */
+-				reg = <0x00080000 0x00380000>;
+-				label = "NOR (RO) Linux Kernel Image";
+-				read-only;
+-			};
++				partition@0 {
++					/* This location must not be altered  */
++					/* 256KB for Vitesse 7385 Switch firmware */
++					reg = <0x0 0x00040000>;
++					label = "NOR (RO) Vitesse-7385 Firmware";
++					read-only;
++				};
+ 
+-			partition@400000 {
+-				/* 11MB for JFFS2 based Root file System */
+-				reg = <0x00400000 0x00b00000>;
+-				label = "NOR (RW) JFFS2 Root File System";
+-			};
++				partition@40000 {
++					compatible = "denx,fit";
++					reg = <0x00040000 0x00ec0000>;
++					label = "firmware";
++				};
+ 
+-			partition@f00000 {
+-				/* This location must not be altered  */
+-				/* 512KB for u-boot Bootloader Image */
+-				/* 512KB for u-boot Environment Variables */
+-				reg = <0x00f00000 0x00100000>;
+-				label = "NOR (RO) U-Boot Image";
+-				read-only;
++				partition@f00000 {
++					/* This location must not be altered  */
++					/* 512KB for u-boot Bootloader Image */
++					/* 512KB for u-boot Environment Variables */
++					reg = <0x00f00000 0x00100000>;
++					label = "u-boot";
++					read-only;
++				};
+ 			};
+ 		};
+ 
+@@ -85,6 +80,7 @@
+ 			compatible = "fsl,p2020-fcm-nand",
+ 				     "fsl,elbc-fcm-nand";
+ 			reg = <0x1 0x0 0x40000>;
++			nand-ecc-mode = "none";
+ 
+ 			partition@0 {
+ 				/* This location must not be altered  */
+@@ -140,13 +136,43 @@
+ 	soc: soc@ffe00000 {
+ 		ranges = <0x0 0x0 0xffe00000 0x100000>;
+ 
++		gpio0: gpio-controller@fc00 {
++		};
++
+ 		i2c@3000 {
++			temperature-sensor@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++
++			eeprom@50 {
++				compatible = "atmel,24c256";
++				reg = <0x50>;
++			};
++
+ 			rtc@68 {
+ 				compatible = "dallas,ds1339";
+ 				reg = <0x68>;
+ 			};
+ 		};
+ 
++		i2c@3100 {
++			pmic@11 {
++				compatible = "zl2006";
++				reg = <0x11>;
++			};
++
++			gpio@18 {
++				compatible = "nxp,pca9557";
++				reg = <0x18>;
++			};
++
++			eeprom@52 {
++				compatible = "atmel,24c01";
++				reg = <0x52>;
++			};
++		};
++
+ 		spi@7000 {
+ 			flash@0 {
+ 				#address-cells = <1>;
+@@ -200,10 +226,12 @@
+ 			phy0: ethernet-phy@0 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x0>;
++				reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ 			};
+ 			phy1: ethernet-phy@1 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x1>;
++				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ 			};
+ 			tbi-phy@2 {
+ 				device_type = "tbi-phy";

target/linux/mpc85xx/patches-6.1/105-powerpc-85xx-panda-support.patch

@@ -0,0 +1,30 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -51,6 +51,17 @@ config HIVEAP_330
+       This board is a Concurrent Dual-Band wireless access point with a
+       Freescale P1020 SoC.
+ 
++config PANDA
++	bool "OCEDO PANDA"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the OCEDO PANDA board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -24,6 +24,7 @@ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
+ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
++obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o

target/linux/mpc85xx/patches-6.1/106-powerpc-85xx-ws-ap3710i-support.patch

@@ -0,0 +1,60 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -62,6 +62,17 @@ config PANDA
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3710I
++	bool "Enterasys WS-AP3710i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Enterasys WS-AP3710i board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
+ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
+ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
++obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -365,6 +366,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -347,7 +347,8 @@ adder875-redboot)
+     binary=y
+     ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y

target/linux/mpc85xx/patches-6.1/107-powerpc-85xx-add-ws-ap3825i-support.patch

@@ -0,0 +1,67 @@
+From 2fa1a7983ef30f3c7486f9b07c001bee87d1f6d6 Mon Sep 17 00:00:00 2001
+From: Martin Kennedy <hurricos@gmail.com>
+Date: Sat, 1 Jan 2022 11:01:37 -0500
+Subject: [PATCH] PowerPC 85xx: Add WS-AP3825i support
+
+This patch adds support for building Linux for the Extreme Networks
+WS-AP3825i AP.
+
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -73,6 +73,16 @@ config WS_AP3710I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3825I
++	bool "Extreme Networks WS-AP3825i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Extreme Networks WS-AP3825i board.
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
+ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
++obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -367,6 +368,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
++image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -348,7 +348,8 @@ adder875-redboot)
+     ;;
+ simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y

target/linux/mpc85xx/patches-6.1/108-powerpc-85xx-firebox-t10-support.patch.patch

@@ -0,0 +1,29 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -83,6 +83,16 @@ config WS_AP3825I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config FIREBOX_T10
++	bool "Watchguard Firebox T10"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Watchguard Firebox T10 board.
++	  This board is a VPN Gateway-Router with a
++	  Freescale P1010 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -28,6 +28,7 @@ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
+ obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
++obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o

target/linux/mpc85xx/patches-6.1/109-powerpc-85xx-add-ws-ap3715i-support.patch

@@ -0,0 +1,48 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -73,6 +73,17 @@ config WS_AP3710I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3715I
++	bool "Enterasys WS-AP3715i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Enterasys WS-AP3715i board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1010 SoC.
++
+ config WS_AP3825I
+ 	bool "Extreme Networks WS-AP3825i"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
+ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
++obj-$(CONFIG_WS_AP3715I)  += ws-ap3715i.o
+ obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
+ obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -368,6 +369,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
++image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100

target/linux/mpc85xx/patches-6.1/110-powerpc-85xx-br200-wp-support.patch

@@ -0,0 +1,57 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -40,6 +40,16 @@ config BSC9132_QDS
+ 	  and dual StarCore SC3850 DSP cores.
+ 	  Manufacturer : Freescale Semiconductor, Inc
+ 
++config BR200_WP
++    bool "Aerohive BR200-WP"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    help
++      This option enables support for the Aerohive BR200-WP board.
++
++      This board is a wireless router with a Freescale P1011 SoC.
++
+ config HIVEAP_330
+     bool "Aerohive HiveAP-330"
+     select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -12,6 +12,7 @@ obj-y += common.o
+ obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+ obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
+ obj-$(CONFIG_C293_PCIE)   += c293pcie.o
++obj-$(CONFIG_BR200_WP) += br200-wp.o
+ obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
+ obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
+ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -366,6 +367,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
++image-$(CONFIG_BR200_WP)		+= simpleImage.br200-wp
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -346,6 +346,7 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-br200-wp|\
+ simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\

target/linux/mpc85xx/patches-6.1/111-powerpc-85xx-hpe-msm-support.patch

@@ -0,0 +1,31 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,18 @@ config FIREBOX_T10
+ 	  This board is a VPN Gateway-Router with a
+ 	  Freescale P1010 SoC.
+ 
++config MSM460
++	bool "HPE MSM460"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	select PPC_ZIMAGE_LA3000000
++	help
++	  This option enables support for the HPE MSM460 board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.
+ obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460)      += msm460.o
+ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o

target/linux/mpc85xx/patches-6.1/150-arch-powerpc-simpleboot-prevent-overwrite-of-CPU1-sp.patch

@@ -0,0 +1,41 @@
+From 5f856ccc34df25060d36a5a81b7b45b574d86e35 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 3 Dec 2023 20:09:24 +0100
+Subject: [PATCH] arch: powerpc: simpleboot: prevent overwrite of CPU1
+ spin-table
+
+Don't overwrite the spin-table of additional CPU cores with loader-heap.
+
+U-Boot places the spin-table for CPU1 on P1020 SoCs in the top 1MB of
+system-memory. Instead of parsing reserved-memory (which would be
+considerable more work), reduce the available system-memory for the
+loader by 1MB.
+
+This prevents the loader from overwriting the spin-table of
+additional CPU cores on these platforms.
+
+Linux itself needs to be made aware by this using reserved-memory
+definitions.
+
+This patch is required for using CPU1 on the Extreme Networks
+WS-AP3825i.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/simpleboot.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/powerpc/boot/simpleboot.c
++++ b/arch/powerpc/boot/simpleboot.c
+@@ -65,6 +65,11 @@ void platform_init(unsigned long r3, uns
+ 	if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
+ 		memsize64 = 0xffffffff;
+ 
++	/* Reserve upper 1 MB of memory for CPU1 spin-table */
++	if (memsize64 > 0x100000) {
++		memsize64 = memsize64 - 0x100000;
++	}
++
+ 	/* finally, setup the timebase */
+ 	node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+ 					     "cpu", sizeof("cpu"));

target/linux/mpc85xx/patches-6.1/900-powerpc-bootwrapper-disable-uImage-generation.patch

@@ -0,0 +1,42 @@
+From d43ab14605510d9d2bd257a8cd70f24ada4621b0 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 29 Feb 2020 14:27:04 +0100
+Subject: [PATCH] powerpc: bootwrapper: disable uImage generation
+
+Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to
+instruct the mkimage to use the xz compression, which isn't
+supported. This disables the uImage generation, as OpenWrt
+generates individual uImages for each board using it's own
+toolchain.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -294,7 +294,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
+ image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
+ image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
+ image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
+-image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
+ image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
+ 
+ #
+@@ -432,15 +431,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+ $(obj)/vmlinux.strip: vmlinux
+ 	$(STRIP) -s -R .comment $< -o $@
+ 
+-$(obj)/uImage: vmlinux $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot)
+-
+-$(obj)/uImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)
+-
+-$(obj)/uImage.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb)
+-
+ $(obj)/cuImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+ 	$(call if_changed,wrap,cuboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)
+ 

target/linux/mpc85xx/patches-6.6/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch

@@ -0,0 +1,10 @@
+--- a/arch/powerpc/platforms/85xx/common.c
++++ b/arch/powerpc/platforms/85xx/common.c
+@@ -31,6 +31,7 @@ static const struct of_device_id mpc85xx
+ 	{ .compatible = "fsl,mpc8548-guts", },
+ 	/* Probably unnecessary? */
+ 	{ .compatible = "gpio-leds", },
++	{ .compatible = "gpio-keys", },
+ 	/* For all PCI controllers */
+ 	{ .compatible = "fsl,mpc8540-pci", },
+ 	{ .compatible = "fsl,mpc8548-pcie", },

target/linux/mpc85xx/patches-6.6/010-powerpc-add-compressed-zImage-for-mpc85xx.patch

@@ -0,0 +1,61 @@
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper  | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -177,6 +177,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot
+ src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
+ src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
+ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
++src-plat-$(CONFIG_PPC_ZIMAGE_LA3000000) += fixed-head.S
+ src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+@@ -342,6 +343,7 @@ image-$(CONFIG_MPC834x_ITX)		+= cuImage.
+ image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
+ 
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-$(CONFIG_PPC_ZIMAGE_LA3000000)	+= zImage.la3000000
+ image-$(CONFIG_MPC85xx_MDS)		+= cuImage.mpc8568mds
+ image-$(CONFIG_MPC85xx_DS)		+= cuImage.mpc8544ds \
+ 					   cuImage.mpc8572ds
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -258,6 +258,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+ 
+ case "$platform" in
++la3000000)
++    binary=y
++    platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++    link_address='0x3000000'
++    ;;
+ of)
+     platformo="$object/of.o $object/epapr.o"
+     make_space=n
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -88,6 +88,10 @@ config NMI_IPI
+ 	depends on SMP && (DEBUGGER || KEXEC_CORE || HARDLOCKUP_DETECTOR)
+ 	default y
+ 
++config PPC_ZIMAGE_LA3000000
++       bool
++       default n
++
+ config PPC_WATCHDOG
+ 	bool
+ 	depends on HARDLOCKUP_DETECTOR_ARCH

target/linux/mpc85xx/patches-6.6/100-powerpc-85xx-tl-wdr4900-v1-support.patch

@@ -0,0 +1,83 @@
+From 1d9f596e572917772b87a2a37e1680902964782f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 20 Feb 2013 08:40:33 +0100
+Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1
+ board
+
+This patch adds support for the TP-Link TL-WDR4900 v1
+concurrent dual-band wireless router. The devices uses
+the Freescale P1014 SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/Makefile           |  3 ++-
+ arch/powerpc/boot/wrapper            |  5 +++++
+ arch/powerpc/platforms/85xx/Kconfig  | 12 ++++++++++++
+ arch/powerpc/platforms/85xx/Makefile |  1 +
+ 4 files changed, 20 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -353,7 +354,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+-
++image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -350,6 +350,11 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-tl-wdr4900-v1)
++    platformo="$object/fixed-head.o $object/simpleboot.o"
++    link_address='0x1500000'
++    binary=y
++    ;;
+ simpleboot-*)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     binary=y
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -176,6 +176,18 @@ config STX_GP3
+ 	select CPM2
+ 	select DEFAULT_UIMAGE
+ 
++config TL_WDR4900_V1
++    bool "TP-Link TL-WDR4900 v1"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    select SWIOTLB
++    help
++      This option enables support for the TP-Link TL-WDR4900 v1 board.
++
++      This board is a Concurrent Dual-Band wireless router with a
++      Freescale P1014 SoC.
++
+ config TQM8540
+ 	bool "TQ Components TQM8540"
+ 	help
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
++obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
+ obj-$(CONFIG_TQM85xx)	  += tqm85xx.o
+ obj-$(CONFIG_PPA8548)     += ppa8548.o
+ obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o

target/linux/mpc85xx/patches-6.6/101-powerpc-85xx-hiveap-330-support.patch

@@ -0,0 +1,58 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -40,6 +40,17 @@ config BSC9132_QDS
+ 	  and dual StarCore SC3850 DSP cores.
+ 	  Manufacturer : Freescale Semiconductor, Inc
+ 
++config HIVEAP_330
++    bool "Aerohive HiveAP-330"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    help
++      This option enables support for the Aerohive HiveAP-330 board.
++
++      This board is a Concurrent Dual-Band wireless access point with a
++      Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -12,6 +12,7 @@ obj-y += common.o
+ obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+ obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
+ obj-$(CONFIG_C293_PCIE)   += c293pcie.o
++obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
+ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
+ obj8259-$(CONFIG_PPC_I8259)   += mpc85xx_8259.o
+ obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o $(obj8259-y)
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -354,6 +355,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
++image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -350,6 +350,7 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'

target/linux/mpc85xx/patches-6.6/102-powerpc-add-cmdline-override.patch

@@ -0,0 +1,37 @@
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -1009,6 +1009,14 @@ config CMDLINE_FORCE
+ 
+ endchoice
+ 
++config CMDLINE_OVERRIDE
++    bool "Use alternative cmdline from device tree"
++    help
++      Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++      be used, this is not a good option for kernels that are shared across
++      devices. This setting enables using "chosen/cmdline-override" as the
++      cmdline if it exists in the device tree.
++
+ config EXTRA_TARGETS
+ 	string "Additional default image types"
+ 	help
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1189,6 +1189,17 @@ int __init early_init_dt_scan_chosen(cha
+ 	if (p != NULL && l > 0)
+ 		strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
+ 
++    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++     * device tree option of chosen/bootargs-override. This is
++     * helpful on boards where u-boot sets bootargs, and is unable
++     * to be modified.
++     */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++	if (p != NULL && l > 0)
++		strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ handle_cmdline:
+ 	/*
+ 	 * CONFIG_CMDLINE is meant to be a default in case nothing else

target/linux/mpc85xx/patches-6.6/103-powerpc-85xx-red-15w-rev1.patch

@@ -0,0 +1,29 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -179,6 +179,16 @@ config XES_MPC85xx
+ 	  Manufacturer: Extreme Engineering Solutions, Inc.
+ 	  URL: <https://www.xes-inc.com/>
+ 
++config RED_15W_REV1
++	bool "Sophos RED 15w Rev.1"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Sophos RED 15w Rev.1 board.
++
++	  This board is a wireless VPN router with a Freescale P1010 SoC.
++
+ config STX_GP3
+ 	bool "Silicon Turnkey Express GP3"
+ 	help
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_PPC_P2020)   += p2020.o $(o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
++obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+ obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
+ obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
+ obj-$(CONFIG_TQM85xx)	  += tqm85xx.o

target/linux/mpc85xx/patches-6.6/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch

@@ -0,0 +1,170 @@
+From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Sun, 30 Dec 2018 23:24:41 +0100
+Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
+
+This patch apply chages for OpenWRT in P2020RDB
+dts file.
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
+ 1 file changed, 63 insertions(+), 35 deletions(-)
+
+--- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
++++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
+@@ -5,10 +5,15 @@
+  * Copyright 2009-2012 Freescale Semiconductor Inc.
+  */
+ 
++/dts-v1/;
++
+ /include/ "p2020si-pre.dtsi"
+ 
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
+ / {
+-	model = "fsl,P2020RDB";
++	model = "Freescale P2020RDB";
+ 	compatible = "fsl,P2020RDB";
+ 
+ 	aliases {
+@@ -34,48 +39,38 @@
+ 			  0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 
+ 		nor@0,0 {
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+ 			compatible = "cfi-flash";
+ 			reg = <0x0 0x0 0x1000000>;
+ 			bank-width = <2>;
+ 			device-width = <1>;
+ 
+-			partition@0 {
+-				/* This location must not be altered  */
+-				/* 256KB for Vitesse 7385 Switch firmware */
+-				reg = <0x0 0x00040000>;
+-				label = "NOR (RO) Vitesse-7385 Firmware";
+-				read-only;
+-			};
+-
+-			partition@40000 {
+-				/* 256KB for DTB Image */
+-				reg = <0x00040000 0x00040000>;
+-				label = "NOR (RO) DTB Image";
+-				read-only;
+-			};
++			partitions {
++				compatible = "fixed-partitions";
++				#address-cells = <1>;
++				#size-cells = <1>;
+ 
+-			partition@80000 {
+-				/* 3.5 MB for Linux Kernel Image */
+-				reg = <0x00080000 0x00380000>;
+-				label = "NOR (RO) Linux Kernel Image";
+-				read-only;
+-			};
++				partition@0 {
++					/* This location must not be altered  */
++					/* 256KB for Vitesse 7385 Switch firmware */
++					reg = <0x0 0x00040000>;
++					label = "NOR (RO) Vitesse-7385 Firmware";
++					read-only;
++				};
+ 
+-			partition@400000 {
+-				/* 11MB for JFFS2 based Root file System */
+-				reg = <0x00400000 0x00b00000>;
+-				label = "NOR (RW) JFFS2 Root File System";
+-			};
++				partition@40000 {
++					compatible = "denx,fit";
++					reg = <0x00040000 0x00ec0000>;
++					label = "firmware";
++				};
+ 
+-			partition@f00000 {
+-				/* This location must not be altered  */
+-				/* 512KB for u-boot Bootloader Image */
+-				/* 512KB for u-boot Environment Variables */
+-				reg = <0x00f00000 0x00100000>;
+-				label = "NOR (RO) U-Boot Image";
+-				read-only;
++				partition@f00000 {
++					/* This location must not be altered  */
++					/* 512KB for u-boot Bootloader Image */
++					/* 512KB for u-boot Environment Variables */
++					reg = <0x00f00000 0x00100000>;
++					label = "u-boot";
++					read-only;
++				};
+ 			};
+ 		};
+ 
+@@ -85,6 +80,7 @@
+ 			compatible = "fsl,p2020-fcm-nand",
+ 				     "fsl,elbc-fcm-nand";
+ 			reg = <0x1 0x0 0x40000>;
++			nand-ecc-mode = "none";
+ 
+ 			partition@0 {
+ 				/* This location must not be altered  */
+@@ -140,13 +136,43 @@
+ 	soc: soc@ffe00000 {
+ 		ranges = <0x0 0x0 0xffe00000 0x100000>;
+ 
++		gpio0: gpio-controller@fc00 {
++		};
++
+ 		i2c@3000 {
++			temperature-sensor@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++
++			eeprom@50 {
++				compatible = "atmel,24c256";
++				reg = <0x50>;
++			};
++
+ 			rtc@68 {
+ 				compatible = "dallas,ds1339";
+ 				reg = <0x68>;
+ 			};
+ 		};
+ 
++		i2c@3100 {
++			pmic@11 {
++				compatible = "zl2006";
++				reg = <0x11>;
++			};
++
++			gpio@18 {
++				compatible = "nxp,pca9557";
++				reg = <0x18>;
++			};
++
++			eeprom@52 {
++				compatible = "atmel,24c01";
++				reg = <0x52>;
++			};
++		};
++
+ 		spi@7000 {
+ 			flash@0 {
+ 				#address-cells = <1>;
+@@ -200,10 +226,12 @@
+ 			phy0: ethernet-phy@0 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x0>;
++				reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ 			};
+ 			phy1: ethernet-phy@1 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x1>;
++				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ 			};
+ 			tbi-phy@2 {
+ 				device_type = "tbi-phy";

target/linux/mpc85xx/patches-6.6/105-powerpc-85xx-panda-support.patch

@@ -0,0 +1,30 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -51,6 +51,17 @@ config HIVEAP_330
+       This board is a Concurrent Dual-Band wireless access point with a
+       Freescale P1020 SoC.
+ 
++config PANDA
++	bool "OCEDO PANDA"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the OCEDO PANDA board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -22,6 +22,7 @@ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
+ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
++obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_PPC_P2020)   += p2020.o $(obj8259-y)
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o

target/linux/mpc85xx/patches-6.6/106-powerpc-85xx-ws-ap3710i-support.patch

@@ -0,0 +1,60 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -62,6 +62,17 @@ config PANDA
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3710I
++	bool "Enterasys WS-AP3710i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Enterasys WS-AP3710i board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -25,6 +25,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
+ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_PPC_P2020)   += p2020.o $(obj8259-y)
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
++obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -357,6 +358,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -351,7 +351,8 @@ adder875-redboot)
+     binary=y
+     ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y

target/linux/mpc85xx/patches-6.6/107-powerpc-85xx-add-ws-ap3825i-support.patch

@@ -0,0 +1,67 @@
+From 2fa1a7983ef30f3c7486f9b07c001bee87d1f6d6 Mon Sep 17 00:00:00 2001
+From: Martin Kennedy <hurricos@gmail.com>
+Date: Sat, 1 Jan 2022 11:01:37 -0500
+Subject: [PATCH] PowerPC 85xx: Add WS-AP3825i support
+
+This patch adds support for building Linux for the Extreme Networks
+WS-AP3825i AP.
+
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -73,6 +73,16 @@ config WS_AP3710I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3825I
++	bool "Extreme Networks WS-AP3825i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Extreme Networks WS-AP3825i board.
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_PPC_P2020)   += p2020.o $(obj8259-y)
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
++obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -185,6 +185,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -359,6 +360,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
++image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -352,7 +352,8 @@ adder875-redboot)
+     ;;
+ simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y

target/linux/mpc85xx/patches-6.6/108-powerpc-85xx-firebox-t10-support.patch.patch

@@ -0,0 +1,29 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -83,6 +83,16 @@ config WS_AP3825I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config FIREBOX_T10
++	bool "Watchguard Firebox T10"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Watchguard Firebox T10 board.
++	  This board is a VPN Gateway-Router with a
++	  Freescale P1010 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_PPC_P2020)   += p2020.o $(o
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
+ obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
++obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+ obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
+ obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o

target/linux/mpc85xx/patches-6.6/109-powerpc-85xx-add-ws-ap3715i-support.patch

@@ -0,0 +1,48 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -73,6 +73,17 @@ config WS_AP3710I
+ 	  This board is a Concurrent Dual-Band wireless access point with a
+ 	  Freescale P1020 SoC.
+ 
++config WS_AP3715I
++	bool "Enterasys WS-AP3715i"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	help
++	  This option enables support for the Enterasys WS-AP3715i board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1010 SoC.
++
+ config WS_AP3825I
+ 	bool "Extreme Networks WS-AP3825i"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_PANDA)       += panda.o
+ obj-$(CONFIG_PPC_P2020)   += p2020.o $(obj8259-y)
+ obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
+ obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o
++obj-$(CONFIG_WS_AP3715I)  += ws-ap3715i.o
+ obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o
+ obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o
+ obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -185,6 +185,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -360,6 +361,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
++image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100

target/linux/mpc85xx/patches-6.6/110-powerpc-85xx-br200-wp-support.patch

@@ -0,0 +1,57 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -40,6 +40,16 @@ config BSC9132_QDS
+ 	  and dual StarCore SC3850 DSP cores.
+ 	  Manufacturer : Freescale Semiconductor, Inc
+ 
++config BR200_WP
++    bool "Aerohive BR200-WP"
++    select DEFAULT_UIMAGE
++    select ARCH_REQUIRE_GPIOLIB
++    select GPIO_MPC8XXX
++    help
++      This option enables support for the Aerohive BR200-WP board.
++
++      This board is a wireless router with a Freescale P1011 SoC.
++
+ config HIVEAP_330
+     bool "Aerohive HiveAP-330"
+     select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -12,6 +12,7 @@ obj-y += common.o
+ obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+ obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
+ obj-$(CONFIG_C293_PCIE)   += c293pcie.o
++obj-$(CONFIG_BR200_WP) += br200-wp.o
+ obj-$(CONFIG_HIVEAP_330) += hiveap-330.o
+ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
+ obj8259-$(CONFIG_PPC_I8259)   += mpc85xx_8259.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
++src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -358,6 +359,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
+ image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
++image-$(CONFIG_BR200_WP)		+= simpleImage.br200-wp
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -350,6 +350,7 @@ adder875-redboot)
+     platformo="$object/fixed-head.o $object/redboot-8xx.o"
+     binary=y
+     ;;
++simpleboot-br200-wp|\
+ simpleboot-hiveap-330|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\

target/linux/mpc85xx/patches-6.6/111-powerpc-85xx-hpe-msm-support.patch

@@ -0,0 +1,31 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,18 @@ config FIREBOX_T10
+ 	  This board is a VPN Gateway-Router with a
+ 	  Freescale P1010 SoC.
+ 
++config MSM460
++	bool "HPE MSM460"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	select PPC_ZIMAGE_LA3000000
++	help
++	  This option enables support for the HPE MSM460 board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -19,6 +19,7 @@ obj8259-$(CONFIG_PPC_I8259)   += mpc85xx
+ obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o $(obj8259-y)
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460)      += msm460.o
+ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o

target/linux/mpc85xx/patches-6.6/150-arch-powerpc-simpleboot-prevent-overwrite-of-CPU1-sp.patch

@@ -0,0 +1,41 @@
+From 5f856ccc34df25060d36a5a81b7b45b574d86e35 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 3 Dec 2023 20:09:24 +0100
+Subject: [PATCH] arch: powerpc: simpleboot: prevent overwrite of CPU1
+ spin-table
+
+Don't overwrite the spin-table of additional CPU cores with loader-heap.
+
+U-Boot places the spin-table for CPU1 on P1020 SoCs in the top 1MB of
+system-memory. Instead of parsing reserved-memory (which would be
+considerable more work), reduce the available system-memory for the
+loader by 1MB.
+
+This prevents the loader from overwriting the spin-table of
+additional CPU cores on these platforms.
+
+Linux itself needs to be made aware by this using reserved-memory
+definitions.
+
+This patch is required for using CPU1 on the Extreme Networks
+WS-AP3825i.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/simpleboot.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/powerpc/boot/simpleboot.c
++++ b/arch/powerpc/boot/simpleboot.c
+@@ -65,6 +65,11 @@ void platform_init(unsigned long r3, uns
+ 	if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
+ 		memsize64 = 0xffffffff;
+ 
++	/* Reserve upper 1 MB of memory for CPU1 spin-table */
++	if (memsize64 > 0x100000) {
++		memsize64 = memsize64 - 0x100000;
++	}
++
+ 	/* finally, setup the timebase */
+ 	node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+ 					     "cpu", sizeof("cpu"));

target/linux/mpc85xx/patches-6.6/900-powerpc-bootwrapper-disable-uImage-generation.patch

@@ -0,0 +1,42 @@
+From d43ab14605510d9d2bd257a8cd70f24ada4621b0 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 29 Feb 2020 14:27:04 +0100
+Subject: [PATCH] powerpc: bootwrapper: disable uImage generation
+
+Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to
+instruct the mkimage to use the xz compression, which isn't
+supported. This disables the uImage generation, as OpenWrt
+generates individual uImages for each board using it's own
+toolchain.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -296,7 +296,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
+ image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
+ image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
+ image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
+-image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
+ image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
+ 
+ #
+@@ -423,15 +422,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+ $(obj)/vmlinux.strip: vmlinux
+ 	$(STRIP) -s -R .comment $< -o $@
+ 
+-$(obj)/uImage: vmlinux $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot)
+-
+-$(obj)/uImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)
+-
+-$(obj)/uImage.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+-	$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb)
+-
+ $(obj)/cuImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE
+ 	$(call if_changed,wrap,cuboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)
+