Initial commit

target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts

@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Device Tree Source
+ *
+ * Based on: Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+/ {
+	model = "Aerohive BR200-WP";
+	compatible = "aerohive,br200-wp";
+
+	chosen {
+		bootargs = "console=ttyS0,9600";
+		bootargs-override = "console=ttyS0,9600 noinitrd";
+	};
+
+	aliases {
+		led-boot = &led_attention;
+		led-failsafe = &led_attention;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					reg = <0x40000 0x40000>;
+					label = "initramfs";
+				};
+
+				partition@80000 {
+					reg = <0x80000 0x27c0000>;
+					label = "rootfs";
+				};
+
+				partition@2840000 {
+					reg = <0x2840000 0x800000>;
+					label = "kernel";
+				};
+
+				partition@3040000 {
+					reg = <0x3040000 0xec0000>;
+					label = "stock-jffs2";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_0: macaddr@0 {
+							compatible = "mac-base";
+							reg = <0x0 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				firmware@0 {
+					reg = <0x0 0x3040000>;
+					label = "firmware";
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				reg = <0x10>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&phy_port1>;
+						nvmem-cells = <&macaddr_hwinfo_0 2>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&phy_port2>;
+						nvmem-cells = <&macaddr_hwinfo_0 3>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&phy_port3>;
+						nvmem-cells = <&macaddr_hwinfo_0 4>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan4";
+						phy-handle = <&phy_port4>;
+						nvmem-cells = <&macaddr_hwinfo_0 5>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "wan";
+						phy-handle = <&phy_port5>;
+						nvmem-cells = <&macaddr_hwinfo_0 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@6 {
+						reg = <6>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 0>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+				  0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000
+				  0x2000000 0x0 0xc0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			ath9k: wifi@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				nvmem-cells = <&macaddr_hwinfo_0 16>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: led-0 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_status: led-1 {
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "/soc@ffe00000/serial@4500";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			clock-frequency = <0x2756cd00>;
+			bus-frequency = <0x13ab6680>;
+			timebase-frequency = <0x2756cd0>;
+		};
+	};
+
+	memory {
+		reg = <0x00 0x00 0x00 0x10000000>;
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <0x13ab668>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <0x13ab6680>;
+
+		serial@4500 {
+			clock-frequency = <0x13ab6680>;
+		};
+
+		serial@4600 {
+			clock-frequency = <0x13ab6680>;
+		};
+	};
+
+	pcie@ffe09000 {
+		clock-frequency = <0x1fca055>;
+	};
+
+	pcie@ffe0a000 {
+		clock-frequency = <0x1fca055>;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts

@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Watchguard Firebox T10";
+	compatible = "watchguard,firebox-t10";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		bootargs-override = "console=ttyS0,115200";
+	};
+
+	aliases {
+		spi0 = &spi0;
+		led-boot = &led_mode;
+		led-failsafe = &led_failover;
+		led-running = &led_mode;
+		led-upgrade = &led_attention;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: attention_orange {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			label = "orange:attention";
+		};
+
+		status_red {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led_mode: mode_green {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "green:mode";
+		};
+
+		led_failover: failover_green {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "green:failover";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			rtc@30 {
+				compatible = "sii,s35390a";
+				reg = <0x30>;
+			};
+		};
+
+		spi0: spi@7000 {
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					uboot: partition@0 {
+						reg = <0x0 0x90000>;
+						label = "u-boot";
+						read-only;
+					};
+
+					partition@90000 {
+						reg = <0x90000 0x10000>;
+						label = "u-boot-env";
+					};
+
+					partition@a0000 {
+						reg = <0xa0000 0x20000>;
+						label = "cfgxxx";
+						read-only;
+					};
+
+					partition@c0000 {
+						reg = <0xc0000 0x40000>;
+						label = "device_id";
+						read-only;
+					};
+				};
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+			phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			phy3: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy1: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		mdio@26000 {
+			tbi_phy2: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@b1000 {
+			tbi-handle = <&tbi_phy1>;
+			phy-handle = <&phy2>;
+			phy-connection-type = "sgmii";
+		};
+
+		enet2: ethernet@b2000 {
+			tbi-handle = <&tbi_phy2>;
+			phy-handle = <&phy3>;
+			phy-connection-type = "sgmii";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			status = "disabled";
+		};
+
+		can0: can@1c000 {
+			status = "disabled";
+		};
+
+		can1: can@1d000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		status = "disabled";
+	};
+
+	ifc: ifc@ffe1e000 {
+		reg = <0x0 0xffe1e000 0 0x2000>;
+
+		/* NOR, NAND Flashes and CPLD on board */
+		ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+			0x1 0x0 0x0 0xff800000 0x00010000
+			0x3 0x0 0x0 0xffb00000 0x00000020>;
+
+		nand@100000000 {
+			compatible = "fsl,ifc-nand";
+			reg = <0x1 0x0 0x10000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/*
+				 * Original partition layout:
+				 * 0x000000000000-0x000000020000 : "NAND (RW) WG DTB Image"
+				 * 0x000000020000-0x000000520000 : "NAND (RW) WG SYSA Kernel"
+				 * 0x000000520000-0x000007f00000 : "NAND (RW) WG SYSA_CODE"
+				 * 0x000007f00000-0x000008400000 : "NAND (RW) WG SYSB Kernel"
+				 * 0x000008400000-0x000009c00000 : "NAND (RW) WG SYSB_CODE"
+				 * 0x000009c00000-0x00000a100000 : "NAND (RW) WG SYSA2 Kernel"
+				 * 0x00000a100000-0x000011ae0000 : "NAND (RW) WG SYSA_CODE2"
+				 * 0x000011ae0000-0x000020000000 : "NAND (RW) WG SYSA_DATA"
+				 */
+
+				partition@0 {
+					reg = <0x0 0x20000>;
+					label = "wg-dtb";
+					read-only;
+				};
+
+				partition@20000 {
+					reg = <0x20000 0x500000>;
+					label = "kernel";
+				};
+
+				partition@520000 {
+					reg = <0x520000 0x79e0000>;
+					label = "wg-sysa-rootfs";
+					read-only;
+				};
+
+				partition@7f00000 {
+					reg = <0x7f00000 0x500000>;
+					label = "wg-sysb-kernel";
+					read-only;
+				};
+
+				partition@8400000 {
+					reg = <0x8400000 0x1800000>;
+					label = "wg-sysb-rootfs";
+					read-only;
+				};
+
+				partition@9c00000 {
+					reg = <0x9c00000 0x500000>;
+					label = "wg-sysa2-kernel";
+					read-only;
+				};
+
+				partition@a100000 {
+					reg = <0xa100000 0x79e0000>;
+					label = "wg-sysa2-rootfs";
+					read-only;
+				};
+
+				partition@11ae0000 {
+					reg = <0x11ae0000 0xe520000>;
+					label = "ubi";
+				};
+			};
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"

target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts

@@ -0,0 +1,424 @@
+/*
+ * Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Aerohive HiveAP-330";
+	compatible = "aerohive,hiveap-330";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_fault_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_fault_red;
+		label-mac-device = &enet0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		/*
+		 * not yet implemented.
+		 * stdout-path = &serial0 ":9600n8";
+		 * <https://www.spinics.net/lists/devicetree-compiler/msg02487.html>
+		 *
+		 * this should work... but it doesn't because CONFIG_CMDLINE in our
+		 * OpenWrt's target config sets "console=ttyS0,115200"
+		 * stdout-path = "/soc@ffe00000/serial@4500:9600n8";
+		 */
+
+		bootargs = "console=ttyS0,9600n8";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			status = "okay";
+			clock-frequency = <533333328>; /* 533.33 MHz */
+			bus-frequency = <266666664>;  /* 266.66 MHz */
+			timebase-frequency = <33333333>; /* 33.33 MHz */
+		};
+
+		PowerPC,P1020@1 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			cpu-release-addr = <0x00 0xffff240>;
+			enable-method = "spin-table";
+			status = "disabled";
+			clock-frequency = <533333328>;
+			bus-frequency = <266666664>;
+			timebase-frequency = <33333333>;
+		};
+	};
+
+	memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		reg = <0x00 0x00 0x00 0x10000000>;
+		device_type = "memory";
+	};
+
+	/*
+	 * Usually, u-boot provided /memreserve/ properties by adding them during boot.
+	 * these have been converted to reserved-memory entries.
+	 */
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * /memreserve/   0x0000000000ffa000 0x0000000000004000;
+		 * The kernel complains when booting:
+		 *
+		 * | OF: fdt: Reserved memory: failed to reserve memory for node
+		 *		'firmware@ffa000': base 0x00ffa000, size 0 MiB
+		 *
+		 * But this likely uboot's bootargs + modified DTB. And if so, we don't care.
+		 * This is because we rely on our own dtb that's in the simpleImage.
+		 *
+		 * Note: This is backed up by u-boot. just before the kernel executes
+		 *	 it prints this final line:
+		 *	 |  Loading Device Tree to 00ff9000, end 00fff1c4 ... OK
+		 *
+		 * firmware@ffa000 {
+		 *	reg = <0x0 0xffa000 0x0 0x4000>;
+		 *	no-map;
+		 * };
+		 */
+
+		// /memreserve/   0x000000000fe2f000 0x0000000000000021;
+		firmware@fe2f000 {
+			reg = <0x0 0xfe2f000 0x0 0x21>;
+			no-map;
+		};
+
+		/*
+		 * /memreserve/   0x000000000ffff000 0x0000000000001000;
+		 * that's the spin-table - see second CPU core binding.
+		 */
+		firmware@ffff000 {
+			reg = <0x0 0xffff000 0x0 0x1000>;
+			no-map;
+		};
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		bus-frequency = <16666666>; /* 16.66 MHz */
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				firmware@0 {
+					reg = <0x0 0x3f00000>;
+					label = "firmware";
+					/*
+					 * This unknown/invalid compatible prevents
+					 * openwrt's mtdsplit_fit to go off a tangent if it
+					 * finds a magic value inside the uncompressed kernel
+					 * at a blocksized aligned place.
+					 */
+					compatible = "areohive,hiveap-330-image";
+				};
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					compatible = "openwrt,uimage", "denx,uimage";
+					reg = <0x40000 0x3ec0000>;
+					label = "kernel";
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_0: macaddr@0 {
+							compatible = "mac-base";
+							reg = <0x0 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+		bus-frequency = <266666664>;
+
+		spi0: spi@7000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			temperature-sensor@1 {
+				compatible = "ti,tmp125";
+				reg = <1>;
+				spi-max-frequency = <5000000>;
+			};
+		};
+
+		i2c@3100 {
+			tpm@29 {
+				compatible = "atmel,at97sc3204t";
+				reg = <0x29>;
+			};
+
+			lp5521@32 {
+				compatible = "national,lp5521";
+				reg = <0x32>;
+				clock-mode = /bits/ 8 <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+#if 1
+				led_fault_red: led@0 {
+					reg = <0>;
+					chan-name = "fault:red";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_RED>;
+					function = LED_FUNCTION_FAULT;
+				};
+				led_power_green: led@1 {
+					reg = <1>;
+					chan-name = "power:green";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_POWER;
+				};
+				led@2{
+					reg = <2>;
+					chan-name = "blue";
+					led-cur = /bits/ 8 <0x2f>;
+					max-cur = /bits/ 8 <0x5f>;
+					color = <LED_COLOR_ID_BLUE>;
+				};
+#else
+				/*
+				 * openwrt isn't ready to handle multi-intensity leds yet
+				 * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
+				 * # echo 255 > /sys/class/leds/tricolor/brightness
+				 */
+
+				rgbled-0 {
+					function = LED_FUNCTION_POWER;
+					color = <LED_COLOR_ID_RGB>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_RED>;
+					};
+					led@1 {
+						reg = <1>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_GREEN>;
+					};
+					led@2{
+						reg = <2>;
+						chan-name = "tricolor";
+						led-cur = /bits/ 8 <0x2f>;
+						max-cur = /bits/ 8 <0x5f>;
+						color = <LED_COLOR_ID_BLUE>;
+					};
+				};
+#endif
+			};
+
+			eeprom@51 {
+				/*
+				 * 1Kbit I2C/SMBus EEPROM with SHA-1 Engine
+				 * Aerohive calls it "dallas".
+				 */
+				compatible = "adi,ds28cn01";
+				reg = <0x51>;
+				read-only;
+			};
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				/* interrupts = <3 1 0 0>; */
+				reg = <0x1>;
+			};
+
+			phy1: ethernet-phy@1 {
+				/* interrupts = <2 1 0 0>; */
+				reg = <0x2>;
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			rx-stash-idx = <0x00>;
+			rx-stash-len = <0x60>;
+			bd-stash;
+			status = "okay";
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 0>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			rx-stash-idx = <0x00>;
+			rx-stash-len = <0x60>;
+			bd-stash;
+			status = "okay";
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 1>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>,
+			 <0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000>,
+				 <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
+			 <0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000>,
+				 <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+&serial0 {
+	clock-frequency = <266666664>;
+};
+
+&serial1 {
+	clock-frequency = <266666664>;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/msm460.dts

@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Hewlett-Packard MSM460";
+	compatible = "hpe,msm460";
+
+	aliases {
+		led-boot = &system_green;
+		led-failsafe = &system_green;
+		led-running = &system_green;
+		led-upgrade = &system_green;
+		label-mac-device = &enet0;
+	};
+
+	chosen {
+		/* Needed for initramfs */
+		bootargs-override = "console=ttyS0,115200 ubi.mtd=5,2048";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+		nand@1,0 {
+			compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+			reg = <0x1 0x0 0x40000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xc0000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@c0000 {
+					reg = <0xc0000 0x40000>;
+					label = "colubris-bid";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_1f822: macaddr@1f822 {
+							/* ETH */
+							compatible = "mac-base";
+							reg = <0x1f822 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_hwinfo_1f9bd: macaddr@1f9bd {
+							/* WLAN */
+							compatible = "mac-base";
+							reg = <0x1f9bd 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				/* uenv{0,1} and ubi occupy kernel and slash partitions */
+
+				partition@100000 {
+					reg = <0x100000 0x80000>;
+					label = "uboot-env0";
+				};
+
+				partition@180000 {
+					reg = <0x180000 0x80000>;
+					label = "uboot-env1";
+				};
+
+				partition@200000 {
+					reg = <0x200000 0x300000>;
+					label = "reserved";
+				};
+
+				partition@500000 {
+					reg = <0x500000 0x5f00000>;
+					label = "ubi";
+				};
+
+				partition@6500000 {
+					reg = <0x6500000 0x400000>;
+					label = "pool";
+					read-only;
+				};
+
+				partition@6900000 {
+					reg = <0x6900000 0x15e0000>;
+					label = "flash";
+					read-only;
+				};
+
+				partition@7ee0000 {
+					reg = <0x7ee0000 0x20000>;
+					label = "pf";
+					read-only;
+				};
+
+				/* BBT is at the end of the flash - 100000@7f00000 */
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x0>;
+				reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&phy0>;
+			nvmem-cells = <&macaddr_hwinfo_1f822 0>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: power {
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			default-state = "on";
+		};
+
+		lan {
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+		};
+
+		radio1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <1>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		radio2 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <2>;
+			linux,default-trigger = "phy1tpt";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset-btn";
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+/include/ "fsl/p1020si-post.dtsi"

target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts

@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "OCEDO Panda";
+	compatible = "ocedo,panda";
+
+	aliases {
+		led-boot = &system_blue;
+		led-failsafe = &system_blue;
+		led-running = &system_blue;
+		led-upgrade = &system_blue;
+	};
+
+	chosen {
+		/* Needed for initramfs */
+		bootargs-override = "console=ttyS0,115200 ubi.mtd=3,2048";
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+		nand@100000000 {
+			compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+			reg = <0x1 0x0 0x40000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xa0000>;
+					label = "uboot";
+					read-only;
+				};
+
+				partition@a0000 {
+					reg = <0xa0000 0x20000>;
+					label = "uboot-env0";
+				};
+
+				partition@c0000 {
+					reg = <0xc0000 0x40000>;
+					label = "uboot-env1";
+				};
+
+				partition@100000 {
+					reg = <0x100000 0xff00000>;
+					label = "ubi";
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			rtc@68 {
+				compatible = "dallas,ds1339";
+				reg = <0x68>;
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@8 {
+				reg = <0x8>;
+			};
+
+			phy1: ethernet-phy@9 {
+				reg = <0x9>;
+			};
+
+			switch0: ethernet-phy@0 {
+				reg = <0x0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						label = "lan1";
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "lan2";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan3";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan4";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan5";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "lan6";
+					};
+
+					port@6 {
+						reg = <6>;
+						label = "lan7";
+					};
+
+					port@7 {
+						reg = <7>;
+						label = "lan8";
+					};
+
+					port@8 {
+						reg = <8>;
+						label = "cpu";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy0: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			tbi_phy1: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&switch0>;
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-connection-type = "sgmii";
+			phy-handle = <&phy0>;
+
+			tbi-handle = <&tbi_phy0>;
+		};
+
+		enet2: ethernet@b2000 {
+			phy-connection-type = "sgmii";
+			phy-handle = <&phy1>;
+
+			tbi-handle = <&tbi_phy1>;
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power {
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+			label = "panda:green:power";
+			default-state = "on";
+		};
+
+		wlan0 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "panda:yellow:wlan0";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wlan1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+			label = "panda:red:wlan1";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		tbd_orange {
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			label = "panda:orange:tbd";
+		};
+
+		system_blue: system {
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "panda:blue:system";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+/include/ "fsl/p1020si-post.dtsi"
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Sophos RED 15w Rev.1";
+	compatible = "sophos,red-15w-rev1";
+
+	aliases {
+		led-boot = &system_green;
+		led-failsafe = &system_red;
+		led-running = &system_green;
+		led-upgrade = &system_red;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: system_green {
+			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+			label = "red-15w-rev1:green:system";
+		};
+
+		system_red: system_red {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "red-15w-rev1:red:system";
+		};
+
+		router {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:router";
+		};
+
+		internet {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:internet";
+		};
+
+		tunnel {
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			label = "red-15w-rev1:green:tunnel";
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			eeprom@50 {
+				compatible = "st,24c256";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@3100 {
+			eeprom@52 {
+				compatible = "atmel,24c01";
+				reg = < 0x52 >;
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy0>;
+			phy-connection-type = "sgmii";
+
+			tbi-handle = <&tbi_phy>;
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+		reg = <0x0 0xffe1e000 0 0x2000>;
+
+		/* NOR, NAND Flashes and CPLD on board */
+		ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+			0x1 0x0 0x0 0xff800000 0x00010000
+			0x3 0x0 0x0 0xffb00000 0x00000020>;
+
+		nand@100000000 {
+			compatible = "fsl,ifc-nand";
+			reg = <0x1 0x0 0x10000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/*
+				 * Original partition layout:
+				 * 0x000000000000-0x000000100000 : "NAND U-Boot Image"
+				 * 0x000000100000-0x000000200000 : "NAND U-Boot Environment"
+				 * 0x000000200000-0x000000300000 : "Provisioning"
+				 *  - OS-Image 1
+				 * 0x000000300000-0x000000400000 : "fdt1"
+				 * 0x000000400000-0x000000c00000 : "uimage1"
+				 * 0x000000c00000-0x000001c00000 : "rootfs1"
+				 *  - OS-Image 2
+				 * 0x000001c00000-0x000001d00000 : "fdt2"
+				 * 0x000001d00000-0x000002500000 : "uimage2"
+				 * 0x000002500000-0x000003500000 : "rootfs2"
+				 *  - Empty
+				 * 0x000003500000-0x000008000000 : "data"
+				 */
+
+				partition@0 {
+					reg = <0x0 0x100000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@100000 {
+					reg = <0x100000 0x100000>;
+					label = "u-boot-env";
+				};
+
+				partition@200000 {
+					reg = <0x200000 0x100000>;
+					label = "provisioning";
+					read-only;
+				};
+
+				oem-partition@300000 {
+					reg = <0x300000 0x1900000>;
+					label = "sophos-os1";
+
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						reg = <0x0 0x800000>;
+						label = "kernel";
+					};
+
+					partition@800000 {
+						reg = <0x800000 0x7500000>;
+						label = "ubi";
+					};
+				};
+
+				oem-partition@1c00000 {
+					reg = <0x1c00000 0x1900000>;
+					label = "sophos-os2";
+				};
+
+				oem-partition@3500000 {
+					reg = <0x3500000 0x4b00000>;
+					label = "sophos-data";
+				};
+			};
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts

@@ -0,0 +1,379 @@
+/*
+ * TP-Link TL-WDR4900 v1 Device Tree Source
+ *
+ * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "TP-Link TL-WDR4900 v1";
+	compatible = "tplink,tl-wdr4900-v1";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+/*
+		stdout-path = "/soc@ffe00000/serial@4500";
+*/
+	};
+
+	aliases {
+		spi0 = &spi0;
+		led-boot = &system_green;
+		led-failsafe = &system_green;
+		led-running = &system_green;
+		led-upgrade = &system_green;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		spi0: spi@7000 {
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					uboot: partition@0 {
+						reg = <0x0 0x0050000>;
+						label = "u-boot";
+						read-only;
+
+						nvmem-layout {
+							compatible = "fixed-layout";
+							#address-cells = <1>;
+							#size-cells = <1>;
+
+							macaddr_uboot_4fc00: macaddr@4fc00 {
+								reg = <0x4fc00 0x6>;
+							};
+						};
+					};
+
+					partition@50000 {
+						reg = <0x00050000 0x00010000>;
+						label = "dtb";
+						read-only;
+					};
+
+					partition@60000 {
+						compatible = "tplink,firmware";
+						reg = <0x00060000 0x00f80000>;
+						label = "firmware";
+					};
+
+					partition@fe0000 {
+						reg = <0x00fe0000 0x00010000>;
+						label = "config";
+						read-only;
+					};
+
+					partition@ff0000 {
+						reg = <0x00ff0000 0x00010000>;
+						label = "caldata";
+						read-only;
+					};
+				};
+			};
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "utmi";
+			dr_mode = "host";
+		};
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				reg = <0x10>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						label = "wan";
+						phy-handle = <&phy_port1>;
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan1";
+						phy-handle = <&phy_port2>;
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan2";
+						phy-handle = <&phy_port3>;
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan3";
+						phy-handle = <&phy_port4>;
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "lan4";
+						phy-handle = <&phy_port5>;
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_uboot_4fc00>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			status = "disabled";
+		};
+
+		can0: can@1c000 {
+			status = "disabled";
+		};
+
+		can1: can@1d000 {
+			status = "disabled";
+		};
+
+		ptp_clock@b0e00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0xb0e00 0xb0>;
+			interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+			fsl,cksel       = <1>;
+			fsl,tclk-period	= <5>;
+			fsl,tmr-prsc	= <2>;
+			fsl,tmr-add	= <0xcccccccd>;
+			fsl,tmr-fiper1	= <0x3b9ac9fb>; /* 1PPS */
+			fsl,tmr-fiper2	= <0x00018696>;
+			fsl,max-adj	= <249999999>;
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0 0xffe09000 0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+		status = "disabled";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: system {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			label = "tp-link:blue:system";
+		};
+
+		usb1 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			label = "tp-link:green:usb1";
+		};
+
+		usb2 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+			label = "tp-link:green:usb2";
+		};
+
+		usbpower {
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+			label = "tp-link:usb:power";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		rfkill {
+			label = "RFKILL switch";
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1010@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <49999999>;
+			clock-frequency = <799999992>;
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x8000000>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+};
+
+/*
+ * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
+ * related to the P1010.
+ *
+ * NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
+ * datasheet states that the P1014 does not include the accelerated crypto
+ * module (CAAM/SEC4) which is present in the P1010.
+ *
+ * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
+ * SEC4 module, but states that SoCs with System Version Register values
+ * 0x80F10110 or 0x80F10120 do not have the security feature.
+ *
+ * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
+ * as: core rev 1.0, "P1014 (without security)".
+ *
+ * The SVR value is reported by uboot on the serial console.
+ */
+
+/ {
+	soc: soc@ffe00000 {
+		/delete-node/ crypto@30000; /* Pulled in by p1010si-post */
+	};
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts

@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Enterasys WS-AP3710i";
+	compatible = "enterasys,ws-ap3710i";
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:radio1";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wifi2 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:radio2";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:green:power";
+		};
+
+		led_power_red: power_red {
+			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+			label = "ws-ap3710i:red:power";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xee000000 0x2000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x2000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					compatible = "denx,uimage";
+					reg = <0x0 0x1d80000>;
+					label = "firmware";
+				};
+
+				partition@1d80000 {
+					reg = <0x1d80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@1e00000 {
+					reg = <0x1e00000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+
+				partition@1f00000 {
+					reg = <0x1f00000 0x20000>;
+					label = "cfg2";
+					read-only;
+				};
+
+				partition@1f20000 {
+					reg = <0x1f20000 0x20000>;
+					label = "cfg1";
+					read-only;
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy4: ethernet-phy@4 {
+				reg = <0x4>;
+				reset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&phy4>;
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+			      0x00 0x100000 0x42000000 0x00 0x00 0x00
+			      0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+			      0xffe00000 0x00 0x100000 0x42000000
+			      0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+};
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1020@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff280>;
+			status = "okay";
+			enable-method = "spin-table";
+		};
+
+		PowerPC,P1020@1 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff2a0>;
+			status = "disabled";
+			enable-method = "spin-table";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpu1-bootpage@ff00000 {
+			/* Reserve upper 1 MB for second-core-bootpage */
+			reg = <0x0 0xff00000 0x0 0x100000>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <24999999>;
+	};
+};
+
+&enet0 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+&enet2 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts

@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1010si-pre.dtsi"
+
+/ {
+	model = "Enterasys WS-AP3715i";
+	compatible = "enterasys,ws-ap3715i";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+	
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "green:radio1";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		wifi2 {
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "green:radio2";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_power_red: power_red {
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		lan1_red {
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
+			label = "red:lan1";
+		};
+
+		lan1_green {
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
+			label = "green:lan1";
+		};
+
+		lan2_red {
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
+			label = "red:lan2";
+		};
+
+		lan2_green {
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
+			label = "green:lan2";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x1>;
+			};
+
+			phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+		};
+
+		mdio@25000 {
+			tbi_phy: tbi-phy@11 {
+				reg = <0x11>;
+			};
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+
+			label = "lan1";
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy2>;
+			phy-connection-type = "sgmii";
+
+			tbi-handle = <&tbi_phy>;
+
+			label = "lan2";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		sdhc@2e000 {
+			status = "disabled";
+		};
+	};
+
+	ifc: ifc@ffe1e000 {
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0 0xffe09000 0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			wifi@0,0 {
+				compatible = "pci168c,0033";
+				reg = <0x0 0 0 0 0>;
+				ieee80211-freq-limit = <2400000 2500000>;
+			};
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+			
+			wifi@0,0 {
+				compatible = "pci168c,0033";
+				reg = <0x0 0 0 0 0>;
+				ieee80211-freq-limit = <5000000 6000000>;
+			};
+		};
+	};
+};
+
+&soc {
+	led_spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <100000>;
+		};
+	};
+
+	spi0: spi@7000 {
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <25000000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xa0000>;
+					label = "boot-bak";
+					read-only;
+				};
+
+				partition@a0000 {
+					reg = <0xa0000 0xa0000>;
+					label = "boot-pri";
+					read-only;
+				};
+
+				partition@120000 {
+					reg = <0x120000 0x10000>;
+					label = "cfg1";
+					read-only;
+				};
+
+				partition@130000 {
+					reg = <0x130000 0x10000>;
+					label = "cfg2";
+					read-only;
+				};
+
+				partition@140000 {
+					compatible = "denx,uimage";
+					reg = <0x140000 0x1d80000>;
+					label = "firmware";
+				};
+
+				partition@1ec0000 {
+					reg = <0x1ec0000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+			};
+		};
+	};
+};
+
+/include/ "fsl/p1010si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1010@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+			status = "disabled";
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};
+

target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts

@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Extreme Networks WS-AP3825i";
+	compatible = "extreme-networks,ws-ap3825i";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi1 {
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "green:radio1";
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wifi2 {
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "green:radio2";
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_power_green: power_green {
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_power_red: power_red {
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		lan1_red {
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
+			label = "red:lan1";
+		};
+
+		lan1_green {
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
+			label = "green:lan1";
+		};
+
+		lan2_red {
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
+			label = "red:lan2";
+		};
+
+		lan2_green {
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
+			label = "green:lan2";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					compatible = "denx,fit";
+					reg = <0x0 0x3d60000>;
+					label = "firmware";
+				};
+
+				partition@3d60000 {
+					reg = <0x3d60000 0x20000>;
+					label = "calib";
+					read-only;
+				};
+
+				partition@3d80000{
+					reg = <0x3d80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@3e00000{
+					reg = <0x3e00000 0x100000>;
+					label = "nvram";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "cfg2";
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "cfg1";
+				};
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				/* interrupts = <3 1 0 0>; */
+				reg = <0x5>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+
+			phy2: ethernet-phy@2 {
+				/* interrupts = <1 1 0 0>; */
+				reg = <0x6>;
+				reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "okay";
+			phy-handle = <&phy2>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+			      0x00 0x100000 0x42000000 0x00 0x00 0x00
+			      0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+			      0xffe00000 0x00 0x100000 0x42000000
+			      0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+&soc {
+	led_spi {
+		/*
+		 * This is currently non-functioning because the spi-gpio
+		 * driver refuses to register when presented with this node.
+		 */
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <1>;
+			spi-max-frequency = <100000>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	cpus {
+		PowerPC,P1020@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff280>;
+			status = "okay";
+			enable-method = "spin-table";
+		};
+
+		PowerPC,P1020@1 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff2a0>;
+			status = "disabled";
+			enable-method = "spin-table";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpu1-bootpage@ff00000 {
+			/* Reserve upper 1 MB for second-core-bootpage */
+			reg = <0x0 0xff00000 0x0 0x100000>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <24999999>;
+	};
+};
+
+&enet0 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+&enet2 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+/*
+ * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
+ * aliases to determine PCI domain numbers, drop aliases so as not to
+ * change the sysfs path of our wireless netdevs.
+ */
+
+/ {
+	aliases {
+		/delete-property/ pci0;
+		/delete-property/ pci1;
+	};
+};