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44 lines
1.3 KiB
Diff
44 lines
1.3 KiB
Diff
From 35da34adec7b5b06ad81455a21c67a9c1152e2c9 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 7 Aug 2021 12:09:35 -0500
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Subject: [PATCH 77/90] riscv: Sort target configs alphabetically
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/riscv/Kconfig | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -14,6 +14,9 @@ config TARGET_AX25_AE350
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config TARGET_MICROCHIP_ICICLE
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bool "Support Microchip PolarFire-SoC Icicle Board"
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+config TARGET_OPENPITON_RISCV64
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+ bool "Support RISC-V cores on OpenPiton SoC"
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+
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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@@ -28,9 +31,6 @@ config TARGET_SIPEED_MAIX
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bool "Support Sipeed Maix Board"
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select SYS_CACHE_SHIFT_6
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-config TARGET_OPENPITON_RISCV64
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- bool "Support RISC-V cores on OpenPiton SoC"
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-
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endchoice
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config SYS_ICACHE_OFF
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@@ -61,9 +61,9 @@ config SPL_SYS_DCACHE_OFF
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source "board/AndesTech/ax25-ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/microchip/mpfs_icicle/Kconfig"
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+source "board/openpiton/riscv64/Kconfig"
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source "board/sifive/unleashed/Kconfig"
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source "board/sifive/unmatched/Kconfig"
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-source "board/openpiton/riscv64/Kconfig"
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source "board/sipeed/maix/Kconfig"
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# platform-specific options below
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