27c9d80f51
Some checks failed
Build Kernel / Build all affected Kernels (push) Has been cancelled
Build all core packages / Build all core packages for selected target (push) Has been cancelled
Build and Push prebuilt tools container / Build and Push all prebuilt containers (push) Has been cancelled
Build Toolchains / Build Toolchains for each target (push) Has been cancelled
Build host tools / Build host tools for linux and macos based systems (push) Has been cancelled
Coverity scan build / Coverity x86/64 build (push) Has been cancelled
51 lines
1.9 KiB
Diff
51 lines
1.9 KiB
Diff
From 66372055ffda939ce52ddc64270079dd4f04d764 Mon Sep 17 00:00:00 2001
|
|
From: Dom Cobley <popcornmix@gmail.com>
|
|
Date: Fri, 21 Apr 2023 22:00:16 +0100
|
|
Subject: [PATCH 0468/1085] drm/vc4: hdmi: Increase MAI fifo dreq threshold
|
|
|
|
Now we wait for write responses and have a burst
|
|
size of 4, we can set the fifo threshold much higher.
|
|
|
|
Set it to 28 (of the 32 entry size) to keep fifo
|
|
fuller and reduce chance of underflow.
|
|
|
|
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 18 +++++++++++++-----
|
|
1 file changed, 13 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -2521,6 +2521,7 @@ static int vc4_hdmi_audio_prepare(struct
|
|
{
|
|
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
|
|
struct drm_device *drm = vc4_hdmi->connector.dev;
|
|
+ struct vc4_dev *vc4 = to_vc4_dev(drm);
|
|
struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
|
|
unsigned int sample_rate = params->sample_rate;
|
|
unsigned int channels = params->channels;
|
|
@@ -2579,11 +2580,18 @@ static int vc4_hdmi_audio_prepare(struct
|
|
VC4_HDMI_AUDIO_PACKET_CEA_MASK);
|
|
|
|
/* Set the MAI threshold */
|
|
- HDMI_WRITE(HDMI_MAI_THR,
|
|
- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
|
|
- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
|
|
- VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
|
|
- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
|
|
+ if (vc4->is_vc5)
|
|
+ HDMI_WRITE(HDMI_MAI_THR,
|
|
+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
|
|
+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
|
|
+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
|
|
+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
|
|
+ else
|
|
+ HDMI_WRITE(HDMI_MAI_THR,
|
|
+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
|
|
+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
|
|
+ VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
|
|
+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
|
|
|
|
HDMI_WRITE(HDMI_MAI_CONFIG,
|
|
VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
|