27c9d80f51
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67 lines
1.8 KiB
Diff
67 lines
1.8 KiB
Diff
From cccda48fda97b1c48afd6e4b6853d3d8a532c180 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Fri, 28 Oct 2022 14:12:18 +0100
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Subject: [PATCH 0527/1085] dt-bindings: clock: Add bindings for Raspberry Pi
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RP1
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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include/dt-bindings/clock/rp1.h | 51 +++++++++++++++++++++++++++++++++
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1 file changed, 51 insertions(+)
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create mode 100644 include/dt-bindings/clock/rp1.h
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--- /dev/null
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+++ b/include/dt-bindings/clock/rp1.h
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@@ -0,0 +1,51 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2021 Raspberry Pi Ltd.
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+ */
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+
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+#define RP1_PLL_SYS_CORE 0
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+#define RP1_PLL_AUDIO_CORE 1
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+#define RP1_PLL_VIDEO_CORE 2
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+
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+#define RP1_PLL_SYS 3
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+#define RP1_PLL_AUDIO 4
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+#define RP1_PLL_VIDEO 5
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+
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+#define RP1_PLL_SYS_PRI_PH 6
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+#define RP1_PLL_SYS_SEC_PH 7
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+
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+#define RP1_PLL_SYS_SEC 8
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+#define RP1_PLL_AUDIO_SEC 9
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+#define RP1_PLL_VIDEO_SEC 10
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+
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+#define RP1_CLK_SYS 11
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+#define RP1_CLK_SLOW_SYS 12
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+#define RP1_CLK_DMA 13
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+#define RP1_CLK_UART 14
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+#define RP1_CLK_ETH 15
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+#define RP1_CLK_PWM0 16
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+#define RP1_CLK_PWM1 17
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+#define RP1_CLK_AUDIO_IN 18
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+#define RP1_CLK_AUDIO_OUT 19
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+#define RP1_CLK_I2S 20
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+#define RP1_CLK_MIPI0_CFG 21
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+#define RP1_CLK_MIPI1_CFG 22
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+#define RP1_CLK_PCIE_AUX 23
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+#define RP1_CLK_USBH0_MICROFRAME 24
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+#define RP1_CLK_USBH1_MICROFRAME 25
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+#define RP1_CLK_USBH0_SUSPEND 26
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+#define RP1_CLK_USBH1_SUSPEND 27
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+#define RP1_CLK_ETH_TSU 28
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+#define RP1_CLK_ADC 29
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+#define RP1_CLK_SDIO_TIMER 30
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+#define RP1_CLK_SDIO_ALT_SRC 31
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+#define RP1_CLK_GP0 32
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+#define RP1_CLK_GP1 33
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+#define RP1_CLK_GP2 34
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+#define RP1_CLK_GP3 35
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+#define RP1_CLK_GP4 36
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+#define RP1_CLK_GP5 37
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+#define RP1_CLK_VEC 38
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+#define RP1_CLK_DPI 39
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+#define RP1_CLK_MIPI0_DPI 40
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+#define RP1_CLK_MIPI1_DPI 41
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