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50 lines
1.8 KiB
Diff
50 lines
1.8 KiB
Diff
From db92246eeab5c5e3d42baac8da32c7d2e38238ef Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 24 Jan 2024 13:55:45 +0000
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Subject: [PATCH 0889/1085] PCI: brcmstb: Enable CRS software visibility after
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linkup
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It appears that bits in the Root Control Register are reset with
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perst_n, which means the PCI layer's call to enable CRS prior to
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adding/scanning the bus has no effect. Open-code the enable in
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brcm_pcie_start_link as a workaround.
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Without CRS visibility, configuration reads issued by the CPU don't
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retire if the endpoint returns a CRS response - the RC will poll until a
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(large) timeout is reached. This means the core can stall for a long
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time during boot.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -1385,7 +1385,7 @@ static int brcm_pcie_start_link(struct b
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{
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struct device *dev = pcie->dev;
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void __iomem *base = pcie->base;
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- u16 nlw, cls, lnksta;
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+ u16 nlw, cls, lnksta, tmp16;
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bool ssc_good = false;
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int ret, i;
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u32 tmp;
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@@ -1449,6 +1449,16 @@ static int brcm_pcie_start_link(struct b
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pci_speed_string(pcie_link_speed[cls]), nlw,
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ssc_good ? "(SSC)" : "(!SSC)");
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+ /*
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+ * RootCtl bits are reset by perst_n, which undoes pci_enable_crs()
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+ * called prior to pci_add_new_bus() during probe. Re-enable here.
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+ */
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+ tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCAP);
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+ if (tmp16 & PCI_EXP_RTCAP_CRSVIS) {
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+ tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
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+ u16p_replace_bits(&tmp16, 1, PCI_EXP_RTCTL_CRSSVE);
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+ writew(tmp16, base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
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+ }
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return 0;
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}
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