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40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
From d5377dd13e91af81f8f31e93532c62216842038c Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 26 Apr 2024 19:20:41 +0100
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Subject: [PATCH 1070/1085] drm/panel-simple: Increase pixel clock on Pi 7inch
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panel
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The Toshiba bridge is very fussy and doesn't like the CM3
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output when being told to produce a 27.777MHz pixel clock, which
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is an almost perfect match to the DSI link integer divider.
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Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz
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and makes the bridge happy with the same video timing as works
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on Pi4.
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(Pi4 will be using a link frequency of 375MHz due to a 3GHz
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parent PLL).
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/panel/panel-simple.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/drivers/gpu/drm/panel/panel-simple.c
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+++ b/drivers/gpu/drm/panel/panel-simple.c
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@@ -3417,11 +3417,11 @@ static const struct panel_desc rocktech_
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};
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static const struct drm_display_mode raspberrypi_7inch_mode = {
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- .clock = 27777,
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+ .clock = 30000,
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.hdisplay = 800,
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- .hsync_start = 800 + 59,
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- .hsync_end = 800 + 59 + 2,
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- .htotal = 800 + 59 + 2 + 45,
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+ .hsync_start = 800 + 131,
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+ .hsync_end = 800 + 131 + 2,
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+ .htotal = 800 + 131 + 2 + 45,
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.vdisplay = 480,
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.vsync_start = 480 + 7,
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.vsync_end = 480 + 7 + 2,
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