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66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:13 +0200
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Subject: net: dsa: qca8k: add explicit SGMII PLL enable
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Support enabling PLL on the SGMII CPU port. Some device require this
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special configuration or no traffic is transmitted and the switch
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doesn't work at all. A dedicated binding is added to the CPU node
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port to apply the correct reg on mac config.
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Fail to correctly configure sgmii with qca8327 switch and warn if pll is
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used on qca8337 with a revision greater than 1.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 19 +++++++++++++++++--
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drivers/net/dsa/qca8k.h | 1 +
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2 files changed, 18 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri
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if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
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priv->sgmii_rx_clk_falling_edge = true;
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+ if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
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+ priv->sgmii_enable_pll = true;
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+
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+ if (priv->switch_id == QCA8K_ID_QCA8327) {
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+ dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
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+ priv->sgmii_enable_pll = false;
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+ }
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+
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+ if (priv->switch_revision < 2)
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+ dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
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+ }
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+
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break;
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default:
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continue;
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@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit
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if (ret)
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return;
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- val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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- QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
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+ val |= QCA8K_SGMII_EN_SD;
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+
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+ if (priv->sgmii_enable_pll)
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+ val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
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+ QCA8K_SGMII_EN_TX;
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if (dsa_is_cpu_port(ds, port)) {
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/* CPU port, we're talking to the CPU MAC, be a PHY */
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -266,6 +266,7 @@ struct qca8k_priv {
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u8 switch_revision;
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bool sgmii_rx_clk_falling_edge;
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bool sgmii_tx_clk_falling_edge;
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+ bool sgmii_enable_pll;
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u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
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bool legacy_phy_port_mapping;
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