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31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From 3b83b32e16fa431c76a5da1ac59c268ca2fecbb5 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Sat, 11 Feb 2023 05:18:11 +0200
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Subject: [PATCH 1017/1024] dt-bindings: riscv: sifive-ccache: Add
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'uncached-offset' property
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Add the 'uncached-offset' property to be used for specifying the
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uncached memory offset required for handling non-coherent DMA
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transactions.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20230211031821.976408-3-cristian.ciocaltea@collabora.com
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---
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Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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@@ -70,6 +70,11 @@ properties:
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next-level-cache: true
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+ uncached-offset:
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+ $ref: /schemas/types.yaml#/definitions/uint64
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+ description: |
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+ Uncached memory offset for handling non-coherent DMA transactions.
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+
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memory-region:
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maxItems: 1
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description: |
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