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36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
From ad7864af76d909c4e357441c2caabd0b5f42e3d4 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 26 Apr 2024 17:05:39 +0100
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Subject: [PATCH 1067/1085] clk-bcm2835: Use PLLD for DSI0 HS clock
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DSI0 can take the clock from either PLLA or PLLD. PLLA is
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the default muxing, but PLLD is considered the more stable.
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Switch to using PLLD.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/clk/bcm/clk-bcm2835.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -107,6 +107,7 @@
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#define CM_UARTDIV 0x0f4
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#define CM_VECCTL 0x0f8
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#define CM_VECDIV 0x0fc
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+#define CM_DSI0HSCK 0x120
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#define CM_PULSECTL 0x190
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#define CM_PULSEDIV 0x194
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#define CM_SDCCTL 0x1a8
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@@ -2352,6 +2353,9 @@ static int bcm2835_clk_probe(struct plat
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if (IS_ERR(cprman->regs))
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return PTR_ERR(cprman->regs);
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+ /* Mux DSI0 clock to PLLD */
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+ cprman_write(cprman, CM_DSI0HSCK, 1);
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+
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fw_node = of_parse_phandle(dev->of_node, "firmware", 0);
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if (fw_node) {
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struct rpi_firmware *fw = rpi_firmware_get(fw_node);
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