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28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
From fccbb0c52438762999ea16c85d4ebf4cc7e2deff Mon Sep 17 00:00:00 2001
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From: Hal Feng <hal.feng@starfivetech.com>
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Date: Sat, 1 Apr 2023 19:19:30 +0800
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Subject: [PATCH 020/122] dt-bindings: riscv: Add SiFive S7 compatible
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Add a new compatible string in cpu.yaml for SiFive S7 CPU
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core which is used on SiFive U74-MC core complex etc.
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
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1 file changed, 1 insertion(+)
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--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
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+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
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@@ -33,6 +33,7 @@ properties:
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- sifive,e5
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- sifive,e7
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- sifive,e71
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+ - sifive,s7
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- sifive,u74-mc
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- sifive,u54
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- sifive,u74
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