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72 lines
2.5 KiB
Diff
72 lines
2.5 KiB
Diff
From ffd7ee4fbd69d477a2156d9cba6ae80434a4c894 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Tue, 14 Mar 2023 17:16:07 +0800
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Subject: [PATCH 034/122] clk: starfive: jh7110-sys: Modify PLL clocks source
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Modify PLL clocks source to be got from dts instead of
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the fixed factor clocks.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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drivers/clk/starfive/Kconfig | 1 +
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.../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++---------------
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2 files changed, 7 insertions(+), 25 deletions(-)
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--- a/drivers/clk/starfive/Kconfig
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+++ b/drivers/clk/starfive/Kconfig
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@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
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select AUXILIARY_BUS
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select CLK_STARFIVE_JH71X0
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select RESET_STARFIVE_JH7110
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+ select CLK_STARFIVE_JH7110_PLL
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default ARCH_STARFIVE
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help
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Say yes here to support the system clock controller on the
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--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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@@ -404,29 +404,6 @@ static int __init jh7110_syscrg_probe(st
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dev_set_drvdata(priv->dev, (void *)(&priv->base));
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- /*
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- * These PLL clocks are not actually fixed factor clocks and can be
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- * controlled by the syscon registers of JH7110. They will be dropped
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- * and registered in the PLL clock driver instead.
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- */
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- /* 24MHz -> 1000.0MHz */
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- priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
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- "osc", 0, 125, 3);
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- if (IS_ERR(priv->pll[0]))
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- return PTR_ERR(priv->pll[0]);
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-
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- /* 24MHz -> 1066.0MHz */
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- priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
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- "osc", 0, 533, 12);
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- if (IS_ERR(priv->pll[1]))
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- return PTR_ERR(priv->pll[1]);
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-
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- /* 24MHz -> 1188.0MHz */
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- priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
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- "osc", 0, 99, 2);
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- if (IS_ERR(priv->pll[2]))
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- return PTR_ERR(priv->pll[2]);
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-
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for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
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u32 max = jh7110_sysclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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@@ -464,8 +441,12 @@ static int __init jh7110_syscrg_probe(st
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parents[i].fw_name = "tdm_ext";
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else if (pidx == JH7110_SYSCLK_MCLK_EXT)
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parents[i].fw_name = "mclk_ext";
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- else
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- parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
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+ else if (pidx == JH7110_SYSCLK_PLL0_OUT)
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+ parents[i].fw_name = "pll0_out";
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+ else if (pidx == JH7110_SYSCLK_PLL1_OUT)
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+ parents[i].fw_name = "pll1_out";
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+ else if (pidx == JH7110_SYSCLK_PLL2_OUT)
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+ parents[i].fw_name = "pll2_out";
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}
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clk->hw.init = &init;
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