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56 lines
1.9 KiB
Diff
56 lines
1.9 KiB
Diff
From 60817a4e755c6e98092fdceec35fcda94d35e4b1 Mon Sep 17 00:00:00 2001
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From: Jack Zhu <jack.zhu@starfivetech.com>
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Date: Tue, 23 May 2023 16:56:23 +0800
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Subject: [PATCH 077/122] media: dt-bindings: cadence-csi2rx: Add resets
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property
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Add resets property for Cadence MIPI-CSI2 RX controller
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
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---
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.../bindings/media/cdns,csi2rx.yaml | 24 +++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
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+++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
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@@ -41,6 +41,24 @@ properties:
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- const: pixel_if2_clk
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- const: pixel_if3_clk
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+ resets:
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+ items:
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+ - description: CSI2Rx system reset
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+ - description: Gated Register bank reset for APB interface
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+ - description: pixel reset for Stream interface 0
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+ - description: pixel reset for Stream interface 1
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+ - description: pixel reset for Stream interface 2
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+ - description: pixel reset for Stream interface 3
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+
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+ reset-names:
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+ items:
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+ - const: sys
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+ - const: reg_bank
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+ - const: pixel_if0
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+ - const: pixel_if1
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+ - const: pixel_if2
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+ - const: pixel_if3
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+
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phys:
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maxItems: 1
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description: MIPI D-PHY
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@@ -123,6 +141,12 @@ examples:
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clock-names = "sys_clk", "p_clk",
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"pixel_if0_clk", "pixel_if1_clk",
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"pixel_if2_clk", "pixel_if3_clk";
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+ resets = <&bytereset 9>, <&bytereset 4>,
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+ <&corereset 5>, <&corereset 6>,
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+ <&corereset 7>, <&corereset 8>;
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+ reset-names = "sys", "reg_bank",
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+ "pixel_if0", "pixel_if1",
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+ "pixel_if2", "pixel_if3";
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phys = <&csi_phy>;
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phy-names = "dphy";
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