Initial commit

package/devel/valgrind/patches/100-fix_configure_check.patch

@@ -0,0 +1,11 @@
+--- a/configure.ac
++++ b/configure.ac
+@@ -345,7 +345,7 @@ case "${host_os}" in
+         # Ok, this is linux. Check the kernel version
+         AC_MSG_CHECKING([for the kernel version])
+ 
+-        kernel=`uname -r`
++        kernel=${UNAME_R:-`uname -r`}
+ 
+         case "${kernel}" in
+              0.*|1.*|2.0.*|2.1.*|2.2.*|2.3.*|2.4.*|2.5.*) 

package/devel/valgrind/patches/130-fix_arm_arch_detection.patch

@@ -0,0 +1,17 @@
+Description: Fix FTBFS on armhf by correctly detecting the architecture
+Origin: vendor
+Bug-Debian: http://bugs.debian.org/730844
+Author: Alessandro Ghedini <ghedo@debian.org>
+Last-Update: 2013-11-30
+
+--- a/configure.ac
++++ b/configure.ac
+@@ -252,7 +252,7 @@ case "${host_cpu}" in
+         ARCH_MAX="s390x"
+         ;;
+ 
+-     armv7*)
++     arm*)
+ 	AC_MSG_RESULT([ok (${host_cpu})])
+ 	ARCH_MAX="arm"
+ 	;;

package/devel/valgrind/patches/130-mips_fix_soft_float.patch

@@ -0,0 +1,68 @@
+Disable the valgrind helpers which use MIPS floating point operations 
+when floating point support is deactivated in the toolchain.
+
+The fix from this commit is not sufficient any more:
+https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=869fcf2f6739f17b4eff36ec68f8dca826c8afeb
+
+This fixes the following error message when compiling with a GCC 10 MIPS BE 32:
+---------------------------------------------------------
+../VEX/priv/guest_mips_helpers.c: In function 'mips_dirtyhelper_calculate_FCSR_fp32':
+../VEX/priv/guest_mips_helpers.c:640:10: error: the register '$f21' cannot be clobbered in 'asm' for the current target
+  640 |          ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)
+      |          ^
+---------------------------------------------------------
+
+--- a/VEX/priv/guest_mips_helpers.c
++++ b/VEX/priv/guest_mips_helpers.c
+@@ -617,6 +617,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
++#ifndef __mips_soft_float
+ #if defined(__mips__)
+    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
+    UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
+@@ -699,6 +700,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
++#endif
+    return ret;
+ }
+ 
+@@ -708,6 +710,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
++#ifndef __mips_soft_float
+ #if defined(__mips__) && ((__mips == 64) ||                                  \
+                           (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
+ #if defined(VGA_mips32)
+@@ -860,6 +863,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
++#endif
+    return ret;
+ }
+ 
+--- a/coregrind/m_machine.c
++++ b/coregrind/m_machine.c
+@@ -1828,6 +1828,7 @@ Bool VG_(machine_get_hwcaps)( void )
+            we are using alternative way to determine FP mode */
+         ULong result = 0;
+ 
++#ifndef __mips_soft_float
+         if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {
+            __asm__ volatile (
+               ".set push\n\t"
+@@ -1845,6 +1846,9 @@ Bool VG_(machine_get_hwcaps)( void )
+ 
+            fpmode = (result != 0x3FF0000000000000ull);
+         }
++#else
++	fpmode = 0;
++#endif
+      }
+ 
+      if (fpmode != 0)