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domenico
2025-06-24 13:14:22 +02:00
commit 4002f145fc
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34
target/linux/ath79/files/arch/mips/include/asm/fw/myloader/myloader.h Normal file
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/*
* Compex's MyLoader specific definitions
*
* Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef _ASM_MIPS_FW_MYLOADER_H
#define _ASM_MIPS_FW_MYLOADER_H
#include <linux/myloader.h>
struct myloader_info {
uint32_t vid;
uint32_t did;
uint32_t svid;
uint32_t sdid;
uint8_t macs[MYLO_ETHADDR_COUNT][6];
};
#ifdef CONFIG_MYLOADER
extern struct myloader_info *myloader_get_info(void) __init;
#else
static inline struct myloader_info *myloader_get_info(void)
{
return NULL;
}
#endif /* CONFIG_MYLOADER */
#endif /* _ASM_MIPS_FW_MYLOADER_H */

203
target/linux/ath79/files/drivers/gpio/gpio-latch.c Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* GPIO latch driver
*
* Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#define GPIO_LATCH_DRIVER_NAME "gpio-latch"
#define GPIO_LATCH_LINES 9
struct gpio_latch_chip {
struct gpio_chip gc;
struct mutex mutex;
struct mutex latch_mutex;
bool latch_enabled;
int le_gpio;
bool le_active_low;
struct gpio_desc *gpios[GPIO_LATCH_LINES];
};
static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
{
return container_of(gc, struct gpio_latch_chip, gc);
}
static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
{
mutex_lock(&glc->mutex);
if (enable)
glc->latch_enabled = true;
if (glc->latch_enabled)
mutex_lock(&glc->latch_mutex);
}
static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
{
if (glc->latch_enabled)
mutex_unlock(&glc->latch_mutex);
if (disable)
glc->latch_enabled = true;
mutex_unlock(&glc->mutex);
}
static int
gpio_latch_get(struct gpio_chip *gc, unsigned offset)
{
struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
int ret;
gpio_latch_lock(glc, false);
ret = gpiod_get_value(glc->gpios[offset]);
gpio_latch_unlock(glc, false);
return ret;
}
static void
gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
bool enable_latch = false;
bool disable_latch = false;
if (offset == glc->le_gpio) {
enable_latch = value ^ glc->le_active_low;
disable_latch = !enable_latch;
}
gpio_latch_lock(glc, enable_latch);
gpiod_set_raw_value(glc->gpios[offset], value);
gpio_latch_unlock(glc, disable_latch);
}
static int
gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
{
struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
bool enable_latch = false;
bool disable_latch = false;
int ret;
if (offset == glc->le_gpio) {
enable_latch = value ^ glc->le_active_low;
disable_latch = !enable_latch;
}
gpio_latch_lock(glc, enable_latch);
ret = gpiod_direction_output_raw(glc->gpios[offset], value);
gpio_latch_unlock(glc, disable_latch);
return ret;
}
static int gpio_latch_probe(struct platform_device *pdev)
{
struct gpio_latch_chip *glc;
struct gpio_chip *gc;
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
int i, n;
glc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);
if (!glc)
return -ENOMEM;
mutex_init(&glc->mutex);
mutex_init(&glc->latch_mutex);
n = gpiod_count(dev, NULL);
if (n <= 0) {
dev_err(dev, "failed to get gpios: %d\n", n);
return n;
} else if (n != GPIO_LATCH_LINES) {
dev_err(dev, "expected %d gpios\n", GPIO_LATCH_LINES);
return -EINVAL;
}
for (i = 0; i < n; i++) {
glc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,
GPIOD_OUT_LOW);
if (IS_ERR(glc->gpios[i])) {
dev_err(dev, "failed to get gpio %d: %d\n", i,
PTR_ERR(glc->gpios[i]));
return PTR_ERR(glc->gpios[i]);
}
}
glc->le_gpio = 8;
glc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);
if (!glc->gpios[glc->le_gpio]) {
dev_err(dev, "missing required latch-enable gpio %d\n",
glc->le_gpio);
return -EINVAL;
}
gc = &glc->gc;
gc->label = GPIO_LATCH_DRIVER_NAME;
gc->can_sleep = true;
gc->base = -1;
gc->ngpio = GPIO_LATCH_LINES;
gc->get = gpio_latch_get;
gc->set = gpio_latch_set;
gc->direction_output = gpio_latch_direction_output;
gc->of_node = of_node;
platform_set_drvdata(pdev, glc);
i = gpiochip_add(&glc->gc);
if (i) {
dev_err(dev, "gpiochip_add() failed: %d\n", i);
return i;
}
return 0;
}
static int gpio_latch_remove(struct platform_device *pdev)
{
struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
gpiochip_remove(&glc->gc);
return 0;
}
static const struct of_device_id gpio_latch_match[] = {
{ .compatible = GPIO_LATCH_DRIVER_NAME },
{},
};
MODULE_DEVICE_TABLE(of, gpio_latch_match);
static struct platform_driver gpio_latch_driver = {
.probe = gpio_latch_probe,
.remove = gpio_latch_remove,
.driver = {
.name = GPIO_LATCH_DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = gpio_latch_match,
},
};
module_platform_driver(gpio_latch_driver);
MODULE_DESCRIPTION("GPIO latch driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);

172
target/linux/ath79/files/drivers/gpio/gpio-rb4xx.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for the MikroTik RouterBoard 4xx series
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>
*
* This file was based on the driver for Linux 2.6.22 published by
* MikroTik for their RouterBoard 4xx series devices.
*
* N.B. driver probe reports "DMA mask not set" warnings which are
* an artifact of using a platform_driver as an MFD device child.
* See conversation here https://lkml.org/lkml/2020/4/28/675
*/
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <mfd/rb4xx-cpld.h>
struct rb4xx_gpio {
struct rb4xx_cpld *cpld;
struct device *dev;
struct gpio_chip chip;
struct mutex lock;
u16 values; /* bitfield of GPIO 0-8 current values */
};
static int rb4xx_gpio_cpld_set(struct rb4xx_gpio *gpio, unsigned int offset,
int value)
{
struct rb4xx_cpld *cpld = gpio->cpld;
u16 values;
int ret;
mutex_lock(&gpio->lock);
values = gpio->values;
if (value)
values |= BIT(offset);
else
values &= ~(BIT(offset));
if (values == gpio->values) {
ret = 0;
goto unlock;
}
if (offset < 8) {
ret = cpld->gpio_set_0_7(cpld, values & 0xff);
} else if (offset == 8) {
ret = cpld->gpio_set_8(cpld, values >> 8);
}
if(likely(!ret))
gpio->values = values;
unlock:
mutex_unlock(&gpio->lock);
return ret;
}
static int rb4xx_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
return 0; /* All 9 GPIOs are out */
}
static int rb4xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
return -EOPNOTSUPP;
}
static int rb4xx_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
return rb4xx_gpio_cpld_set(gpiochip_get_data(chip), offset, value);
}
static int rb4xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct rb4xx_gpio *gpio = gpiochip_get_data(chip);
int ret;
mutex_lock(&gpio->lock);
ret = (gpio->values >> offset) & 0x1;
mutex_unlock(&gpio->lock);
return ret;
}
static void rb4xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
rb4xx_gpio_cpld_set(gpiochip_get_data(chip), offset, value);
}
static int rb4xx_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct rb4xx_gpio *gpio;
u32 val;
if (!parent)
return -ENODEV;
gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
platform_set_drvdata(pdev, gpio);
gpio->cpld = dev_get_drvdata(parent);
gpio->dev = dev;
gpio->values = 0;
mutex_init(&gpio->lock);
gpio->chip.label = "rb4xx-gpio";
gpio->chip.parent = dev;
gpio->chip.owner = THIS_MODULE;
gpio->chip.get_direction = rb4xx_gpio_get_direction;
gpio->chip.direction_input = rb4xx_gpio_direction_input;
gpio->chip.direction_output = rb4xx_gpio_direction_output;
gpio->chip.get = rb4xx_gpio_get;
gpio->chip.set = rb4xx_gpio_set;
gpio->chip.ngpio = 9;
gpio->chip.base = -1;
gpio->chip.can_sleep = 1;
if (!of_property_read_u32(dev->of_node, "base", &val))
gpio->chip.base = val;
return gpiochip_add_data(&gpio->chip, gpio);
}
static int rb4xx_gpio_remove(struct platform_device *pdev)
{
struct rb4xx_gpio *gpio = platform_get_drvdata(pdev);
gpiochip_remove(&gpio->chip);
mutex_destroy(&gpio->lock);
return 0;
}
static const struct platform_device_id rb4xx_gpio_id_table[] = {
{ "mikrotik,rb4xx-gpio", },
{ },
};
MODULE_DEVICE_TABLE(platform, rb4xx_gpio_id_table);
static struct platform_driver rb4xx_gpio_driver = {
.probe = rb4xx_gpio_probe,
.remove = rb4xx_gpio_remove,
.id_table = rb4xx_gpio_id_table,
.driver = {
.name = "rb4xx-gpio",
},
};
module_platform_driver(rb4xx_gpio_driver);
MODULE_DESCRIPTION("Mikrotik RB4xx GPIO driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
MODULE_AUTHOR("Christopher Hill <ch6574@gmail.com");
MODULE_LICENSE("GPL v2");

182
target/linux/ath79/files/drivers/mfd/rb4xx-cpld.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* CPLD driver for the MikroTik RouterBoard 4xx series
*
* This driver provides access to a CPLD that interfaces between the SoC SPI bus
* and other devices. Behind the CPLD there is a NAND flash chip and five LEDs.
*
* The CPLD supports SPI two-wire mode, in which two bits are transferred per
* SPI clock cycle. The second bit is transmitted with the SoC's CS2 pin.
*
* The CPLD also acts as a GPIO expander.
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>
*
* This file was based on the driver for Linux 2.6.22 published by
* MikroTik for their RouterBoard 4xx series devices.
*/
#include <linux/mfd/core.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <mfd/rb4xx-cpld.h>
/* CPLD commands */
#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send idle */
#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */
#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */
#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */
#define CPLD_CMD_GPIO8_HIGH 0x0c /* send cmd */
#define CPLD_CMD_GPIO8_LOW 0x0d /* send cmd */
static int rb4xx_cpld_write_nand(struct rb4xx_cpld *cpld, const void *tx_buf,
unsigned int len)
{
struct spi_message m;
static const u8 cmd = CPLD_CMD_WRITE_NAND;
struct spi_transfer t[3] = {
{
.tx_buf = &cmd,
.len = sizeof(cmd),
}, {
.tx_buf = tx_buf,
.len = len,
.tx_nbits = SPI_NBITS_DUAL,
}, {
.len = 1,
.tx_nbits = SPI_NBITS_DUAL,
},
};
spi_message_init(&m);
spi_message_add_tail(&t[0], &m);
spi_message_add_tail(&t[1], &m);
spi_message_add_tail(&t[2], &m);
return spi_sync(cpld->spi, &m);
}
static int rb4xx_cpld_read_nand(struct rb4xx_cpld *cpld, void *rx_buf,
unsigned int len)
{
struct spi_message m;
static const u8 cmd[2] = {
CPLD_CMD_READ_NAND, 0
};
struct spi_transfer t[2] = {
{
.tx_buf = &cmd,
.len = sizeof(cmd),
}, {
.rx_buf = rx_buf,
.len = len,
},
};
spi_message_init(&m);
spi_message_add_tail(&t[0], &m);
spi_message_add_tail(&t[1], &m);
return spi_sync(cpld->spi, &m);
}
static int rb4xx_cpld_cmd(struct rb4xx_cpld *cpld, const void *tx_buf,
unsigned int len)
{
struct spi_message m;
struct spi_transfer t = {
.tx_buf = tx_buf,
.len = len,
};
spi_message_init(&m);
spi_message_add_tail(&t, &m);
return spi_sync(cpld->spi, &m);
}
static int rb4xx_cpld_gpio_set_0_7(struct rb4xx_cpld *cpld, u8 values)
{
/* GPIO 0-7 change can be sent via command + bitfield */
u8 cmd[2] = {
CPLD_CMD_WRITE_CFG, values
};
return rb4xx_cpld_cmd(cpld, &cmd, 2);
}
static int rb4xx_cpld_gpio_set_8(struct rb4xx_cpld *cpld, u8 value)
{
/* GPIO 8 uses dedicated high/low commands */
u8 cmd = CPLD_CMD_GPIO8_HIGH | !!(value);
return rb4xx_cpld_cmd(cpld, &cmd, 1);
}
static const struct mfd_cell rb4xx_cpld_cells[] = {
{
.name = "mikrotik,rb4xx-gpio",
.of_compatible = "mikrotik,rb4xx-gpio",
}, {
.name = "mikrotik,rb4xx-nand",
.of_compatible = "mikrotik,rb4xx-nand",
},
};
static int rb4xx_cpld_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct rb4xx_cpld *cpld;
int ret;
cpld = devm_kzalloc(dev, sizeof(*cpld), GFP_KERNEL);
if (!cpld)
return -ENOMEM;
dev_set_drvdata(dev, cpld);
cpld->spi = spi;
cpld->write_nand = rb4xx_cpld_write_nand;
cpld->read_nand = rb4xx_cpld_read_nand;
cpld->gpio_set_0_7 = rb4xx_cpld_gpio_set_0_7;
cpld->gpio_set_8 = rb4xx_cpld_gpio_set_8;
spi->mode = SPI_MODE_0 | SPI_TX_DUAL;
ret = spi_setup(spi);
if (ret)
return ret;
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
rb4xx_cpld_cells,
ARRAY_SIZE(rb4xx_cpld_cells),
NULL, 0, NULL);
}
static int rb4xx_cpld_remove(struct spi_device *spi)
{
return 0;
}
static const struct of_device_id rb4xx_cpld_dt_match[] = {
{ .compatible = "mikrotik,rb4xx-cpld", },
{ },
};
MODULE_DEVICE_TABLE(of, rb4xx_cpld_dt_match);
static struct spi_driver rb4xx_cpld_driver = {
.probe = rb4xx_cpld_probe,
.remove = rb4xx_cpld_remove,
.driver = {
.name = "rb4xx-cpld",
.bus = &spi_bus_type,
.of_match_table = of_match_ptr(rb4xx_cpld_dt_match),
},
};
module_spi_driver(rb4xx_cpld_driver);
MODULE_DESCRIPTION("Mikrotik RB4xx CPLD driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
MODULE_AUTHOR("Christopher Hill <ch6574@gmail.com");
MODULE_LICENSE("GPL v2");

1526
target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c Normal file
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262
target/linux/ath79/files/drivers/mtd/nand/raw/nand_rb4xx.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* NAND driver for the MikroTik RouterBoard 4xx series
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>
*
* This file was based on the driver for Linux 2.6.22 published by
* MikroTik for their RouterBoard 4xx series devices.
*
* N.B. driver probe reports "DMA mask not set" warnings which are
* an artifact of using a platform_driver as an MFD device child.
* See conversation here https://lkml.org/lkml/2020/4/28/675
*/
#include <linux/platform_device.h>
#include <linux/mtd/rawnand.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/version.h>
#include <mfd/rb4xx-cpld.h>
struct rb4xx_nand {
struct rb4xx_cpld *cpld;
struct device *dev;
struct nand_chip chip;
struct gpio_desc *ale;
struct gpio_desc *cle;
struct gpio_desc *nce;
struct gpio_desc *rdy;
};
static int rb4xx_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
switch (section) {
case 0:
oobregion->offset = 8;
oobregion->length = 3;
return 0;
case 1:
oobregion->offset = 13;
oobregion->length = 3;
return 0;
default:
return -ERANGE;
}
}
static int rb4xx_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
switch (section) {
case 0:
oobregion->offset = 0;
oobregion->length = 4;
return 0;
case 1:
oobregion->offset = 4;
oobregion->length = 1;
return 0;
case 2:
oobregion->offset = 6;
oobregion->length = 2;
return 0;
case 3:
oobregion->offset = 11;
oobregion->length = 2;
return 0;
default:
return -ERANGE;
}
}
static const struct mtd_ooblayout_ops rb4xx_nand_ecclayout_ops = {
.ecc = rb4xx_ooblayout_ecc,
.free = rb4xx_ooblayout_free,
};
static u8 rb4xx_nand_read_byte(struct nand_chip *chip)
{
struct rb4xx_nand *nand = chip->priv;
struct rb4xx_cpld *cpld = nand->cpld;
u8 data;
int ret;
ret = cpld->read_nand(cpld, &data, 1);
if (unlikely(ret))
return 0xff;
return data;
}
static void rb4xx_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
struct rb4xx_nand *nand = chip->priv;
struct rb4xx_cpld *cpld = nand->cpld;
cpld->write_nand(cpld, buf, len);
}
static void rb4xx_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
struct rb4xx_nand *nand = chip->priv;
struct rb4xx_cpld *cpld = nand->cpld;
cpld->read_nand(cpld, buf, len);
}
static void rb4xx_nand_cmd_ctrl(struct nand_chip *chip, int dat,
unsigned int ctrl)
{
struct rb4xx_nand *nand = chip->priv;
struct rb4xx_cpld *cpld = nand->cpld;
u8 data = dat;
if (ctrl & NAND_CTRL_CHANGE) {
gpiod_set_value_cansleep(nand->cle, !!(ctrl & NAND_CLE));
gpiod_set_value_cansleep(nand->ale, !!(ctrl & NAND_ALE));
gpiod_set_value_cansleep(nand->nce, !(ctrl & NAND_NCE));
}
if (dat != NAND_CMD_NONE)
cpld->write_nand(cpld, &data, 1);
}
static int rb4xx_nand_dev_ready(struct nand_chip *chip)
{
struct rb4xx_nand *nand = chip->priv;
return gpiod_get_value_cansleep(nand->rdy);
}
static int rb4xx_nand_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct rb4xx_nand *nand;
struct mtd_info *mtd;
int ret;
if (!parent)
return -ENODEV;
nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
if (!nand)
return -ENOMEM;
platform_set_drvdata(pdev, nand);
nand->cpld = dev_get_drvdata(parent);
nand->dev = dev;
nand->ale = devm_gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);
if (IS_ERR(nand->ale))
dev_err(dev, "missing gpio ALE: %ld\n", PTR_ERR(nand->ale));
nand->cle = devm_gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);
if (IS_ERR(nand->cle))
dev_err(dev, "missing gpio CLE: %ld\n", PTR_ERR(nand->cle));
nand->nce = devm_gpiod_get_index(dev, NULL, 2, GPIOD_OUT_LOW);
if (IS_ERR(nand->nce))
dev_err(dev, "missing gpio nCE: %ld\n", PTR_ERR(nand->nce));
nand->rdy = devm_gpiod_get_index(dev, NULL, 3, GPIOD_IN);
if (IS_ERR(nand->rdy))
dev_err(dev, "missing gpio RDY: %ld\n", PTR_ERR(nand->rdy));
if (IS_ERR(nand->ale) || IS_ERR(nand->cle) ||
IS_ERR(nand->nce) || IS_ERR(nand->rdy))
return -ENOENT;
gpiod_set_consumer_name(nand->ale, "mikrotik:nand:ALE");
gpiod_set_consumer_name(nand->cle, "mikrotik:nand:CLE");
gpiod_set_consumer_name(nand->nce, "mikrotik:nand:nCE");
gpiod_set_consumer_name(nand->rdy, "mikrotik:nand:RDY");
mtd = nand_to_mtd(&nand->chip);
mtd->priv = nand;
mtd->owner = THIS_MODULE;
mtd->dev.parent = dev;
mtd_set_of_node(mtd, dev->of_node);
if (mtd->writesize == 512)
mtd_set_ooblayout(mtd, &rb4xx_nand_ecclayout_ops);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
nand->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
nand->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
#else
nand->chip.ecc.mode = NAND_ECC_SOFT;
nand->chip.ecc.algo = NAND_ECC_HAMMING;
#endif
nand->chip.options = NAND_NO_SUBPAGE_WRITE;
nand->chip.priv = nand;
nand->chip.legacy.read_byte = rb4xx_nand_read_byte;
nand->chip.legacy.write_buf = rb4xx_nand_write_buf;
nand->chip.legacy.read_buf = rb4xx_nand_read_buf;
nand->chip.legacy.cmd_ctrl = rb4xx_nand_cmd_ctrl;
nand->chip.legacy.dev_ready = rb4xx_nand_dev_ready;
nand->chip.legacy.chip_delay = 25;
ret = nand_scan(&nand->chip, 1);
if (ret)
return -ENXIO;
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
return ret;
}
return 0;
}
static int rb4xx_nand_remove(struct platform_device *pdev)
{
struct rb4xx_nand *nand = platform_get_drvdata(pdev);
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&nand->chip));
nand_cleanup(&nand->chip);
#else
nand_release(&nand->chip);
#endif
return 0;
}
static const struct platform_device_id rb4xx_nand_id_table[] = {
{ "mikrotik,rb4xx-nand", },
{ },
};
MODULE_DEVICE_TABLE(platform, rb4xx_nand_id_table);
static struct platform_driver rb4xx_nand_driver = {
.probe = rb4xx_nand_probe,
.remove = rb4xx_nand_remove,
.id_table = rb4xx_nand_id_table,
.driver = {
.name = "rb4xx-nand",
},
};
module_platform_driver(rb4xx_nand_driver);
MODULE_DESCRIPTION("Mikrotik RB4xx NAND driver");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
MODULE_AUTHOR("Christopher Hill <ch6574@gmail.com");
MODULE_LICENSE("GPL v2");

375
target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c Normal file
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@@ -0,0 +1,375 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MikroTik RB91x NAND flash driver
*
* Main part is copied from original driver written by Gabor Juhos.
*
* Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
*/
/*
* WARNING: to speed up NAND reading/writing we are working with SoC GPIO
* controller registers directly -- not through standard GPIO API.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <linux/version.h>
#include <linux/of_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
/* Bit masks for NAND data lines in ath79 gpio 32-bit register */
#define RB91X_NAND_NRW_BIT BIT(12)
#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \
| BIT(13) | BIT(14) | BIT(15))
#define RB91X_NAND_LOW_DATA_MASK 0x1f
#define RB91X_NAND_HIGH_DATA_MASK 0xe0
#define RB91X_NAND_HIGH_DATA_SHIFT 8
enum rb91x_nand_gpios {
RB91X_NAND_READ,/* Read */
RB91X_NAND_RDY, /* NAND Ready */
RB91X_NAND_NCE, /* Chip Enable. Active low */
RB91X_NAND_CLE, /* Command Latch Enable */
RB91X_NAND_ALE, /* Address Latch Enable */
RB91X_NAND_NRW, /* Read/Write. Active low */
RB91X_NAND_NLE, /* Latch Enable. Active low */
RB91X_NAND_GPIOS,
};
struct rb91x_nand_drvdata {
struct nand_chip chip;
struct device *dev;
struct gpio_desc **gpio;
void __iomem *ath79_gpio_base;
};
static inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,
int lock)
{
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);
}
static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
switch (section) {
case 0:
oobregion->offset = 8;
oobregion->length = 3;
return 0;
case 1:
oobregion->offset = 13;
oobregion->length = 3;
return 0;
default:
return -ERANGE;
}
}
static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
switch (section) {
case 0:
oobregion->offset = 0;
oobregion->length = 4;
return 0;
case 1:
oobregion->offset = 4;
oobregion->length = 1;
return 0;
case 2:
oobregion->offset = 6;
oobregion->length = 2;
return 0;
case 3:
oobregion->offset = 11;
oobregion->length = 2;
return 0;
default:
return -ERANGE;
}
}
static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
.ecc = rb91x_ooblayout_ecc,
.free = rb91x_ooblayout_free,
};
static void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,
const u8 *buf,
unsigned len)
{
void __iomem *base = drvdata->ath79_gpio_base;
u32 oe_reg;
u32 out_reg;
u32 out;
unsigned i;
rb91x_nand_latch_lock(drvdata, 1);
oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
/* Set data lines to output mode */
__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),
base + AR71XX_GPIO_REG_OE);
out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);
for (i = 0; i != len; i++) {
u32 data;
data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
RB91X_NAND_HIGH_DATA_SHIFT;
data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
data |= out;
__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
/* Deactivate WE line */
data |= RB91X_NAND_NRW_BIT;
__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
/* Flush write */
__raw_readl(base + AR71XX_GPIO_REG_OUT);
}
/* Restore registers */
__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
/* Flush write */
__raw_readl(base + AR71XX_GPIO_REG_OUT);
rb91x_nand_latch_lock(drvdata, 0);
}
static void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,
u8 *read_buf,
unsigned len)
{
void __iomem *base = drvdata->ath79_gpio_base;
u32 oe_reg;
u32 out_reg;
unsigned i;
/* Enable read mode */
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);
rb91x_nand_latch_lock(drvdata, 1);
/* Save registers */
oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
/* Set data lines to input mode */
__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
base + AR71XX_GPIO_REG_OE);
for (i = 0; i < len; i++) {
u32 in;
u8 data;
/* Activate RE line */
__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);
/* Flush write */
__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
/* Read input lines */
in = __raw_readl(base + AR71XX_GPIO_REG_IN);
/* Deactivate RE line */
__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);
data = (in & RB91X_NAND_LOW_DATA_MASK);
data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
RB91X_NAND_HIGH_DATA_MASK;
read_buf[i] = data;
}
/* Restore registers */
__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
/* Flush write */
__raw_readl(base + AR71XX_GPIO_REG_OUT);
rb91x_nand_latch_lock(drvdata, 0);
/* Disable read mode */
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);
}
static int rb91x_nand_dev_ready(struct nand_chip *chip)
{
struct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);
return gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);
}
static void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
unsigned int ctrl)
{
struct rb91x_nand_drvdata *drvdata = chip->priv;
if (ctrl & NAND_CTRL_CHANGE) {
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],
(ctrl & NAND_CLE) ? 1 : 0);
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],
(ctrl & NAND_ALE) ? 1 : 0);
gpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],
(ctrl & NAND_NCE) ? 1 : 0);
}
if (cmd != NAND_CMD_NONE) {
u8 t = cmd;
rb91x_nand_write(drvdata, &t, 1);
}
}
static u8 rb91x_nand_read_byte(struct nand_chip *chip)
{
u8 data = 0xff;
rb91x_nand_read(chip->priv, &data, 1);
return data;
}
static void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
rb91x_nand_read(chip->priv, buf, len);
}
static void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
rb91x_nand_write(chip->priv, buf, len);
}
static void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
mtd_device_unregister(nand_to_mtd(&drvdata->chip));
nand_cleanup(&drvdata->chip);
#else
nand_release(&drvdata->chip);
#endif
}
static int rb91x_nand_probe(struct platform_device *pdev)
{
struct rb91x_nand_drvdata *drvdata;
struct mtd_info *mtd;
int r;
struct device *dev = &pdev->dev;
struct gpio_descs *gpios;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
platform_set_drvdata(pdev, drvdata);
gpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);
if (IS_ERR(gpios)) {
dev_err(dev, "failed to get gpios: %d\n", (int)gpios);
return -EINVAL;
}
if (gpios->ndescs != RB91X_NAND_GPIOS) {
dev_err(dev, "expected %d gpios\n", RB91X_NAND_GPIOS);
return -EINVAL;
}
drvdata->gpio = gpios->desc;
gpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);
drvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
drvdata->dev = dev;
drvdata->chip.priv = drvdata;
drvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;
drvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;
drvdata->chip.legacy.read_byte = rb91x_nand_read_byte;
drvdata->chip.legacy.write_buf = rb91x_nand_write_buf;
drvdata->chip.legacy.read_buf = rb91x_nand_read_buf;
drvdata->chip.legacy.chip_delay = 25;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
drvdata->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
drvdata->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
#else
drvdata->chip.ecc.mode = NAND_ECC_SOFT;
drvdata->chip.ecc.algo = NAND_ECC_HAMMING;
#endif
drvdata->chip.options = NAND_NO_SUBPAGE_WRITE;
r = nand_scan(&drvdata->chip, 1);
if (r) {
dev_err(dev, "nand_scan() failed: %d\n", r);
return r;
}
mtd = nand_to_mtd(&drvdata->chip);
mtd->dev.parent = dev;
mtd_set_of_node(mtd, dev->of_node);
mtd->owner = THIS_MODULE;
if (mtd->writesize == 512)
mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
r = mtd_device_register(mtd, NULL, 0);
if (r) {
dev_err(dev, "mtd_device_register() failed: %d\n",
r);
goto err_release_nand;
}
return 0;
err_release_nand:
rb91x_nand_release(drvdata);
return r;
}
static int rb91x_nand_remove(struct platform_device *pdev)
{
struct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);
rb91x_nand_release(drvdata);
return 0;
}
static const struct of_device_id rb91x_nand_match[] = {
{ .compatible = "mikrotik,rb91x-nand" },
{},
};
MODULE_DEVICE_TABLE(of, rb91x_nand_match);
static struct platform_driver rb91x_nand_driver = {
.probe = rb91x_nand_probe,
.remove = rb91x_nand_remove,
.driver = {
.name = "rb91x-nand",
.owner = THIS_MODULE,
.of_match_table = rb91x_nand_match,
},
};
module_platform_driver(rb91x_nand_driver);
MODULE_DESCRIPTION("MikrotTik RB91x NAND flash driver");
MODULE_VERSION(DRV_VERSION);
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
MODULE_LICENSE("GPL v2");

163
target/linux/ath79/files/drivers/mtd/parsers/parser_cybertan.c Normal file
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@@ -0,0 +1,163 @@
/*
* Copyright (C) 2009 Christian Daniel <cd@maintech.de>
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* TRX flash partition table.
* Based on ar7 map by Felix Fietkau <nbd@nbd.name>
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/version.h>
struct cybertan_header {
char magic[4];
u8 res1[4];
char fw_date[3];
char fw_ver[3];
char id[4];
char hw_ver;
char unused;
u8 flags[2];
u8 res2[10];
} __packed;
#define TRX_PARTS 3
#define TRX_MAGIC 0x30524448
#define TRX_MAX_OFFSET 3
struct trx_header {
__le32 magic; /* "HDR0" */
__le32 len; /* Length of file including header */
__le32 crc32; /* 32-bit CRC from flag_version to end of file */
__le32 flag_version; /* 0:15 flags, 16:31 version */
__le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
} __packed;
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
struct uimage_header {
__be32 ih_magic; /* Image Header Magic Number */
__be32 ih_hcrc; /* Image Header CRC Checksum */
__be32 ih_time; /* Image Creation Timestamp */
__be32 ih_size; /* Image Data Size */
__be32 ih_load; /* Data» Load Address */
__be32 ih_ep; /* Entry Point Address */
__be32 ih_dcrc; /* Image Data CRC Checksum */
uint8_t ih_os; /* Operating System */
uint8_t ih_arch; /* CPU architecture */
uint8_t ih_type; /* Image Type */
uint8_t ih_comp; /* Compression Type */
uint8_t ih_name[IH_NMLEN]; /* Image Name */
} __packed;
struct firmware_header {
struct cybertan_header cybertan;
struct trx_header trx;
struct uimage_header uimage;
} __packed;
static int cybertan_parse_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
{
struct firmware_header header;
struct trx_header *theader;
struct uimage_header *uheader;
struct mtd_partition *trx_parts;
size_t retlen;
unsigned int kernel_len;
int ret;
trx_parts = kcalloc(TRX_PARTS, sizeof(struct mtd_partition),
GFP_KERNEL);
if (!trx_parts) {
ret = -ENOMEM;
goto out;
}
ret = mtd_read(master, 0, sizeof(header),
&retlen, (uint8_t *)&header);
if (ret)
goto free_parts;
if (retlen != sizeof(header)) {
ret = -EIO;
goto free_parts;
}
theader = &header.trx;
if (theader->magic != cpu_to_le32(TRX_MAGIC)) {
printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
goto free_parts;
}
uheader = &header.uimage;
if (uheader->ih_magic != cpu_to_be32(IH_MAGIC)) {
printk(KERN_NOTICE "%s: no uImage found\n", master->name);
goto free_parts;
}
kernel_len = le32_to_cpu(theader->offsets[1]) +
sizeof(struct cybertan_header);
trx_parts[0].name = "header";
trx_parts[0].offset = 0;
trx_parts[0].size = offsetof(struct firmware_header, uimage);
trx_parts[0].mask_flags = 0;
trx_parts[1].name = "kernel";
trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
trx_parts[1].size = kernel_len - trx_parts[0].size;
trx_parts[1].mask_flags = 0;
trx_parts[2].name = "rootfs";
trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
trx_parts[2].size = master->size - trx_parts[1].size - trx_parts[0].size;
trx_parts[2].mask_flags = 0;
*pparts = trx_parts;
return TRX_PARTS;
free_parts:
kfree(trx_parts);
out:
return ret;
}
static const struct of_device_id mtd_parser_cybertan_of_match_table[] = {
{ .compatible = "cybertan,trx" },
{},
};
MODULE_DEVICE_TABLE(of, mtd_parser_cybertan_of_match_table);
static struct mtd_part_parser mtd_parser_cybertan = {
.parse_fn = cybertan_parse_partitions,
.name = "cybertan-trx",
.of_match_table = mtd_parser_cybertan_of_match_table,
};
module_mtd_part_parser(mtd_parser_cybertan);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");

25
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Kconfig Normal file
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@@ -0,0 +1,25 @@
config AG71XX
tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
depends on ATH79
select PHYLIB
help
If you wish to compile a kernel for AR7XXX/91XXX and enable
ethernet support, then you should always answer Y to this.
if AG71XX
config AG71XX_DEBUG
bool "Atheros AR71xx built-in ethernet driver debugging"
default n
help
Atheros AR71xx built-in ethernet driver debugging messages.
config AG71XX_DEBUG_FS
bool "Atheros AR71xx built-in ethernet driver debugfs support"
depends on DEBUG_FS
default n
help
Say Y, if you need access to various statistics provided by
the ag71xx driver.
endif

13
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile Normal file
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@@ -0,0 +1,13 @@
#
# Makefile for the Atheros AR71xx built-in ethernet macs
#
ag71xx-y += ag71xx_main.o
ag71xx-y += ag71xx_gmac.o
ag71xx-y += ag71xx_ethtool.o
ag71xx-y += ag71xx_phy.o
ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o
obj-$(CONFIG_AG71XX) += ag71xx_mdio.o
obj-$(CONFIG_AG71XX) += ag71xx.o

458
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h Normal file
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@@ -0,0 +1,458 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __AG71XX_H
#define __AG71XX_H
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/random.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/ethtool.h>
#include <linux/etherdevice.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/reset.h>
#include <linux/of.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/bitops.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#define AG71XX_DRV_NAME "ag71xx"
/*
* For our NAPI weight bigger does *NOT* mean better - it means more
* D-cache misses and lots more wasted cycles than we'll ever
* possibly gain from saving instructions.
*/
#define AG71XX_NAPI_WEIGHT 32
#define AG71XX_OOM_REFILL (1 + HZ/10)
#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
#define AG71XX_TX_MTU_LEN 1540
#define AG71XX_TX_RING_SPLIT 512
#define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
AG71XX_TX_RING_SPLIT)
#define AG71XX_TX_RING_SIZE_DEFAULT 128
#define AG71XX_RX_RING_SIZE_DEFAULT 256
#define AG71XX_TX_RING_SIZE_MAX 128
#define AG71XX_RX_RING_SIZE_MAX 256
#ifdef CONFIG_AG71XX_DEBUG
#define DBG(fmt, args...) pr_debug(fmt, ## args)
#else
#define DBG(fmt, args...) do {} while (0)
#endif
#define ag71xx_assert(_cond) \
do { \
if (_cond) \
break; \
printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
BUG(); \
} while (0)
struct ag71xx_desc {
u32 data;
u32 ctrl;
#define DESC_EMPTY BIT(31)
#define DESC_MORE BIT(24)
#define DESC_PKTLEN_M 0xfff
u32 next;
u32 pad;
} __attribute__((aligned(4)));
#define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
L1_CACHE_BYTES)
struct ag71xx_buf {
union {
struct sk_buff *skb;
void *rx_buf;
};
union {
dma_addr_t dma_addr;
unsigned int len;
};
};
struct ag71xx_ring {
struct ag71xx_buf *buf;
u8 *descs_cpu;
dma_addr_t descs_dma;
u16 desc_split;
u16 order;
unsigned int curr;
unsigned int dirty;
};
struct ag71xx_int_stats {
unsigned long rx_pr;
unsigned long rx_be;
unsigned long rx_of;
unsigned long tx_ps;
unsigned long tx_be;
unsigned long tx_ur;
unsigned long total;
};
struct ag71xx_napi_stats {
unsigned long napi_calls;
unsigned long rx_count;
unsigned long rx_packets;
unsigned long rx_packets_max;
unsigned long tx_count;
unsigned long tx_packets;
unsigned long tx_packets_max;
unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
};
struct ag71xx_debug {
struct dentry *debugfs_dir;
struct ag71xx_int_stats int_stats;
struct ag71xx_napi_stats napi_stats;
};
struct ag71xx {
/*
* Critical data related to the per-packet data path are clustered
* early in this structure to help improve the D-cache footprint.
*/
struct ag71xx_ring rx_ring ____cacheline_aligned;
struct ag71xx_ring tx_ring ____cacheline_aligned;
int mac_idx;
u16 desc_pktlen_mask;
u16 rx_buf_size;
u8 rx_buf_offset;
u8 tx_hang_workaround:1;
struct net_device *dev;
struct platform_device *pdev;
spinlock_t lock;
struct napi_struct napi;
u32 msg_enable;
/*
* From this point onwards we're not looking at per-packet fields.
*/
void __iomem *mac_base;
void __iomem *mii_base;
struct ag71xx_desc *stop_desc;
dma_addr_t stop_desc_dma;
struct phy_device *phy_dev;
void *phy_priv;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0)
phy_interface_t phy_if_mode;
#else
int phy_if_mode;
#endif
unsigned int link;
unsigned int speed;
int duplex;
struct delayed_work restart_work;
struct timer_list oom_timer;
struct reset_control *mac_reset;
struct reset_control *mdio_reset;
u32 fifodata[3];
u32 plldata[3];
u32 pllreg[3];
struct regmap *pllregmap;
#ifdef CONFIG_AG71XX_DEBUG_FS
struct ag71xx_debug debug;
#endif
};
struct ag71xx_mdio {
struct reset_control *mdio_reset;
struct mii_bus *mii_bus;
struct regmap *mii_regmap;
};
extern struct ethtool_ops ag71xx_ethtool_ops;
void ag71xx_link_adjust(struct ag71xx *ag);
int ag71xx_phy_connect(struct ag71xx *ag);
void ag71xx_phy_disconnect(struct ag71xx *ag);
static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
{
return (desc->ctrl & DESC_EMPTY) != 0;
}
static inline struct ag71xx_desc *
ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
{
return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
}
static inline int
ag71xx_ring_size_order(int size)
{
return fls(size - 1);
}
/* Register offsets */
#define AG71XX_REG_MAC_CFG1 0x0000
#define AG71XX_REG_MAC_CFG2 0x0004
#define AG71XX_REG_MAC_IPG 0x0008
#define AG71XX_REG_MAC_HDX 0x000c
#define AG71XX_REG_MAC_MFL 0x0010
#define AG71XX_REG_MII_CFG 0x0020
#define AG71XX_REG_MII_CMD 0x0024
#define AG71XX_REG_MII_ADDR 0x0028
#define AG71XX_REG_MII_CTRL 0x002c
#define AG71XX_REG_MII_STATUS 0x0030
#define AG71XX_REG_MII_IND 0x0034
#define AG71XX_REG_MAC_IFCTL 0x0038
#define AG71XX_REG_MAC_ADDR1 0x0040
#define AG71XX_REG_MAC_ADDR2 0x0044
#define AG71XX_REG_FIFO_CFG0 0x0048
#define AG71XX_REG_FIFO_CFG1 0x004c
#define AG71XX_REG_FIFO_CFG2 0x0050
#define AG71XX_REG_FIFO_CFG3 0x0054
#define AG71XX_REG_FIFO_CFG4 0x0058
#define AG71XX_REG_FIFO_CFG5 0x005c
#define AG71XX_REG_FIFO_RAM0 0x0060
#define AG71XX_REG_FIFO_RAM1 0x0064
#define AG71XX_REG_FIFO_RAM2 0x0068
#define AG71XX_REG_FIFO_RAM3 0x006c
#define AG71XX_REG_FIFO_RAM4 0x0070
#define AG71XX_REG_FIFO_RAM5 0x0074
#define AG71XX_REG_FIFO_RAM6 0x0078
#define AG71XX_REG_FIFO_RAM7 0x007c
#define AG71XX_REG_TX_CTRL 0x0180
#define AG71XX_REG_TX_DESC 0x0184
#define AG71XX_REG_TX_STATUS 0x0188
#define AG71XX_REG_RX_CTRL 0x018c
#define AG71XX_REG_RX_DESC 0x0190
#define AG71XX_REG_RX_STATUS 0x0194
#define AG71XX_REG_INT_ENABLE 0x0198
#define AG71XX_REG_INT_STATUS 0x019c
#define AG71XX_REG_FIFO_DEPTH 0x01a8
#define AG71XX_REG_RX_SM 0x01b0
#define AG71XX_REG_TX_SM 0x01b4
#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
#define MAC_CFG1_LB BIT(8) /* Loopback mode */
#define MAC_CFG1_SR BIT(31) /* Soft Reset */
#define MAC_CFG2_FDX BIT(0)
#define MAC_CFG2_CRC_EN BIT(1)
#define MAC_CFG2_PAD_CRC_EN BIT(2)
#define MAC_CFG2_LEN_CHECK BIT(4)
#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
#define MAC_CFG2_IF_1000 BIT(9)
#define MAC_CFG2_IF_10_100 BIT(8)
#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
| FIFO_CFG0_TXS | FIFO_CFG0_TXF)
#define FIFO_CFG0_ENABLE_SHIFT 8
#define FIFO_CFG4_DE BIT(0) /* Drop Event */
#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG4_FC BIT(2) /* False Carrier */
#define FIFO_CFG4_CE BIT(3) /* Code Error */
#define FIFO_CFG4_CR BIT(4) /* CRC error */
#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
#define FIFO_CFG4_LO BIT(6) /* Length out of range */
#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG4_DR BIT(10) /* Dribble */
#define FIFO_CFG4_LE BIT(11) /* Long Event */
#define FIFO_CFG4_CF BIT(12) /* Control Frame */
#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG5_DE BIT(0) /* Drop Event */
#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG5_FC BIT(2) /* False Carrier */
#define FIFO_CFG5_CE BIT(3) /* Code Error */
#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(9) /* Dribble */
#define FIFO_CFG5_CF BIT(10) /* Control Frame */
#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(14) /* Long Event */
#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
#define FIFO_CFG5_16 BIT(16) /* unknown */
#define FIFO_CFG5_17 BIT(17) /* unknown */
#define FIFO_CFG5_SF BIT(18) /* Short Frame */
#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
#define AG71XX_INT_TX_PS BIT(0)
#define AG71XX_INT_TX_UR BIT(1)
#define AG71XX_INT_TX_BE BIT(3)
#define AG71XX_INT_RX_PR BIT(4)
#define AG71XX_INT_RX_OF BIT(6)
#define AG71XX_INT_RX_BE BIT(7)
#define MAC_IFCTL_SPEED BIT(16)
#define MII_CFG_CLK_DIV_4 0
#define MII_CFG_CLK_DIV_6 2
#define MII_CFG_CLK_DIV_8 3
#define MII_CFG_CLK_DIV_10 4
#define MII_CFG_CLK_DIV_14 5
#define MII_CFG_CLK_DIV_20 6
#define MII_CFG_CLK_DIV_28 7
#define MII_CFG_CLK_DIV_34 8
#define MII_CFG_CLK_DIV_42 9
#define MII_CFG_CLK_DIV_50 10
#define MII_CFG_CLK_DIV_58 11
#define MII_CFG_CLK_DIV_66 12
#define MII_CFG_CLK_DIV_74 13
#define MII_CFG_CLK_DIV_82 14
#define MII_CFG_CLK_DIV_98 15
#define MII_CFG_RESET BIT(31)
#define MII_CMD_WRITE 0x0
#define MII_CMD_READ 0x1
#define MII_ADDR_SHIFT 8
#define MII_IND_BUSY BIT(0)
#define MII_IND_INVALID BIT(2)
#define TX_CTRL_TXE BIT(0) /* Tx Enable */
#define TX_STATUS_PS BIT(0) /* Packet Sent */
#define TX_STATUS_UR BIT(1) /* Tx Underrun */
#define TX_STATUS_BE BIT(3) /* Bus Error */
#define RX_CTRL_RXE BIT(0) /* Rx Enable */
#define RX_STATUS_PR BIT(0) /* Packet Received */
#define RX_STATUS_OF BIT(2) /* Rx Overflow */
#define RX_STATUS_BE BIT(3) /* Bus Error */
static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
{
__raw_writel(value, ag->mac_base + reg);
/* flush write */
(void) __raw_readl(ag->mac_base + reg);
}
static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
{
return __raw_readl(ag->mac_base + reg);
}
static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
{
void __iomem *r;
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) | mask, r);
/* flush write */
(void) __raw_readl(r);
}
static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
{
void __iomem *r;
r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) & ~mask, r);
/* flush write */
(void) __raw_readl(r);
}
static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
{
ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
}
static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
{
ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
}
#ifdef CONFIG_AG71XX_DEBUG_FS
int ag71xx_debugfs_root_init(void);
void ag71xx_debugfs_root_exit(void);
int ag71xx_debugfs_init(struct ag71xx *ag);
void ag71xx_debugfs_exit(struct ag71xx *ag);
void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
#else
static inline int ag71xx_debugfs_root_init(void) { return 0; }
static inline void ag71xx_debugfs_root_exit(void) {}
static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
u32 status) {}
static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
int rx, int tx) {}
#endif /* CONFIG_AG71XX_DEBUG_FS */
int ag71xx_ar7240_init(struct ag71xx *ag, struct device_node *np);
void ag71xx_ar7240_cleanup(struct ag71xx *ag);
int ag71xx_setup_gmac(struct device_node *np);
int ar7240sw_phy_read(struct mii_bus *mii, int addr, int reg);
int ar7240sw_phy_write(struct mii_bus *mii, int addr, int reg, u16 val);
#endif /* _AG71XX_H */

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target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c Normal file
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/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/debugfs.h>
#include "ag71xx.h"
static struct dentry *ag71xx_debugfs_root;
static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)
{
if (status)
ag->debug.int_stats.total++;
if (status & AG71XX_INT_TX_PS)
ag->debug.int_stats.tx_ps++;
if (status & AG71XX_INT_TX_UR)
ag->debug.int_stats.tx_ur++;
if (status & AG71XX_INT_TX_BE)
ag->debug.int_stats.tx_be++;
if (status & AG71XX_INT_RX_PR)
ag->debug.int_stats.rx_pr++;
if (status & AG71XX_INT_RX_OF)
ag->debug.int_stats.rx_of++;
if (status & AG71XX_INT_RX_BE)
ag->debug.int_stats.rx_be++;
}
static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
#define PR_INT_STAT(_label, _field) \
len += snprintf(buf + len, sizeof(buf) - len, \
"%20s: %10lu\n", _label, ag->debug.int_stats._field);
struct ag71xx *ag = file->private_data;
char buf[256];
unsigned int len = 0;
PR_INT_STAT("TX Packet Sent", tx_ps);
PR_INT_STAT("TX Underrun", tx_ur);
PR_INT_STAT("TX Bus Error", tx_be);
PR_INT_STAT("RX Packet Received", rx_pr);
PR_INT_STAT("RX Overflow", rx_of);
PR_INT_STAT("RX Bus Error", rx_be);
len += snprintf(buf + len, sizeof(buf) - len, "\n");
PR_INT_STAT("Total", total);
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
#undef PR_INT_STAT
}
static const struct file_operations ag71xx_fops_int_stats = {
.open = ag71xx_debugfs_generic_open,
.read = read_file_int_stats,
.owner = THIS_MODULE
};
void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)
{
struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
if (rx) {
stats->rx_count++;
stats->rx_packets += rx;
if (rx <= AG71XX_NAPI_WEIGHT)
stats->rx[rx]++;
if (rx > stats->rx_packets_max)
stats->rx_packets_max = rx;
}
if (tx) {
stats->tx_count++;
stats->tx_packets += tx;
if (tx <= AG71XX_NAPI_WEIGHT)
stats->tx[tx]++;
if (tx > stats->tx_packets_max)
stats->tx_packets_max = tx;
}
}
static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ag71xx *ag = file->private_data;
struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
char *buf;
unsigned int buflen;
unsigned int len = 0;
unsigned long rx_avg = 0;
unsigned long tx_avg = 0;
int ret;
int i;
buflen = 2048;
buf = kmalloc(buflen, GFP_KERNEL);
if (!buf)
return -ENOMEM;
if (stats->rx_count)
rx_avg = stats->rx_packets / stats->rx_count;
if (stats->tx_count)
tx_avg = stats->tx_packets / stats->tx_count;
len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n",
"len", "rx", "tx");
for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)
len += snprintf(buf + len, buflen - len,
"%3d: %10lu %10lu\n",
i, stats->rx[i], stats->tx[i]);
len += snprintf(buf + len, buflen - len, "\n");
len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
"sum", stats->rx_count, stats->tx_count);
len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
"avg", rx_avg, tx_avg);
len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
"max", stats->rx_packets_max, stats->tx_packets_max);
len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
"pkt", stats->rx_packets, stats->tx_packets);
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
kfree(buf);
return ret;
}
static const struct file_operations ag71xx_fops_napi_stats = {
.open = ag71xx_debugfs_generic_open,
.read = read_file_napi_stats,
.owner = THIS_MODULE
};
#define DESC_PRINT_LEN 64
static ssize_t read_file_ring(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos,
struct ag71xx *ag,
struct ag71xx_ring *ring,
unsigned desc_reg)
{
int ring_size = BIT(ring->order);
int ring_mask = ring_size - 1;
char *buf;
unsigned int buflen;
unsigned int len = 0;
unsigned long flags;
ssize_t ret;
int curr;
int dirty;
u32 desc_hw;
int i;
buflen = (ring_size * DESC_PRINT_LEN);
buf = kmalloc(buflen, GFP_KERNEL);
if (!buf)
return -ENOMEM;
len += snprintf(buf + len, buflen - len,
"Idx ... %-8s %-8s %-8s %-8s .\n",
"desc", "next", "data", "ctrl");
spin_lock_irqsave(&ag->lock, flags);
curr = (ring->curr & ring_mask);
dirty = (ring->dirty & ring_mask);
desc_hw = ag71xx_rr(ag, desc_reg);
for (i = 0; i < ring_size; i++) {
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
u32 desc_dma = ((u32) ring->descs_dma) + i * AG71XX_DESC_SIZE;
len += snprintf(buf + len, buflen - len,
"%3d %c%c%c %08x %08x %08x %08x %c\n",
i,
(i == curr) ? 'C' : ' ',
(i == dirty) ? 'D' : ' ',
(desc_hw == desc_dma) ? 'H' : ' ',
desc_dma,
desc->next,
desc->data,
desc->ctrl,
(desc->ctrl & DESC_EMPTY) ? 'E' : '*');
}
spin_unlock_irqrestore(&ag->lock, flags);
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
kfree(buf);
return ret;
}
static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ag71xx *ag = file->private_data;
return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,
AG71XX_REG_TX_DESC);
}
static const struct file_operations ag71xx_fops_tx_ring = {
.open = ag71xx_debugfs_generic_open,
.read = read_file_tx_ring,
.owner = THIS_MODULE
};
static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ag71xx *ag = file->private_data;
return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring,
AG71XX_REG_RX_DESC);
}
static const struct file_operations ag71xx_fops_rx_ring = {
.open = ag71xx_debugfs_generic_open,
.read = read_file_rx_ring,
.owner = THIS_MODULE
};
void ag71xx_debugfs_exit(struct ag71xx *ag)
{
debugfs_remove_recursive(ag->debug.debugfs_dir);
}
int ag71xx_debugfs_init(struct ag71xx *ag)
{
struct device *dev = &ag->pdev->dev;
ag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev),
ag71xx_debugfs_root);
if (!ag->debug.debugfs_dir) {
dev_err(dev, "unable to create debugfs directory\n");
return -ENOENT;
}
debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir,
ag, &ag71xx_fops_int_stats);
debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir,
ag, &ag71xx_fops_napi_stats);
debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir,
ag, &ag71xx_fops_tx_ring);
debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir,
ag, &ag71xx_fops_rx_ring);
return 0;
}
int ag71xx_debugfs_root_init(void)
{
if (ag71xx_debugfs_root)
return -EBUSY;
ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
if (!ag71xx_debugfs_root)
return -ENOENT;
return 0;
}
void ag71xx_debugfs_root_exit(void)
{
debugfs_remove(ag71xx_debugfs_root);
ag71xx_debugfs_root = NULL;
}

194
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c Normal file
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@@ -0,0 +1,194 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include "ag71xx.h"
struct ag71xx_statistic {
unsigned short offset;
u32 mask;
const char name[ETH_GSTRING_LEN];
};
static const struct ag71xx_statistic ag71xx_statistics[] = {
{ 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", },
{ 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", },
{ 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", },
{ 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", },
{ 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", },
{ 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", },
{ 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", },
{ 0x009C, GENMASK(23, 0), "Rx Byte", },
{ 0x00A0, GENMASK(17, 0), "Rx Packet", },
{ 0x00A4, GENMASK(11, 0), "Rx FCS Error", },
{ 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", },
{ 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", },
{ 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", },
{ 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", },
{ 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", },
{ 0x00BC, GENMASK(11, 0), "Rx Alignment Error", },
{ 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", },
{ 0x00C4, GENMASK(11, 0), "Rx Code Error", },
{ 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", },
{ 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", },
{ 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", },
{ 0x00D4, GENMASK(11, 0), "Rx Fragments", },
{ 0x00D8, GENMASK(11, 0), "Rx Jabber", },
{ 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", },
{ 0x00E0, GENMASK(23, 0), "Tx Byte", },
{ 0x00E4, GENMASK(17, 0), "Tx Packet", },
{ 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", },
{ 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", },
{ 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", },
{ 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", },
{ 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", },
{ 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", },
{ 0x0100, GENMASK(11, 0), "Tx Multiple Collision", },
{ 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", },
{ 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", },
{ 0x010C, GENMASK(12, 0), "Tx Total Collision", },
{ 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", },
{ 0x0114, GENMASK(11, 0), "Tx Drop Frame", },
{ 0x0118, GENMASK(11, 0), "Tx Jabber Frame", },
{ 0x011C, GENMASK(11, 0), "Tx FCS Error", },
{ 0x0120, GENMASK(11, 0), "Tx Control Frame", },
{ 0x0124, GENMASK(11, 0), "Tx Oversize Frame", },
{ 0x0128, GENMASK(11, 0), "Tx Undersize Frame", },
{ 0x012C, GENMASK(11, 0), "Tx Fragment", },
};
static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev)
{
struct ag71xx *ag = netdev_priv(dev);
return ag->msg_enable;
}
static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level)
{
struct ag71xx *ag = netdev_priv(dev);
ag->msg_enable = msg_level;
}
static void ag71xx_ethtool_get_ringparam(struct net_device *dev,
struct ethtool_ringparam *er)
{
struct ag71xx *ag = netdev_priv(dev);
er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX;
er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX;
er->rx_mini_max_pending = 0;
er->rx_jumbo_max_pending = 0;
er->tx_pending = BIT(ag->tx_ring.order);
er->rx_pending = BIT(ag->rx_ring.order);
er->rx_mini_pending = 0;
er->rx_jumbo_pending = 0;
if (ag->tx_ring.desc_split)
er->tx_pending /= AG71XX_TX_RING_DS_PER_PKT;
}
static int ag71xx_ethtool_set_ringparam(struct net_device *dev,
struct ethtool_ringparam *er)
{
struct ag71xx *ag = netdev_priv(dev);
unsigned tx_size;
unsigned rx_size;
int err = 0;
if (er->rx_mini_pending != 0||
er->rx_jumbo_pending != 0 ||
er->rx_pending == 0 ||
er->tx_pending == 0)
return -EINVAL;
tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ?
er->tx_pending : AG71XX_TX_RING_SIZE_MAX;
rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ?
er->rx_pending : AG71XX_RX_RING_SIZE_MAX;
if (netif_running(dev)) {
err = dev->netdev_ops->ndo_stop(dev);
if (err)
return err;
}
if (ag->tx_ring.desc_split)
tx_size *= AG71XX_TX_RING_DS_PER_PKT;
ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
ag->rx_ring.order = ag71xx_ring_size_order(rx_size);
if (netif_running(dev))
err = dev->netdev_ops->ndo_open(dev);
return err;
}
static int ag71xx_ethtool_nway_reset(struct net_device *dev)
{
struct ag71xx *ag = netdev_priv(dev);
struct phy_device *phydev = ag->phy_dev;
if (!phydev)
return -ENODEV;
return genphy_restart_aneg(phydev);
}
static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset,
u8 *data)
{
if (sset == ETH_SS_STATS) {
int i;
for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)
memcpy(data + i * ETH_GSTRING_LEN,
ag71xx_statistics[i].name, ETH_GSTRING_LEN);
}
}
static void ag71xx_ethtool_get_stats(struct net_device *ndev,
struct ethtool_stats *stats, u64 *data)
{
struct ag71xx *ag = netdev_priv(ndev);
int i;
for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)
*data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset)
& ag71xx_statistics[i].mask;
}
static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset)
{
if (sset == ETH_SS_STATS)
return ARRAY_SIZE(ag71xx_statistics);
return -EOPNOTSUPP;
}
struct ethtool_ops ag71xx_ethtool_ops = {
.get_msglevel = ag71xx_ethtool_get_msglevel,
.set_msglevel = ag71xx_ethtool_set_msglevel,
.get_ringparam = ag71xx_ethtool_get_ringparam,
.set_ringparam = ag71xx_ethtool_set_ringparam,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.set_link_ksettings = phy_ethtool_set_link_ksettings,
.get_link = ethtool_op_get_link,
.get_ts_info = ethtool_op_get_ts_info,
.nway_reset = ag71xx_ethtool_nway_reset,
.get_strings = ag71xx_ethtool_get_strings,
.get_ethtool_stats = ag71xx_ethtool_get_stats,
.get_sset_count = ag71xx_ethtool_get_sset_count,
};

135
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c Normal file
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/*
* Atheros AR71xx built-in ethernet mac driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/sizes.h>
#include <linux/of_address.h>
#include "ag71xx.h"
static void ag71xx_of_set(struct device_node *np, const char *prop,
u32 *reg, u32 shift, u32 mask)
{
u32 val;
if (of_property_read_u32(np, prop, &val))
return;
*reg &= ~(mask << shift);
*reg |= ((val & mask) << shift);
}
static void ag71xx_of_bit(struct device_node *np, const char *prop,
u32 *reg, u32 mask)
{
u32 val;
if (of_property_read_u32(np, prop, &val))
return;
if (val)
*reg |= mask;
else
*reg &= ~mask;
}
static void ag71xx_setup_gmac_933x(struct device_node *np, void __iomem *base)
{
u32 val = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
ag71xx_of_bit(np, "switch-phy-swap", &val, AR933X_ETH_CFG_SW_PHY_SWAP);
ag71xx_of_bit(np, "switch-phy-addr-swap", &val,
AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
__raw_writel(val, base + AR933X_GMAC_REG_ETH_CFG);
}
static void ag71xx_setup_gmac_934x(struct device_node *np, void __iomem *base)
{
u32 val = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
ag71xx_of_bit(np, "rgmii-gmac0", &val, AR934X_ETH_CFG_RGMII_GMAC0);
ag71xx_of_bit(np, "mii-gmac0", &val, AR934X_ETH_CFG_MII_GMAC0);
ag71xx_of_bit(np, "mii-gmac0-slave", &val, AR934X_ETH_CFG_MII_GMAC0_SLAVE);
ag71xx_of_bit(np, "gmii-gmac0", &val, AR934X_ETH_CFG_GMII_GMAC0);
ag71xx_of_bit(np, "switch-phy-swap", &val, AR934X_ETH_CFG_SW_PHY_SWAP);
ag71xx_of_bit(np, "switch-only-mode", &val,
AR934X_ETH_CFG_SW_ONLY_MODE);
ag71xx_of_set(np, "rxdv-delay", &val,
AR934X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "rxd-delay", &val,
AR934X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "txd-delay", &val,
AR934X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "txen-delay", &val,
AR934X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);
__raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);
}
static void ag71xx_setup_gmac_955x(struct device_node *np, void __iomem *base)
{
u32 val = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
ag71xx_of_bit(np, "rgmii-enabled", &val, QCA955X_ETH_CFG_RGMII_EN);
ag71xx_of_bit(np, "ge0-sgmii", &val, QCA955X_ETH_CFG_GE0_SGMII);
ag71xx_of_set(np, "txen-delay", &val, QCA955X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "txd-delay", &val, QCA955X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "rxdv-delay", &val, QCA955X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);
ag71xx_of_set(np, "rxd-delay", &val, QCA955X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);
__raw_writel(val, base + QCA955X_GMAC_REG_ETH_CFG);
}
static void ag71xx_setup_gmac_956x(struct device_node *np, void __iomem *base)
{
u32 val = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
ag71xx_of_bit(np, "switch-phy-swap", &val, QCA956X_ETH_CFG_SW_PHY_SWAP);
ag71xx_of_bit(np, "switch-phy-addr-swap", &val,
QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);
__raw_writel(val, base + QCA956X_GMAC_REG_ETH_CFG);
}
int ag71xx_setup_gmac(struct device_node *np)
{
struct device_node *np_dev;
void __iomem *base;
int err = 0;
np = of_get_child_by_name(np, "gmac-config");
if (!np)
return 0;
np_dev = of_parse_phandle(np, "device", 0);
if (!np_dev)
goto out;
base = of_iomap(np_dev, 0);
if (!base) {
pr_err("%pOF: can't map GMAC registers\n", np_dev);
err = -ENOMEM;
goto err_iomap;
}
if (of_device_is_compatible(np_dev, "qca,ar9330-gmac"))
ag71xx_setup_gmac_933x(np, base);
else if (of_device_is_compatible(np_dev, "qca,ar9340-gmac"))
ag71xx_setup_gmac_934x(np, base);
else if (of_device_is_compatible(np_dev, "qca,qca9550-gmac"))
ag71xx_setup_gmac_955x(np, base);
else if (of_device_is_compatible(np_dev, "qca,qca9560-gmac"))
ag71xx_setup_gmac_956x(np, base);
iounmap(base);
err_iomap:
of_node_put(np_dev);
out:
of_node_put(np);
return err;
}

1830
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c Normal file
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File diff suppressed because it is too large Load Diff

254
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c Normal file
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@@ -0,0 +1,254 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/of_mdio.h>
#include "ag71xx.h"
#define AG71XX_MDIO_RETRY 1000
#define AG71XX_MDIO_DELAY 5
static int bus_count;
static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am)
{
int i;
for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
u32 busy;
udelay(AG71XX_MDIO_DELAY);
regmap_read(am->mii_regmap, AG71XX_REG_MII_IND, &busy);
if (!busy)
return 0;
udelay(AG71XX_MDIO_DELAY);
}
pr_err("%s: MDIO operation timed out\n", am->mii_bus->name);
return -ETIMEDOUT;
}
static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
{
struct ag71xx_mdio *am = bus->priv;
int err;
int ret;
err = ag71xx_mdio_wait_busy(am);
if (err)
return 0xffff;
regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
regmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,
((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_READ);
err = ag71xx_mdio_wait_busy(am);
if (err)
return 0xffff;
regmap_read(am->mii_regmap, AG71XX_REG_MII_STATUS, &ret);
ret &= 0xffff;
regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
return ret;
}
static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
{
struct ag71xx_mdio *am = bus->priv;
DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
regmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,
((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
regmap_write(am->mii_regmap, AG71XX_REG_MII_CTRL, val);
ag71xx_mdio_wait_busy(am);
return 0;
}
static const u32 ar71xx_mdio_div_table[] = {
4, 4, 6, 8, 10, 14, 20, 28,
};
static const u32 ar7240_mdio_div_table[] = {
2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
};
static const u32 ar933x_mdio_div_table[] = {
4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
};
static int ag71xx_mdio_get_divider(struct device_node *np, u32 *div)
{
struct clk *ref_clk = of_clk_get(np, 0);
unsigned long ref_clock;
u32 mdio_clock;
const u32 *table;
int ndivs, i;
if (IS_ERR(ref_clk))
return -EINVAL;
ref_clock = clk_get_rate(ref_clk);
clk_put(ref_clk);
if(of_property_read_u32(np, "qca,mdio-max-frequency", &mdio_clock)) {
if (of_property_read_bool(np, "builtin-switch"))
mdio_clock = 5000000;
else
mdio_clock = 2000000;
}
if (of_device_is_compatible(np, "qca,ar9330-mdio") ||
of_device_is_compatible(np, "qca,ar9340-mdio")) {
table = ar933x_mdio_div_table;
ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
} else if (of_device_is_compatible(np, "qca,ar7240-mdio")) {
table = ar7240_mdio_div_table;
ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
} else {
table = ar71xx_mdio_div_table;
ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
}
for (i = 0; i < ndivs; i++) {
unsigned long t;
t = ref_clock / table[i];
if (t <= mdio_clock) {
*div = i;
return 0;
}
}
return -ENOENT;
}
static int ag71xx_mdio_reset(struct mii_bus *bus)
{
struct device_node *np = bus->dev.of_node;
struct ag71xx_mdio *am = bus->priv;
bool builtin_switch;
u32 t;
builtin_switch = of_property_read_bool(np, "builtin-switch");
if (ag71xx_mdio_get_divider(np, &t)) {
if (of_device_is_compatible(np, "qca,ar9340-mdio"))
t = MII_CFG_CLK_DIV_58;
else if (builtin_switch)
t = MII_CFG_CLK_DIV_10;
else
t = MII_CFG_CLK_DIV_28;
}
regmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
udelay(100);
regmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t);
udelay(100);
return 0;
}
static int ag71xx_mdio_probe(struct platform_device *pdev)
{
struct device *amdev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
struct ag71xx_mdio *am;
struct mii_bus *mii_bus;
bool builtin_switch;
int i, err;
am = devm_kzalloc(amdev, sizeof(*am), GFP_KERNEL);
if (!am)
return -ENOMEM;
am->mii_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
if (IS_ERR(am->mii_regmap))
return PTR_ERR(am->mii_regmap);
mii_bus = devm_mdiobus_alloc(amdev);
if (!mii_bus)
return -ENOMEM;
am->mdio_reset = devm_reset_control_get_exclusive(amdev, "mdio");
builtin_switch = of_property_read_bool(np, "builtin-switch");
mii_bus->name = "ag71xx_mdio";
mii_bus->read = ag71xx_mdio_mii_read;
mii_bus->write = ag71xx_mdio_mii_write;
mii_bus->reset = ag71xx_mdio_reset;
mii_bus->priv = am;
mii_bus->parent = amdev;
snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, bus_count++);
if (!builtin_switch &&
of_property_read_u32(np, "phy-mask", &mii_bus->phy_mask))
mii_bus->phy_mask = 0;
for (i = 0; i < PHY_MAX_ADDR; i++)
mii_bus->irq[i] = PHY_POLL;
if (!IS_ERR(am->mdio_reset)) {
reset_control_assert(am->mdio_reset);
msleep(100);
reset_control_deassert(am->mdio_reset);
msleep(200);
}
err = of_mdiobus_register(mii_bus, np);
if (err)
return err;
am->mii_bus = mii_bus;
platform_set_drvdata(pdev, am);
return 0;
}
static int ag71xx_mdio_remove(struct platform_device *pdev)
{
struct ag71xx_mdio *am = platform_get_drvdata(pdev);
mdiobus_unregister(am->mii_bus);
return 0;
}
static const struct of_device_id ag71xx_mdio_match[] = {
{ .compatible = "qca,ar7240-mdio" },
{ .compatible = "qca,ar9330-mdio" },
{ .compatible = "qca,ar9340-mdio" },
{ .compatible = "qca,ath79-mdio" },
{}
};
static struct platform_driver ag71xx_mdio_driver = {
.probe = ag71xx_mdio_probe,
.remove = ag71xx_mdio_remove,
.driver = {
.name = "ag71xx-mdio",
.of_match_table = ag71xx_mdio_match,
}
};
module_platform_driver(ag71xx_mdio_driver);
MODULE_LICENSE("GPL");

92
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c Normal file
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@@ -0,0 +1,92 @@
/*
* Atheros AR71xx built-in ethernet mac driver
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Based on Atheros' AG7100 driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/of_mdio.h>
#include "ag71xx.h"
static void ag71xx_phy_link_adjust(struct net_device *dev)
{
struct ag71xx *ag = netdev_priv(dev);
struct phy_device *phydev = ag->phy_dev;
unsigned long flags;
int status_change = 0;
spin_lock_irqsave(&ag->lock, flags);
if (phydev->link) {
if (ag->duplex != phydev->duplex
|| ag->speed != phydev->speed) {
status_change = 1;
}
}
if (phydev->link != ag->link)
status_change = 1;
ag->link = phydev->link;
ag->duplex = phydev->duplex;
ag->speed = phydev->speed;
if (status_change)
ag71xx_link_adjust(ag);
spin_unlock_irqrestore(&ag->lock, flags);
}
int ag71xx_phy_connect(struct ag71xx *ag)
{
struct device_node *np = ag->pdev->dev.of_node;
struct device_node *phy_node;
int ret;
if (of_phy_is_fixed_link(np)) {
ret = of_phy_register_fixed_link(np);
if (ret < 0) {
dev_err(&ag->pdev->dev,
"Failed to register fixed PHY link: %d\n", ret);
return ret;
}
phy_node = of_node_get(np);
} else {
phy_node = of_parse_phandle(np, "phy-handle", 0);
}
if (!phy_node) {
dev_err(&ag->pdev->dev,
"Could not find valid phy node\n");
return -ENODEV;
}
ag->phy_dev = of_phy_connect(ag->dev, phy_node, ag71xx_phy_link_adjust,
0, ag->phy_if_mode);
of_node_put(phy_node);
if (!ag->phy_dev) {
dev_err(&ag->pdev->dev,
"Could not connect to PHY device. Deferring probe.\n");
return -EPROBE_DEFER;
}
dev_info(&ag->pdev->dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
phydev_name(ag->phy_dev),
ag->phy_dev->phy_id, ag->phy_dev->drv->name);
return 0;
}
void ag71xx_phy_disconnect(struct ag71xx *ag)
{
phy_disconnect(ag->phy_dev);
}

25
target/linux/ath79/files/include/mfd/rb4xx-cpld.h Normal file
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@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* CPLD driver for the MikroTik RouterBoard 4xx series
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>
*
* This file was based on the driver for Linux 2.6.22 published by
* MikroTik for their RouterBoard 4xx series devices.
*/
#include <linux/spi/spi.h>
struct rb4xx_cpld {
struct spi_device *spi;
int (*write_nand)(struct rb4xx_cpld *self, const void *tx_buf,
unsigned int len);
int (*read_nand)(struct rb4xx_cpld *self, void *rx_buf,
unsigned int len);
int (*gpio_set_0_7)(struct rb4xx_cpld *self, u8 values);
int (*gpio_set_8)(struct rb4xx_cpld *self, u8 value);
};