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domenico
2025-06-24 13:14:22 +02:00
commit 4002f145fc
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24
target/linux/ipq40xx/Makefile Normal file
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include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=ipq40xx
BOARDNAME:=Qualcomm Atheros IPQ40XX
FEATURES:=squashfs fpu ramdisk nand
CPU_TYPE:=cortex-a7
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic mikrotik
KERNEL_PATCHVER:=5.4
KERNEL_TESTING_PATCHVER:=5.10
KERNELNAME:=zImage Image dtbs
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb-dwc3-qcom \
kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
kmod-ath10k-ct wpad-basic-wolfssl \
kmod-usb3 kmod-usb-dwc3 ath10k-firmware-qca4019-ct \
uboot-envtools
$(eval $(call BuildTarget))

80
target/linux/ipq40xx/base-files/etc/board.d/01_leds Normal file
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#
# Copyright (C) 2015 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
alfa-network,ap120c-ac)
ucidef_set_led_netdev "wan" "WAN" "amber:wan" "eth1"
;;
asus,rt-ac58u)
ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1"
ucidef_set_led_switch "lan" "LAN" "blue:lan" "switch0" "0x1e"
;;
avm,fritzbox-4040)
ucidef_set_led_wlan "wlan" "WLAN" "green:wlan" "phy0tpt" "phy1tpt"
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1"
ucidef_set_led_switch "lan" "LAN" "green:lan" "switch0" "0x1e"
;;
avm,fritzbox-7530 |\
glinet,gl-b1300)
ucidef_set_led_wlan "wlan" "WLAN" "green:wlan" "phy0tpt"
;;
edgecore,oap100)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "blue:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "blue:wlan5g" "phy1tpt"
;;
engenius,eap1300)
ucidef_set_led_netdev "lan" "LAN" "blue:lan" "eth0"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "blue:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "yellow:wlan5g" "phy1tpt"
ucidef_set_led_default "mesh" "MESH" "blue:mesh" "0"
;;
engenius,eap2200)
ucidef_set_led_netdev "lan1" "LAN1" "blue:lan1" "eth0"
ucidef_set_led_netdev "lan2" "LAN2" "blue:lan2" "eth1"
;;
engenius,ens620ext)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy1tpt"
ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth0"
ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth1"
;;
mikrotik,sxtsq-5-ac)
ucidef_set_rssimon "wlan0" "200000" "1"
ucidef_set_led_rssi "rssilow" "rssilow" "green:rssilow" "wlan0" "1" "100"
ucidef_set_led_rssi "rssimediumlow" "rssimediumlow" "green:rssimediumlow" "wlan0" "21" "100"
ucidef_set_led_rssi "rssimedium" "rssimedium" "green:rssimedium" "wlan0" "41" "100"
ucidef_set_led_rssi "rssimediumhigh" "rssimediumhigh" "green:rssimediumhigh" "wlan0" "61" "100"
ucidef_set_led_rssi "rssihigh" "rssihigh" "green:rssihigh" "wlan0" "81" "100"
;;
mobipromo,cm520-79f)
ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1"
ucidef_set_led_switch "lan1" "LAN1" "blue:lan1" "switch0" "0x10"
ucidef_set_led_switch "lan2" "LAN2" "blue:lan2" "switch0" "0x08"
;;
netgear,ex6100v2 |\
netgear,ex6150v2)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:router" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:client" "phy1tpt"
;;
qxwlan,e2600ac-c1 |\
qxwlan,e2600ac-c2)
ucidef_set_led_wlan "wlan2g" "WLAN0" "green:wlan0" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN1" "green:wlan1" "phy1tpt"
;;
zyxel,nbg6617 |\
zyxel,wre6606)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy1tpt"
;;
esac
board_config_flush
exit 0

197
target/linux/ipq40xx/base-files/etc/board.d/02_network Normal file
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#
# Copyright (c) 2015 The Linux Foundation. All rights reserved.
# Copyright (c) 2011-2015 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
ipq40xx_setup_interfaces()
{
local board="$1"
case "$board" in
8dev,habanero-dvk|\
8dev,jalapeno|\
alfa-network,ap120c-ac|\
engenius,emr3500|\
engenius,ens620ext|\
luma,wrtq-329acn|\
netgear,wac510|\
plasmacloud,pa1200|\
plasmacloud,pa2200)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
aruba,ap-303|\
aruba,ap-365|\
avm,fritzrepeater-1200|\
dlink,dap-2610 |\
engenius,eap1300|\
engenius,emd1|\
meraki,mr33|\
mikrotik,sxtsq-5-ac|\
netgear,ex6100v2|\
netgear,ex6150v2|\
zyxel,wre6606)
ucidef_set_interface_lan "eth0"
;;
aruba,ap-303h)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "0u@eth1" "5:wan"
;;
asus,map-ac2200|\
cilab,meshpoint-one|\
edgecore,ecw5211|\
edgecore,oap100|\
openmesh,a42|\
openmesh,a62)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
asus,rt-ac58u|\
mikrotik,hap-ac2|\
zyxel,nbg6617)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"
;;
avm,fritzbox-4040|\
linksys,ea6350v3|\
linksys,ea8300|\
linksys,mr8300)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
;;
avm,fritzbox-7530)
ucidef_add_switch "switch0" \
"0u@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"
;;
avm,fritzrepeater-3000)
ucidef_add_switch "switch0" \
"0u@eth0" "4:lan:1" "5:lan:2"
;;
compex,wpj419|\
compex,wpj428|\
engenius,eap2200)
ucidef_set_interface_lan "eth0 eth1"
;;
buffalo,wtr-m2133hp)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "2:lan:3" "3:lan:2" "4:lan:1"
;;
cellc,rtl30vw)
ucidef_set_interface_lan "eth0"
ucidef_add_switch "switch0" \
"0u@eth0" "3:lan" "4:lan"
;;
devolo,magic-2-wifi-next)
ucidef_set_interface_lan "eth0 eth1 eth2"
;;
ezviz,cs-w3-wd1200g-eup)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "2:lan:3" "3:lan:2" "4:lan:1" "0u@eth1" "5:wan"
;;
glinet,gl-ap1300 |\
glinet,gl-b1300 |\
glinet,gl-s1300)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "3:lan" "4:lan"
;;
mobipromo,cm520-79f)
ucidef_add_switch "switch0" \
"0u@eth0" "3:lan:2" "4:lan:1"
ucidef_set_interface_wan "eth1"
;;
qxwlan,e2600ac-c1 |\
qxwlan,e2600ac-c2)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "3:lan" "4:lan" "0u@eth1" "5:wan"
;;
unielec,u4019-32m)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "0u@eth1" "5:wan"
;;
*)
echo "Unsupported hardware. Network interfaces not initialized"
;;
esac
}
ipq40xx_setup_macs()
{
local board="$1"
local lan_mac=""
local wan_mac=""
local label_mac=""
case "$board" in
8dev,habanero-dvk)
label_mac=$(mtd_get_mac_binary "ART" 0x1006)
;;
asus,rt-ac58u)
CI_UBIPART=UBI_DEV
wan_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)
lan_mac=$(mtd_get_mac_binary_ubi Factory 0x5006)
label_mac=$wan_mac
;;
cilab,meshpoint-one)
label_mac=$(mtd_get_mac_binary "ART" 0x1006)
;;
devolo,magic-2-wifi-next)
lan_mac=$(mtd_get_mac_ascii APPSBLENV MacAddress0)
label_mac=$lan_mac
;;
dlink,dap-2610)
lan_mac=$(mtd_get_mac_ascii bdcfg lanmac)
label_mac=$lan_mac
;;
engenius,eap2200|\
engenius,emd1)
lan_mac=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
label_mac=$lan_mac
;;
engenius,emr3500)
wan_mac=$(mtd_get_mac_ascii 0:APPSBLENV wanaddr)
lan_mac=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
label_mac=$wan_mac
;;
engenius,ens620ext)
wan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
ezviz,cs-w3-wd1200g-eup)
label_mac=$(mtd_get_mac_binary "ART" 0x6)
;;
linksys,ea6350v3)
wan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
mikrotik,hap-ac2)
wan_mac=$(cat /sys/firmware/mikrotik/hard_config/mac_base)
lan_mac=$(macaddr_add $wan_mac 1)
label_mac="$wan_mac"
;;
mikrotik,sxtsq-5-ac)
lan_mac=$(cat /sys/firmware/mikrotik/hard_config/mac_base)
label_mac="$lan_mac"
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
}
board_config_update
board=$(board_name)
ipq40xx_setup_interfaces $board
ipq40xx_setup_macs $board
board_config_flush
exit 0

25
target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches Normal file
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. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
cellc,rtl30vw)
ucidef_add_gpio_switch "w_disable" "W_DISABLE mPCIE pin" "398" "1"
ucidef_add_gpio_switch "pmd_resin_n" "PMD_RESIN_N pin" "399" "1"
ucidef_add_gpio_switch "mcpie_vcc" "LTE power" "400" "0"
ucidef_add_gpio_switch "usb_vcc" "USB power" "401" "0"
;;
cilab,meshpoint-one)
ucidef_add_gpio_switch "poe_passtrough" "POE passtrough enable" "413" "1"
;;
compex,wpj428)
ucidef_add_gpio_switch "sim_card_select" "SIM card select" "3" "0"
;;
esac
board_config_flush
exit 0

281
target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata Normal file
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#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:01:00.0.bin")
case "$board" in
meraki,mr33)
caldata_extract_ubi "ART" 0x9000 0x844
caldata_valid "4408" || caldata_extract "ART" 0x9000 0x844
ath10k_patch_mac $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 0x66) 1)
;;
esac
;;
"ath10k/pre-cal-pci-0000:01:00.0.bin")
case "$board" in
asus,map-ac2200)
caldata_extract_ubi "Factory" 0x9000 0x2f20
ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
;;
avm,fritzrepeater-3000)
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1")
;;
buffalo,wtr-m2133hp)
caldata_extract "ART" 0x9000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary ORGDATA 0x32)
;;
engenius,eap2200 |\
openmesh,a62 |\
plasmacloud,pa2200)
caldata_extract "0:ART" 0x9000 0x2f20
;;
linksys,ea8300 |\
linksys,mr8300)
caldata_extract "ART" 0x9000 0x2f20
# OEM assigns 4 sequential MACs
ath10k_patch_mac $(macaddr_setbit_la $(macaddr_add "$(cat /sys/class/net/eth0/address)" 4))
;;
esac
;;
"ath10k/pre-cal-ahb-a000000.wifi.bin")
case "$board" in
8dev,habanero-dvk |\
8dev,jalapeno |\
alfa-network,ap120c-ac |\
cilab,meshpoint-one |\
ezviz,cs-w3-wd1200g-eup |\
glinet,gl-ap1300 |\
glinet,gl-b1300 |\
glinet,gl-s1300 |\
linksys,ea6350v3 |\
mobipromo,cm520-79f |\
qcom,ap-dk01.1-c1)
caldata_extract "ART" 0x1000 0x2f20
;;
aruba,ap-303 |\
aruba,ap-303h |\
aruba,ap-365)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary mfginfo 0x1D)
;;
asus,map-ac2200)
caldata_extract_ubi "Factory" 0x1000 0x2f20
;;
asus,rt-ac58u)
CI_UBIPART=UBI_DEV
caldata_extract_ubi "Factory" 0x1000 0x2f20
;;
avm,fritzbox-4040)
/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
;;
avm,fritzbox-7530 |\
avm,fritzrepeater-1200 |\
avm,fritzrepeater-3000)
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1")
;;
buffalo,wtr-m2133hp)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary ORGDATA 0x26)
;;
cellc,rtl30vw |\
compex,wpj419 |\
compex,wpj428 |\
edgecore,ecw5211 |\
edgecore,oap100 |\
engenius,eap1300 |\
engenius,eap2200 |\
luma,wrtq-329acn|\
openmesh,a42 |\
openmesh,a62 |\
plasmacloud,pa1200 |\
plasmacloud,pa2200 |\
qxwlan,e2600ac-c1 |\
qxwlan,e2600ac-c2 |\
unielec,u4019-32m)
caldata_extract "0:ART" 0x1000 0x2f20
;;
devolo,magic-2-wifi-next)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii APPSBLENV WiFiMacAddress0)
;;
dlink,dap-2610)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac)
;;
engenius,emd1)
caldata_extract "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV wlanaddr)
;;
engenius,emr3500)
caldata_extract "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
;;
engenius,ens620ext)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2)
;;
linksys,ea8300 |\
linksys,mr8300)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 2)
;;
meraki,mr33)
caldata_extract_ubi "ART" 0x1000 0x2f20
caldata_valid "202f" || caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 0x66) 2)
;;
mikrotik,hap-ac2)
wlan_data="/sys/firmware/mikrotik/hard_config/wlan_data"
( [ -f "$wlan_data" ] && caldata_sysfsload_from_file "$wlan_data" 0x0 0x2f20 ) || \
( [ -d "$wlan_data" ] && caldata_sysfsload_from_file "$wlan_data/data_0" 0x0 0x2f20 )
;;
netgear,ex6100v2 |\
netgear,ex6150v2)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary dnidata 0x0)
;;
netgear,wac510)
caldata_extract "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary "0:MANUDATA" 0x6)
;;
zyxel,nbg6617 |\
zyxel,wre6606)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2)
;;
esac
;;
"ath10k/pre-cal-ahb-a800000.wifi.bin")
case "$board" in
8dev,habanero-dvk |\
8dev,jalapeno |\
alfa-network,ap120c-ac |\
cilab,meshpoint-one |\
ezviz,cs-w3-wd1200g-eup |\
glinet,gl-ap1300 |\
glinet,gl-b1300 |\
glinet,gl-s1300 |\
linksys,ea6350v3 |\
mobipromo,cm520-79f |\
qcom,ap-dk01.1-c1)
caldata_extract "ART" 0x5000 0x2f20
;;
aruba,ap-303 |\
aruba,ap-303h |\
aruba,ap-365)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary mfginfo 0x1D) 1)
;;
asus,map-ac2200)
caldata_extract_ubi "Factory" 0x5000 0x2f20
;;
asus,rt-ac58u)
CI_UBIPART=UBI_DEV
caldata_extract_ubi "Factory" 0x5000 0x2f20
;;
avm,fritzbox-4040)
/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
;;
avm,fritzbox-7530 |\
avm,fritzrepeater-1200 |\
avm,fritzrepeater-3000)
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader0") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1") || \
/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader1")
;;
buffalo,wtr-m2133hp)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary ORGDATA 0x2c)
;;
cellc,rtl30vw |\
compex,wpj419 |\
compex,wpj428 |\
edgecore,ecw5211 |\
edgecore,oap100 |\
engenius,eap1300 |\
engenius,eap2200 |\
luma,wrtq-329acn|\
openmesh,a42 |\
openmesh,a62 |\
plasmacloud,pa1200 |\
plasmacloud,pa2200 |\
qxwlan,e2600ac-c1 |\
qxwlan,e2600ac-c2 |\
unielec,u4019-32m)
caldata_extract "0:ART" 0x5000 0x2f20
;;
devolo,magic-2-wifi-next)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii APPSBLENV WiFiMacAddress1)
;;
dlink,dap-2610)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac_a)
;;
engenius,emd1)
caldata_extract "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV wlanaddr) 1)
;;
engenius,emr3500)
caldata_extract "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV ethaddr) 1)
;;
engenius,ens620ext)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 3)
;;
linksys,ea8300 |\
linksys,mr8300)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 3)
;;
meraki,mr33)
caldata_extract_ubi "ART" 0x5000 0x2f20
caldata_valid "202f" || caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 0x66) 3)
;;
mikrotik,hap-ac2|\
mikrotik,sxtsq-5-ac)
wlan_data="/sys/firmware/mikrotik/hard_config/wlan_data"
( [ -f "$wlan_data" ] && caldata_sysfsload_from_file "$wlan_data" 0x8000 0x2f20 ) || \
( [ -d "$wlan_data" ] && caldata_sysfsload_from_file "$wlan_data/data_2" 0x0 0x2f20 )
;;
netgear,ex6100v2 |\
netgear,ex6150v2)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary dnidata 0xc)
;;
netgear,wac510)
caldata_extract "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary "0:MANUDATA" 0x6) 16)
;;
zyxel,nbg6617 |\
zyxel,wre6606)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -1)
;;
esac
;;
*)
exit 1
;;
esac

20
target/linux/ipq40xx/base-files/etc/init.d/bootcount Executable file
View File

@@ -0,0 +1,20 @@
#!/bin/sh /etc/rc.common
START=99
boot() {
case $(board_name) in
alfa-network,ap120c-ac)
[ -n "$(fw_printenv bootcount changed 2>/dev/null)" ] &&\
echo -e "bootcount\nchanged\n" | /usr/sbin/fw_setenv -s -
;;
linksys,ea6350v3|\
linksys,ea8300|\
linksys,mr8300)
mtd resetbc s_env || true
;;
netgear,wac510)
fw_setenv boot_cnt=0
;;
esac
}

5
target/linux/ipq40xx/base-files/etc/inittab Normal file
View File

@@ -0,0 +1,5 @@
# Copyright (c) 2013 The Linux Foundation. All rights reserved.
::sysinit:/etc/init.d/rcS S boot
::shutdown:/etc/init.d/rcS K shutdown
ttyMSM0::askfirst:/usr/libexec/login.sh
ttyMSM1::askfirst:/usr/libexec/login.sh

19
target/linux/ipq40xx/base-files/etc/uci-defaults/04_led_migration Normal file
View File

@@ -0,0 +1,19 @@
. /lib/functions/migrations.sh
board=$(board_name)
case "$board" in
engenius,emr3500)
migrate_leds "emr3500:="
;;
engenius,ens620ext|\
zyxel,nbg6617)
migrate_leds ":wlan2G=:wlan2g" ":wlan5G=:wlan5g"
;;
esac
remove_devicename_leds
migrations_apply system
exit 0

36
target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh Normal file
View File

@@ -0,0 +1,36 @@
. /lib/functions.sh
preinit_set_mac_address() {
case $(board_name) in
asus,map-ac2200)
base_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)
ip link set dev eth0 address $(macaddr_add "$base_mac" 1)
ip link set dev eth1 address $(macaddr_add "$base_mac" 3)
;;
ezviz,cs-w3-wd1200g-eup)
ip link set dev eth0 address $(mtd_get_mac_binary "ART" 0x6)
ip link set dev eth1 address $(mtd_get_mac_binary "ART" 0x0)
;;
engenius,eap2200)
base_mac=$(cat /sys/class/net/eth0/address)
ip link set dev eth1 address $(macaddr_add "$base_mac" 1)
;;
linksys,ea8300|\
linksys,mr8300)
base_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
ip link set dev eth0 address "$base_mac"
ip link set dev eth1 address $(macaddr_add "$base_mac" 1)
;;
meraki,mr33)
mac_lan=$(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 0x66)
[ -n "$mac_lan" ] && ip link set dev eth0 address "$mac_lan"
;;
zyxel,nbg6617)
base_mac=$(cat /sys/class/net/eth0/address)
ip link set dev eth0 address $(macaddr_add "$base_mac" 2)
ip link set dev eth1 address $(macaddr_add "$base_mac" 3)
;;
esac
}
boot_hook_add preinit_main preinit_set_mac_address

22
target/linux/ipq40xx/base-files/lib/preinit/06_set_preinit_iface_ipq40xx.sh Normal file
View File

@@ -0,0 +1,22 @@
set_preinit_iface() {
. /lib/functions.sh
case $(board_name) in
aruba,ap-303| \
asus,rt-ac58u| \
avm,fritzbox-4040| \
ezviz,cs-w3-wd1200g-eup| \
glinet,gl-b1300| \
linksys,ea8300| \
linksys,mr8300| \
meraki,mr33| \
zyxel,nbg6617)
ifname=eth0
;;
devolo,magic-2-wifi-next)
ifname=eth1
;;
esac
}
boot_hook_add preinit_main set_preinit_iface

108
target/linux/ipq40xx/base-files/lib/upgrade/dualboot_datachk.sh Normal file
View File

@@ -0,0 +1,108 @@
# The U-Boot loader with the datachk patchset for dualbooting requires image
# sizes and checksums to be provided in the U-Boot environment.
# The devices come with 2 main partitions - while one is active
# sysupgrade will flash the other. The boot order is changed to boot the
# newly flashed partition. If the new partition can't be booted due to
# upgrade failures the previously used partition is loaded.
platform_do_upgrade_dualboot_datachk() {
local tar_file="$1"
local restore_backup
local primary_kernel_mtd
local setenv_script="/tmp/fw_env_upgrade"
local kernel_mtd="$(find_mtd_index $PART_NAME)"
local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
# detect to which flash region the new image is written to.
#
# 1. check what is the mtd index for the first flash region on this
# device
# 2. check if the target partition ("inactive") has the mtd index of
# the first flash region
#
# - when it is: the new bootseq will be 1,2 and the first region is
# modified
# - when it isnt: bootseq will be 2,1 and the second region is
# modified
#
# The detection has to be done via the hardcoded mtd partition because
# the current boot might be done with the fallback region. Let us
# assume that the current bootseq is 1,2. The bootloader detected that
# the image in flash region 1 is corrupt and thus switches to flash
# region 2. The bootseq in the u-boot-env is now still the same and
# the sysupgrade code can now only rely on the actual mtd indexes and
# not the bootseq variable to detect the currently booted flash
# region/image.
#
# In the above example, an implementation which uses bootseq ("1,2") to
# detect the currently booted image would assume that region 1 is booted
# and then overwrite the variables for the wrong flash region (aka the
# one which isn't modified). This could result in a device which doesn't
# boot anymore to Linux until it was reflashed with ap51-flash.
local next_boot_part="1"
case "$(board_name)" in
plasmacloud,pa1200|\
openmesh,a42)
primary_kernel_mtd=8
;;
plasmacloud,pa2200|\
openmesh,a62)
primary_kernel_mtd=10
;;
*)
echo "failed to detect primary kernel mtd partition for board"
return 1
;;
esac
[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
# rootfs without EOF marker
rootfs_length=$((rootfs_length-4))
local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
# md5 checksum of rootfs with EOF marker
local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
#
# add tar support to get_image() to use default_do_upgrade() instead?
#
# take care of restoring a saved config
[ -n "$UPGRADE_BACKUP" ] && restore_backup="${MTD_CONFIG_ARGS} -j ${UPGRADE_BACKUP}"
mtd -q erase inactive
tar xf $tar_file ${board_dir}/root -O | mtd -n -p $kernel_length $restore_backup write - $PART_NAME
tar xf $tar_file ${board_dir}/kernel -O | mtd -n write - $PART_NAME
# prepare new u-boot env
if [ "$next_boot_part" = "1" ]; then
echo "bootseq 1,2" > $setenv_script
else
echo "bootseq 2,1" > $setenv_script
fi
printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
# store u-boot env changes
mkdir -p /var/lock
fw_setenv -s $setenv_script || {
echo "failed to update U-Boot environment"
return 1
}
}

122
target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh Executable file
View File

@@ -0,0 +1,122 @@
linksys_get_target_firmware() {
local cur_boot_part mtd_ubi0
cur_boot_part="$(/usr/sbin/fw_printenv -n boot_part)"
if [ -z "${cur_boot_part}" ]; then
mtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)
case "$(grep -E "^mtd${mtd_ubi0}:" /proc/mtd | cut -d '"' -f 2)" in
kernel|rootfs)
cur_boot_part=1
;;
alt_kernel|alt_rootfs)
cur_boot_part=2
;;
esac
>&2 printf "Current boot_part='%s' selected from ubi0/mtd_num='%s'" \
"${cur_boot_part}" "${mtd_ubi0}"
fi
# OEM U-Boot for EA6350v3, EA8300 and MR8300; bootcmd=
# if test $auto_recovery = no;
# then bootipq;
# elif test $boot_part = 1;
# then run bootpart1;
# else run bootpart2;
# fi
case "$cur_boot_part" in
1)
fw_setenv -s - <<-EOF
boot_part 2
auto_recovery yes
EOF
printf "alt_kernel"
return
;;
2)
fw_setenv -s - <<-EOF
boot_part 1
auto_recovery yes
EOF
printf "kernel"
return
;;
*)
return
;;
esac
}
linksys_get_root_magic() {
(get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null
}
platform_do_upgrade_linksys() {
local magic_long="$(get_magic_long "$1")"
local rm_oem_fw_vols="squashfs ubifs" # from OEM [alt_]rootfs UBI
local vol
mkdir -p /var/lock
local part_label="$(linksys_get_target_firmware)"
touch /var/lock/fw_printenv.lock
if [ -z "$part_label" ]; then
echo "cannot find target partition"
exit 1
fi
local target_mtd=$(find_mtd_part "$part_label")
[ "$magic_long" = "73797375" ] && {
CI_KERNPART="$part_label"
if [ "$part_label" = "kernel" ]; then
CI_UBIPART="rootfs"
else
CI_UBIPART="alt_rootfs"
fi
local mtdnum="$(find_mtd_index "$CI_UBIPART")"
if [ ! "$mtdnum" ]; then
echo "cannot find ubi mtd partition $CI_UBIPART"
return 1
fi
local ubidev="$(nand_find_ubi "$CI_UBIPART")"
if [ ! "$ubidev" ]; then
ubiattach -m "$mtdnum"
sync
ubidev="$(nand_find_ubi "$CI_UBIPART")"
fi
if [ "$ubidev" ]; then
for vol in $rm_oem_fw_vols; do
ubirmvol "/dev/$ubidev" -N "$vol" 2>/dev/null
done
fi
# complete std upgrade
nand_upgrade_tar "$1"
}
[ "$magic_long" = "27051956" ] && {
# This magic is for a uImage (which is a sysupgrade image)
# check firmwares' rootfs types
local oldroot="$(linksys_get_root_magic "$target_mtd")"
local newroot="$(linksys_get_root_magic "$1")"
if [ "$newroot" = "55424923" ] && [ "$oldroot" = "55424923" ]; then
# we're upgrading from a firmware with UBI to one with UBI
# erase everything to be safe
# - Is that really needed? Won't remove (or comment) the if,
# because it may be needed in a future device.
#mtd erase $part_label
#get_image "$1" | mtd -n write - $part_label
echo "writing \"$1\" UBI image to \"$part_label\" (UBI)..."
get_image "$1" | mtd write - "$part_label"
else
echo "writing \"$1\" image to \"$part_label\""
get_image "$1" | mtd write - "$part_label"
fi
}
}

134
target/linux/ipq40xx/base-files/lib/upgrade/platform.sh Normal file
View File

@@ -0,0 +1,134 @@
PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_check_image() {
case "$(board_name)" in
asus,rt-ac58u)
CI_UBIPART="UBI_DEV"
local ubidev=$(nand_find_ubi $CI_UBIPART)
local asus_root=$(nand_find_volume $ubidev jffs2)
[ -n "$asus_root" ] || return 0
cat << EOF
jffs2 partition is still present.
There's probably no space left
to install the filesystem.
You need to delete the jffs2 partition first:
# ubirmvol /dev/ubi0 --name=jffs2
Once this is done. Retry.
EOF
return 1
;;
esac
return 0;
}
askey_do_upgrade() {
local tar_file="$1"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
tar Oxf $tar_file ${board_dir}/root | mtd write - rootfs
nand_do_upgrade "$1"
}
zyxel_do_upgrade() {
local tar_file="$1"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
tar Oxf $tar_file ${board_dir}/kernel | mtd write - kernel
if [ -n "$UPGRADE_BACKUP" ]; then
tar Oxf $tar_file ${board_dir}/root | mtd -j "$UPGRADE_BACKUP" write - rootfs
else
tar Oxf $tar_file ${board_dir}/root | mtd write - rootfs
fi
}
platform_do_upgrade() {
case "$(board_name)" in
8dev,jalapeno |\
aruba,ap-303 |\
aruba,ap-303h |\
aruba,ap-365 |\
avm,fritzbox-7530 |\
avm,fritzrepeater-1200 |\
avm,fritzrepeater-3000 |\
buffalo,wtr-m2133hp |\
cilab,meshpoint-one |\
edgecore,ecw5211 |\
edgecore,oap100 |\
engenius,eap2200 |\
glinet,gl-ap1300 |\
luma,wrtq-329acn |\
mobipromo,cm520-79f |\
netgear,wac510 |\
qxwlan,e2600ac-c2)
nand_do_upgrade "$1"
;;
alfa-network,ap120c-ac)
part="$(awk -F 'ubi.mtd=' '{printf $2}' /proc/cmdline | sed -e 's/ .*$//')"
if [ "$part" = "rootfs1" ]; then
fw_setenv active 2 || exit 1
CI_UBIPART="rootfs2"
else
fw_setenv active 1 || exit 1
CI_UBIPART="rootfs1"
fi
nand_do_upgrade "$1"
;;
asus,map-ac2200)
CI_KERNPART="linux"
nand_do_upgrade "$1"
;;
asus,rt-ac58u)
CI_UBIPART="UBI_DEV"
CI_KERNPART="linux"
nand_do_upgrade "$1"
;;
cellc,rtl30vw)
CI_UBIPART="ubifs"
askey_do_upgrade "$1"
;;
compex,wpj419)
nand_do_upgrade "$1"
;;
linksys,ea6350v3 |\
linksys,ea8300 |\
linksys,mr8300)
platform_do_upgrade_linksys "$1"
;;
meraki,mr33)
CI_KERNPART="part.safe"
nand_do_upgrade "$1"
;;
mikrotik,hap-ac2|\
mikrotik,sxtsq-5-ac)
[ "$(rootfs_type)" = "tmpfs" ] && mtd erase firmware
default_do_upgrade "$1"
;;
openmesh,a42 |\
openmesh,a62 |\
plasmacloud,pa1200 |\
plasmacloud,pa2200)
PART_NAME="inactive"
platform_do_upgrade_dualboot_datachk "$1"
;;
zyxel,nbg6617)
zyxel_do_upgrade "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

493
target/linux/ipq40xx/config-5.10 Normal file
View File

@@ -0,0 +1,493 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_ESSEDMA=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

461
target/linux/ipq40xx/config-5.4 Normal file
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@@ -0,0 +1,461 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_ESSEDMA=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_UFS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PM=y
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
CONFIG_QCOM_SCM=y
CONFIG_QCOM_SCM_32=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_TURING_404 is not set
# CONFIG_QRTR is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts Normal file
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// SPDX-License-Identifier: ISC
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "OpenMesh A42";
compatible = "openmesh,a42";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_green;
led-running = &led_status_green;
led-upgrade = &led_status_green;
};
leds {
compatible = "gpio-leds";
status_red {
label = "red:status";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
status_blue {
label = "blue:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
/* hw_margin_ms is actually 300s but driver limits it to 60s */
hw_margin_ms = <60000>;
always-running;
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ALFA Network AP120C-AC";
compatible = "alfa-network,ap120c-ac";
aliases {
led-boot = &status;
led-failsafe = &status;
led-running = &status;
led-upgrade = &status;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
status: status {
label = "blue:status";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
wan {
label = "amber:wan";
gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "red:wlan5g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_i2c3 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 4 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "priv_data1";
reg = <0x00180000 0x00010000>;
read-only;
};
partition@190000 {
label = "priv_data2";
reg = <0x00190000 0x00010000>;
read-only;
};
};
};
nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs1";
reg = <0x00000000 0x04000000>;
};
partition@4000000 {
label = "rootfs2";
reg = <0x04000000 0x04000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&ethphy4 {
gpio-controller;
#gpio-cells = <2>;
};
&gmac0 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
vlan_tag = <1 0x10>;
};
&gmac1 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
vlan_tag = <2 0x20>;
};
&tlmm {
i2c0_pins: i2c0_pinmux {
mux_i2c {
function = "blsp_i2c0";
pins = "gpio58", "gpio59";
drive-strength = <16>;
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_mdio {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_mdc {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial0_pins: serial0_pinmux {
mux_uart {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux_spi {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio4";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EZVIZ CS-W3-WD1200G EUP";
compatible = "ezviz,cs-w3-wd1200g-eup";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_green;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_status_red: status_red {
label = "red:status";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
led_status_blue: status_blue {
label = "blue:status";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition9@580000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x00e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
};

241
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "D-Link DAP 2610";
compatible = "dlink,dap-2610";
aliases {
led-boot = &led_red;
led-failsafe = &led_red;
led-running = &led_green;
led-upgrade = &led_red;
};
soc {
edma@c080000 {
qcom,num_gmac = <1>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
rng@22000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x20>;
switch_wan_bmp = <0x00>;
};
ess-psgmii@98000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_red: red {
label = "red:power";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
};
led_green: green {
label = "green:power";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fixed-partitions";
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "wrg";
label = "firmware";
reg = <0x180000 0xdc0000>;
};
partition@fb0000 {
label = "rgbd";
reg = <0xfb0000 0x10000>;
read-only;
};
partition@fc0000 {
label = "bdcfg";
reg = <0xfc0000 0x10000>;
read-only;
};
partition@fd0000 {
label = "langpack";
reg = <0xfd0000 0x20000>;
read-only;
};
partition@ff0000 {
label = "certificate";
reg = <0xff0000 0x10000>;
read-only;
};
partition@f40000 {
label = "captival";
reg = <0xf40000 0x70000>;
read-only;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&mdio {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "dlink,dap-2610";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "dlink,dap-2610";
};

277
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Linksys EA6350v3";
compatible = "linksys,ea6350v3";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power: status {
label = "green:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
MBIB@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
QSEE@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
CDT@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
APPSBLENV@d0000 {
label = "APPSBLENV";
reg = <0x000d0000 0x00010000>;
read-only;
};
APPSBL@e0000 {
label = "APPSBL"; /* uboot */
reg = <0x000e0000 0x00080000>;
read-only;
};
ART@160000 {
label = "ART";
reg = <0x00160000 0x00010000>;
read-only;
};
u_env@170000 {
label = "u_env";
reg = <0x00170000 0x00020000>;
};
s_env@190000 {
label = "s_env";
reg = <0x00190000 0x00020000>;
};
devinfo@1b0000 {
label = "devinfo";
reg = <0x001b0000 0x00010000>;
};
/* 0x001c0000 - 0x00200000 unused */
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x00000000 0x02800000>;
};
rootfs@300000 {
label = "rootfs";
reg = <0x00300000 0x02500000>;
};
alt_kernel@2800000 {
label = "alt_kernel";
reg = <0x02800000 0x02800000>;
};
alt_rootfs@2b00000 {
label = "alt_rootfs";
reg = <0x02b00000 0x02500000>;
};
sysdiag@5000000 {
label = "sysdiag";
reg = <0x05000000 0x00100000>;
};
syscfg@5100000 {
label = "syscfg";
reg = <0x05100000 0x02F00000>;
};
/* 0x00000000 - 0x08000000: 128 MiB */
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EAP1300";
compatible = "engenius,eap1300";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
leds {
compatible = "gpio-leds";
power: orange {
label = "orange:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
lan {
label = "blue:lan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
mesh {
label = "blue:mesh";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "yellow:wlan5g";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00090000>;
read-only;
};
partition7@180000 {
label = "0:ART";
reg = <0x00180000 0x00010000>;
read-only;
};
partition8@190000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x190000 0x1dc0000>;
};
partition9@1f50000 {
label = "u-boot-env";
reg = <0x01f50000 0x00010000>;
};
partition10@1f60000 {
label = "userconfig";
reg = <0x01f60000 0x000a0000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <2 0x20>;
};
&gmac1 {
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};

323
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Edgecore ECW5211";
compatible = "edgecore,ecw5211";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &gmac0;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "yellow:power";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
soc {
rng@22000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_mdio {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_mdc {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54", "gpio4";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c0_pins: i2c0_pinmux {
mux_i2c {
function = "blsp_i2c0";
pins = "gpio58", "gpio59";
drive-strength = <16>;
bias-disable;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV"; /* uboot env */
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "0:APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
flash@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x04000000>;
};
};
};
};
&blsp1_i2c3 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gmac0 {
qcom,poll_required = <1>;
qcom,phy_mdio_addr = <4>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,poll_required = <1>;
qcom,phy_mdio_addr = <3>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

233
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EMD1";
compatible = "engenius,emd1";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x20>;
switch_wan_bmp = <0x00>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "red:wlan2g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
mesh {
label = "orange:mesh";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
label = "userconfig";
reg = <0x00180000 0x00080000>;
read-only;
};
partition9@200000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x200000 0x01e00000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMD1";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMD1";
};

235
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EMR3500";
compatible = "engenius,emr3500";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2_hs_phy: hsphy@a8000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
leds {
compatible = "gpio-leds";
power: white {
label = "white:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
red {
label = "red";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
orange {
label = "orange";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "userconfig";
reg = <0x00180000 0x00080000>;
read-only;
};
partition@200000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x200000 0x1e00000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <1 0x10>;
};
&gmac1 {
vlan_tag = <2 0x20>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius ENS620EXT";
compatible = "engenius,ens620ext";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
/*
* Disable the broken restart as a workaround for the buggy
* 3.0.0/3.0.1 U-boots that ship with the device.
* Note: The watchdog is now used to restart this device.
*/
restart@4ab000 {
status = "disabled";
};
};
buttons {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power: power {
label = "amber:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "green:lan1";
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "green:lan2";
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00090000>;
read-only;
};
partition@180000 {
label = "ART";
reg = <0x00180000 0x00010000>;
read-only;
};
partition@190000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00190000 0x14d0000>;
};
partition@1660000 {
label = "failsafe";
reg = <0x01660000 0x008F0000>;
read-only;
};
partition@1f50000 {
label = "u-boot-env";
reg = <0x01f50000 0x00010000>;
read-only;
};
partition@1f60000 {
label = "userconfig";
reg = <0x01f60000 0x000a0000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
};

31
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts Normal file
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4018-ex61x0v2.dtsi"
/ {
model = "Netgear EX6100v2";
compatible = "netgear,ex6100v2";
};
&wifi0 {
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
};
&wifi1 {
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
};

31
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts Normal file
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4018-ex61x0v2.dtsi"
/ {
model = "Netgear EX6150v2";
compatible = "netgear,ex6150v2";
};
&wifi0 {
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
};
&wifi1 {
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
};

312
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi Normal file
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Netgear EX61X0v2";
compatible = "netgear,ex61x0v2";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
aliases {
led-boot = &power_amber;
led-failsafe = &power_amber;
led-running = &power_green;
led-upgrade = &power_amber;
label-mac-device = &gmac0;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
power_amber: power_amber {
label = "amber:power";
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
};
power_green: power_green {
label = "green:power";
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
};
right {
label = "blue:right";
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
};
left {
label = "blue:left";
gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
};
client_green {
label = "green:client";
gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
};
client_red {
label = "red:client";
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
};
router_green {
label = "green:router";
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
};
router_red {
label = "red:router";
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l12805d@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <45000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
label = "config";
reg = <0x00180000 0x00010000>;
read-only;
};
partition9@190000 {
label = "pot";
reg = <0x00190000 0x00010000>;
read-only;
};
partition10@1a0000 {
label = "dnidata";
reg = <0x001a0000 0x00010000>;
read-only;
};
partition11@1b0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x001b0000 0x00e10000>;
};
partition12@fc0000 {
label = "language";
reg = <0x00fc0000 0x00040000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

309
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Box 4040";
compatible = "avm,fritzbox-4040";
aliases {
led-boot = &power;
led-failsafe = &flash;
led-running = &power;
led-upgrade = &flash;
label-mac-device = &gmac0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
switch-leds {
compatible = "gpio-leds";
wlan {
label = "green:wlan";
gpios = <&ethphy0 0 GPIO_ACTIVE_HIGH>;
};
panic: info_red {
label = "red:info";
gpios = <&ethphy0 1 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
wan {
label = "green:wan";
gpios = <&ethphy1 0 GPIO_ACTIVE_HIGH>;
};
power: power {
label = "green:power";
gpios = <&ethphy2 1 GPIO_ACTIVE_HIGH>;
};
lan {
label = "green:lan";
gpios = <&ethphy3 0 GPIO_ACTIVE_HIGH>;
};
flash: info_amber {
label = "amber:info";
gpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
status = "okay";
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBLENV"; /* uboot env - empty */
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "urlader"; /* APPSBL */
reg = <0x000f0000 0x0002dc000>;
read-only;
};
partition7@11dc00 {
/* make a backup of this partition! */
label = "urlader_config";
reg = <0x0011dc00 0x00002400>;
read-only;
};
partition8@120000 {
label = "tffs1";
reg = <0x00120000 0x00080000>;
read-only;
};
partition9@1a0000 {
label = "tffs2";
reg = <0x001a0000 0x00080000>;
read-only;
};
partition10@220000 {
label = "uboot";
reg = <0x00220000 0x00080000>;
read-only;
};
partition11@2A0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x002a0000 0x01c60000>;
};
partition12@1f00000 {
label = "jffs2";
reg = <0x01f00000 0x00100000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&ethphy0 {
gpio-controller;
#gpio-cells = <2>;
};
&ethphy1 {
gpio-controller;
#gpio-cells = <2>;
enable-usb-power {
gpio-hog;
line-name = "enable USB3 power";
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&ethphy2 {
gpio-controller;
#gpio-cells = <2>;
};
&ethphy3 {
gpio-controller;
#gpio-cells = <2>;
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
};

269
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-AP1300";
compatible = "glinet,gl-ap1300";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1 clk_ignore_unused";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x18>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "green:power";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
wan {
label = "green:wan";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
flash@0 {
status = "okay";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
spi-nand@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux_spi {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio5";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-AP1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-AP1300";
};

273
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MikroTik hAP ac2";
compatible = "mikrotik,hap-ac2";
memory {
device_type = "memory";
reg = <0x80000000 0x08000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &led_user;
led-failsafe = &led_user;
led-running = &led_user;
led-upgrade = &led_user;
};
soc {
rng@22000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
mode {
label = "mode";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
leds {
compatible = "gpio-leds";
power {
label = "green:power";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
default-state = "keep";
panic-indicator;
};
led_user: user {
label = "green:user";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
enable-usb-power {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "enable USB power";
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
size = <0x2000>;
};
dtb_config {
read-only;
};
soft_config {
};
};
partition@100000 {
compatible = "mikrotik,minor";
label = "firmware";
reg = <0x100000 0xf00000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&mdio {
status = "okay";
};
&ethphy0 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy1 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy2 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy3 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy4 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
};

9
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
#include "qcom-ipq4018-jalapeno.dtsi"
/ {
model = "8devices Jalapeno";
compatible = "8dev,jalapeno";
};

269
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>; /* lan port bitmap */
};
edma@c080000 {
status = "okay";
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
pinmux_1 {
pins = "gpio53";
function = "mdio";
};
pinmux_2 {
pins = "gpio52";
function = "mdc";
};
pinconf {
pins = "gpio52", "gpio53";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
status = "okay";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
spi-nand@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,poll_required = <1>;
qcom,poll_required_dynamic = <1>;
qcom,phy_mdio_addr = <3>;
vlan_tag = <1 0x10>;
};
&gmac1 {
qcom,poll_required = <1>;
qcom,poll_required_dynamic = <1>;
qcom,phy_mdio_addr = <4>;
vlan_tag = <2 0x20>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

268
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "devolo Magic 2 WiFi next";
compatible = "devolo,magic-2-wifi-next";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
};
ess-psgmii@98000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x3e>;
switch_wan_bmp = <0x0>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <3>;
gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x10>;
};
gmac1 {
qcom,phy_mdio_addr = <2>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x08>;
};
gmac2 {
local-mac-address = [00 00 00 00 00 00];
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x20>;
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
plc {
gpio-export,name = "plc-enable";
gpio-export,output = <1>;
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
};
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "WLAN";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "Reset";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
status_dlan {
label = "white:dlan";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
status_wlan {
label = "white:wlan";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
error_dlan {
label = "red:dlan";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
};
&tlmm {
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio61", "gpio60";
function = "blsp_uart0";
bias-disable;
};
};
button_pins: button_pinmux {
mux {
function = "gpio";
pins = "gpio0", "gpio5";
bias-disable;
input;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "n25q128a11";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x01a80000>;
};
};
};
};

81
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
* Author: Robert Marko <robert@meshpoint.me>
*/
#include "qcom-ipq4018-jalapeno.dtsi"
/ {
model = "Crisis Innovation Lab MeshPoint.One";
compatible = "cilab,meshpoint-one";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
soc {
i2c-gpio {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
&tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
>;
bme280@76 {
status = "okay";
compatible = "bosch,bme280";
reg = <0x76>;
};
pcf2129@51 {
status = "okay";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
ina230@40 {
status = "okay";
compatible = "ti,ina230";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina230@44 {
status = "okay";
compatible = "ti,ina230";
reg = <0x44>;
shunt-resistor = <2000>;
};
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
leds {
compatible = "gpio-leds";
led_status: status {
label = "blue:status";
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
};
};
};

337
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ZyXEL NBG6617";
compatible = "zyxel,nbg6617";
chosen {
/*
* the vendor u-boot adds root and mtdparts cmdline parameters
* which we don't want... but we have to overwrite them or else
* the kernel will take them at face value.
*/
bootargs-append = " mtdparts= root=31:13";
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RFKILL>;
linux,input-type = <EV_SW>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
power: power {
label = "green:power";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
usb {
label = "green:usb";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-low;
};
};
led_pins: led_pinmux {
mux {
pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
drive-strength = <0x8>;
bias-disable;
output-low;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
status = "okay";
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBL"; /* u-boot */
reg = <0x000e0000 0x00080000>;
/* U-Boot Standalone App "zloader" is located at 0x64000 */
read-only;
};
partition6@160000 {
label = "APPSBLENV"; /* u-boot env */
reg = <0x00160000 0x00010000>;
};
partition7@170000 {
/* make a backup of this partition! */
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
label = "kernel";
reg = <0x00180000 0x00400000>;
};
partition9@580000 {
label = "dualflag";
reg = <0x00580000 0x00010000>;
read-only;
};
partition10@590000 {
label = "header";
reg = <0x00590000 0x00010000>;
};
partition11@5a0000 {
label = "romd";
reg = <0x005a0000 0x00100000>;
read-only;
};
partition12@6a0000 {
label = "not_root_data";
/*
* for some strange reason, someone at ZyXEL
* had the "great" idea to put the rootfs_data
* in front of rootfs... Don't do that!
* As a result this one, full MebiByte remains
* unused.
*/
reg = <0x006a0000 0x00100000>;
};
partition13@7a0000 {
label = "rootfs";
reg = <0x007a0000 0x01860000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
* Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Plasma Cloud PA1200";
compatible = "plasmacloud,pa1200";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &led_status_purple;
led-failsafe = &led_status_yellow;
led-running = &led_status_cyan;
led-upgrade = &led_status_yellow;
};
leds {
compatible = "gpio-leds";
led_status_cyan: status_cyan {
label = "cyan:status";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
led_status_purple: status_purple {
label = "purple:status";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
led_status_yellow: status_yellow {
label = "yellow:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ASUS RT-AC58U";
compatible = "asus,rt-ac58u";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
bootargs-append = " ubi.mtd=UBI_DEV";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_power: status {
label = "blue:status";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wan {
label = "blue:wan";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan2G {
label = "blue:wlan2G";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5G {
label = "blue:wlan5G";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
usb {
label = "blue:usb";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
trigger-sources = <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
lan {
label = "blue:lan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
/*
* U-boot looks for "n25q128a11" node,
* if we don't have it, it will spit out the following warning:
* "ipq: fdt fixup unable to find compatible node".
*/
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
spi-max-frequency = <30000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
/* 0x00180000 - 0x00200000 unused */
};
};
spi-nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <30000000>;
/*
* U-boot looks for "spinand,mt29f" node,
* if we don't have it, it will spit out the following warning:
* "ipq: fdt fixup unable to find compatible node".
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/*
* TODO: change to label = "ubi" once we drop 4.14.
* also drop the bootargs-append and all the
* userspace CI_UBIPART="UBI_DEV" remains.
*/
label = "UBI_DEV";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "RT-AC58U";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "RT-AC58U";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MikroTik SXTsq 5 ac (RBSXTsqG-5acD)";
compatible = "mikrotik,sxtsq-5-ac";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &led_user;
led-failsafe = &led_user;
led-running = &led_user;
led-upgrade = &led_user;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
phy-mode = "rgmii";
qcom,num_gmac = <1>;
qcom,single-phy;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power {
label = "blue:power";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
default-state = "keep";
panic-indicator;
};
led_user: user {
label = "green:user";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
rssilow {
label = "green:rssilow";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
rssimediumlow {
label = "green:rssimediumlow";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
rssimedium {
label = "green:rssimedium";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
rssimediumhigh {
label = "green:rssimediumhigh";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
rssihigh {
label = "green:rssihigh";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
};
dtb_config {
read-only;
};
soft_config {
};
};
partition@100000 {
compatible = "mikrotik,minor";
label = "firmware";
reg = <0x100000 0xf00000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-SXTsq-5-ac";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&mdio {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Netgear WAC510";
compatible = "netgear,wac510";
aliases {
led-boot = &led_power_amber;
led-failsafe = &led_power_amber;
led-running = &led_power_green;
led-upgrade = &led_power_amber;
label-mac-device = &gmac0;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
soc {
rng@22000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
ssr: ssr@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
led_power_amber: power_amber {
label = "amber:power";
gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
panic-indicator;
};
led_power_green: power_green {
label = "green:power";
gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
};
wlan2g_blue {
label = "blue:wlan2g";
gpios = <&ssr 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&ssr 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0radio";
};
wlan5g_blue {
label = "blue:wlan5g";
gpios = <&ssr 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&ssr 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1radio";
};
act_green {
label = "green:act";
gpios = <&ssr 0 GPIO_ACTIVE_LOW>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x000f0000>;
read-only;
};
partition@1e0000 {
label = "0:MANUDATA";
reg = <0x001e0000 0x00010000>;
read-only;
};
partition@1f0000 {
label = "0:ART";
reg = <0x001f0000 0x00010000>;
read-only;
};
};
};
nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <48000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x03800000>;
};
partition@3800000 {
label = "rootfs_1";
reg = <0x03800000 0x03800000>;
};
partition@7000000 {
label = "var_config";
reg = <0x07000000 0x00f00000>;
read-only;
};
partition@7f00000 {
label = "Oops_log";
reg = <0x07f00000 0x000c0000>;
read-only;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
&gmac0 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-WAC510";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-WAC510";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts Normal file
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ZyXEL WRE6606";
compatible = "zyxel,wre6606";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
chosen {
bootargs-append = " mtdparts=";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
leds {
compatible = "gpio-leds";
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
power: power {
label = "green:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
wlan5g_red {
label = "red:wlan5g";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
wlan2g_red {
label = "red:wlan2g";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l12805d@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x00ce0000>;
};
partition9@e60000 {
label = "manufacture";
reg = <0x00e60000 0x00050000>;
read-only;
};
partition10@eb0000 {
label = "storage";
reg = <0x00eb0000 0x00150000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Luma Home WRTQ-329ACN";
compatible = "luma,wrtq-329acn";
i2c-gpio {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
/* No driver exists */
led_ring@48 {
compatible = "ti,msp430";
reg = <0x48>;
};
eeprom@50 {
compatible = "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
read-only;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@3;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x1e>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x040000 0x020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x060000 0x060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x0c0000 0x010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x0d0000 0x010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x0e0000 0x010000>;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x0f0000 0x080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x010000>;
read-only;
};
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x0000000 0x8000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <2>;
qcom,poll_required = <1>;
};
&gmac1 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
};
&tlmm {
serial0_pins: serial0_pinmux {
mux {
function = "blsp_uart0";
pins = "gpio60", "gpio61";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
bias-disable;
drive-strength = <12>;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
bias-disable;
drive-strength = <2>;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts Normal file
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// SPDX-License-Identifier: ISC
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "OpenMesh A62";
compatible = "openmesh,a62";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_green;
led-running = &led_status_green;
led-upgrade = &led_status_green;
};
leds {
compatible = "gpio-leds";
status_red {
label = "red:status";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
status_blue {
label = "blue:status";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
/* hw_margin_ms is actually 300s but driver limits it to 60s */
hw_margin_ms = <60000>;
always-running;
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
enable-usb-power {
gpio-hog;
gpios = <58 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "enable USB2 power";
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "OM-A62";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A62";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A62";
ieee80211-freq-limit = <5470000 5875000>;
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MobiPromo CM520-79F";
compatible = "mobipromo,cm520-79f";
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
usb {
label = "blue:usb";
gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "usbport";
trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
};
led_sys: can {
label = "blue:can";
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
};
wan {
label = "blue:wan";
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "blue:lan1";
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "blue:lan2";
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
status = "okay";
};
&blsp1_uart2 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
nvmem-cells = <&macaddr_art_1006>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_art_5006>;
nvmem-cell-names = "mac-address";
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "MIBIB";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "BOOTCONFIG";
reg = <0x200000 0x100000>;
};
partition@300000 {
label = "QSEE";
reg = <0x300000 0x100000>;
read-only;
};
partition@400000 {
label = "QSEE_1";
reg = <0x400000 0x100000>;
read-only;
};
partition@500000 {
label = "CDT";
reg = <0x500000 0x80000>;
read-only;
};
partition@580000 {
label = "CDT_1";
reg = <0x580000 0x80000>;
read-only;
};
partition@600000 {
label = "BOOTCONFIG1";
reg = <0x600000 0x80000>;
};
partition@680000 {
label = "APPSBLENV";
reg = <0x680000 0x80000>;
};
partition@700000 {
label = "APPSBL";
reg = <0x700000 0x200000>;
read-only;
};
partition@900000 {
label = "APPSBL_1";
reg = <0x900000 0x200000>;
read-only;
};
art: partition@b00000 {
label = "ART";
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "ubi";
reg = <0xb80000 0x7480000>;
};
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "CM520-79F";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "CM520-79F";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_1006: macaddr@1006 {
reg = <0x1006 0x6>;
};
macaddr_art_5006: macaddr@5006 {
reg = <0x5006 0x6>;
};
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019-e2600ac.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qxwlan E2600AC c1";
compatible = "qxwlan,e2600ac-c1";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019-e2600ac.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qxwlan E2600AC c2";
compatible = "qxwlan,e2600ac-c2";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x04000000>;
};
};
};
};
&tlmm {
nand_pins: nand-pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};

266
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qxwlan E2600AC";
compatible = "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256MB */
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
i2c@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
led1 {
label = "green:wlan0";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
led2 {
label = "green:wlan1";
gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
};
led3 {
label = "green:usb";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
led4 {
label = "green:ctrl1";
gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
};
led5 {
label = "green:ctrl2";
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
led6 {
label = "green:ctrl3";
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
i2c_0_pins: i2c-0-pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial0-pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
};

95
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-xx8300.dtsi"
/ {
model = "Linksys EA8300 (Dallas)";
compatible = "linksys,ea8300", "qcom,ipq4019";
aliases {
led-boot = &led_wps_amber;
led-failsafe = &led_wps;
led-running = &led_linksys;
led-upgrade = &led_world;
serial0 = &blsp1_uart1;
};
leds {
compatible = "gpio-leds";
// Retain node names from running OEM on EA8300
// Front panel LEDs, top to bottom
led_plug: diag {
label = "amber:plug";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
led_world: internet {
label = "amber:world";
gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
};
led_wps: wps {
label = "white:wps";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_wps_amber: wps_amber {
label = "amber:wps";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_linksys: pwr {
label = "white:linksys";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
// On back panel, above USB socket
led_usb: usb {
label = "green:usb";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb3_port1>, <&usb3_port2>,
<&usb2_port1>;
linux,default-trigger = "usbport";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5330000>;
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};
&wifi2 {
status = "okay";
ieee80211-freq-limit = <5490000 5835000>;
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "EnGenius EAP2200";
compatible = "engenius,eap2200";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "amber:power";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "blue:lan1";
gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "blue:lan2";
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "yellow:wlan5g";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan5g2 {
label = "yellow:wlan5g2";
gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy2tpt";
};
mode {
label = "blue:mode";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <1 0x10>;
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs1";
reg = <0x00000000 0x04000000>;
};
partition@40000000 {
label = "ubi";
reg = <0x04000000 0x04000000>;
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <5470000 5875000>;
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5350000>;
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};

303
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Box 7530";
compatible = "avm,fritzbox-7530";
aliases {
led-boot = &power_green;
led-failsafe = &info_red;
led-running = &power_green;
led-upgrade = &info_green;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
dect {
label = "dect";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
};
leds {
compatible = "gpio-leds";
info_red: info_red {
label = "red:info";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
};
info_green: info {
label = "green:info";
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
};
fon {
label = "green:fon";
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
power_green: power {
label = "green:power";
gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
usb-power {
line-name = "enable USB3 power";
gpios = <49 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x000000 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x080000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
dsl@1,0 {
compatible = "intel,vrx518";
status = "okay";
reg = <0x00010000 0 0 0 0>;
};
};
};

273
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Repeater 1200";
compatible = "avm,fritzrepeater-1200";
aliases {
led-boot = &power_green;
led-failsafe = &power_red;
led-running = &power_green;
led-upgrade = &power_red;
label-mac-device = &wifi0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@2;
/delete-node/ ethernet-phy@3;
/delete-node/ ethernet-phy@4;
/delete-node/ psgmii-phy@5;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
status = "okay";
phy-mode = "rgmii-id";
qcom,num_gmac = <1>;
qcom,single-phy;
};
};
key {
compatible = "gpio-keys";
wps {
label = "WPS button";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power_red: power_red {
label = "red:power";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
power_green: power_green {
label = "green:power";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
power_yellow {
label = "yellow:power";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
phy-reset {
line-name = "PHY-reset";
gpios = <19 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
phy-reset-2 {
line-name = "PHY-reset-2";
gpios = <47 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
};
&gmac0 {
qcom,phy_mdio_addr = <0>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};

269
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Repeater 3000";
compatible = "avm,fritzrepeater-3000";
aliases {
led-boot = &power_led;
led-failsafe = &power_led;
led-running = &power_led;
led-upgrade = &power_led;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x30>;
switch_wan_bmp = <0x02>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
key {
compatible = "gpio-keys";
connect {
label = "Connect";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
connect_red {
label = "red:connect";
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
connect_green {
label = "green:connect";
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
connect_blue {
label = "blue:connect";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
};
power_led: power {
label = "green:power";
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x000000 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x080000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&gmac0 {
vlan_tag = <1 0x30>;
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5350000>;
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
/* QCA9984 */
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <5470000 5875000>;
/* Uses the reference BDF */
};
};
};

357
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "8devices Habanero DVK";
compatible = "8dev,habanero-dvk";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_upgrade;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status: status {
label = "green:status";
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_upgrade: upgrade {
label = "green:upgrade";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56", "gpio57",
"gpio60", "gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67", "gpio68",
"gpio69";
function = "qpic";
bias-pull-down;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio28", "gpio29", "gpio30", "gpio31";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio32";
drive-strength = <10>;
bias-disable;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env */
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "cfg";
reg = <0x00180000 0x00040000>;
};
partition@1c0000 {
label = "firmware";
compatible = "denx,fit";
reg = <0x001c0000 0x01e40000>;
};
};
};
};
/* Some DVK boards ship without NAND */
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
/* Free slot for use */
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Habanero";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Habanero";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ASUS Lyra MAP-AC2200";
compatible = "asus,map-ac2200";
aliases {
led-boot = &led_blue0;
led-failsafe = &led_red0;
led-running = &led_blue0;
led-upgrade = &led_red0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "CDT";
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "APPSBL";
reg = <0x280000 0x140000>;
read-only;
};
partition@3c0000 {
label = "APPSBLENV";
reg = <0x3c0000 0x40000>;
read-only;
};
partition@400000 {
label = "ubi";
reg = <0x400000 0x7c00000>;
};
};
};
};
&tlmm {
i2c_0_pins: i2c_0_pinmux {
pinmux {
function = "blsp_i2c0";
pins = "gpio20", "gpio21";
drive-strength = <16>;
bias-disable;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
enable_ext_pa_high {
gpio-hog;
gpios = <44 GPIO_ACTIVE_HIGH>,
<46 GPIO_ACTIVE_HIGH>;
output-high;
bias-pull-down;
line-name = "enable external PA output-high";
};
enable_ext_pa_low {
gpio-hog;
gpios = <45 GPIO_ACTIVE_HIGH>,
<47 GPIO_ACTIVE_HIGH>;
output-low;
bias-pull-down;
line-name = "enable external PA output-low";
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
ieee80211-freq-limit = <5470000 5875000>;
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&usb2_hs_phy {
/* Bluetooth module attached via USB */
status = "okay";
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
led-controller@32 {
/* 9-channel RGB LED controller */
compatible = "national,lp5523";
reg = <0x32>;
clock-mode = [01];
led_blue0: blue0 {
chan-name = "blue0";
label = "blue:chan0";
led-cur = [fa];
max-cur = [ff];
};
blue1 {
chan-name = "blue1";
label = "blue:chan1";
led-cur = [fa];
max-cur = [ff];
};
blue2 {
chan-name = "blue2";
label = "blue:chan2";
led-cur = [fa];
max-cur = [ff];
};
led_green0: green0 {
chan-name = "green0";
label = "green:chan0";
led-cur = [fa];
max-cur = [ff];
};
green1 {
chan-name = "green1";
label = "green:chan1";
led-cur = [fa];
max-cur = [ff];
};
green2 {
chan-name = "green2";
label = "green:chan2";
led-cur = [fa];
max-cur = [ff];
};
led_red0: red0 {
chan-name = "red0";
label = "red:chan0";
led-cur = [fa];
max-cur = [ff];
};
red1 {
chan-name = "red1";
label = "red:chan1";
led-cur = [fa];
max-cur = [ff];
};
red2 {
chan-name = "red2";
label = "red:chan2";
led-cur = [fa];
max-cur = [ff];
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-xx8300.dtsi"
/ {
model = "Linksys MR8300 (Dallas)";
compatible = "linksys,mr8300", "qcom,ipq4019";
aliases {
led-boot = &led_blue;
led-failsafe = &led_red;
led-running = &led_blue;
led-upgrade = &led_amber;
serial0 = &blsp1_uart1;
};
// Top panel LEDs, above Linksys logo
leds {
compatible = "gpio-leds";
led_red: red {
label = "red:alarm";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
led_amber: amber {
label = "amber:programming";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_blue: blue {
label = "blue:power";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
// On back panel, above USB socket
led_usb: usb {
label = "green:usb";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb3_port1>, <&usb3_port2>,
<&usb2_port1>;
linux,default-trigger = "usbport";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5330000>;
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};
&wifi2 {
status = "okay";
ieee80211-freq-limit = <5490000 5835000>;
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-oap100.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EdgeCore OAP-100";
compatible = "edgecore,oap100";
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
soc {
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */
switch_initvlas = <0x0007c 0x54>; /* port0 status */
switch_lan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
key {
compatible = "gpio-keys";
button@1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
led_system: led_system {
label = "green:system";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
led_2g {
label = "blue:wlan2g";
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
};
led_5g {
label = "blue:wlan5g";
gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
usb {
gpio-export,name = "usb-power";
gpio-export,output = <1>;
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
};
poe {
gpio-export,name = "poe-power";
gpio-export,output = <0>;
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "m25p80", "gd25q256";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x4000000>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Edgecore OAP100";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Edgecore OAP100";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
* Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Plasma Cloud PA2200";
compatible = "plasmacloud,pa2200";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
aliases {
led-boot = &led_power_orange;
led-failsafe = &led_status_blue;
led-running = &led_power_orange;
led-upgrade = &led_status_blue;
};
leds {
compatible = "gpio-leds";
led_power_orange: power_orange {
label = "orange:power";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
};
2g_blue {
label = "blue:2g";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
2g_green {
label = "green:5g1";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
5g2_green {
label = "green:5g2";
gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy2tpt";
};
led_status_blue: status_blue {
label = "blue:status";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
ieee80211-freq-limit = <5470000 5875000>;
};

385
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts Normal file
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// SPDX-License-Identifier: ISC
// Copyright (c) 2015, The Linux Foundation. All rights reserved.
// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/soc/qcom,tcsr.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Cell C RTL30VW";
compatible = "cellc,rtl30vw";
aliases {
led-boot = &led_power_blue;
led-failsafe = &led_power_red;
led-running = &led_power_blue;
led-upgrade = &led_power_red;
};
chosen {
bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;
mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <2>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
led_power_blue: power_blue {
gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
label = "blue:power";
default-state = "on";
};
led_power_red: power_red {
gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
label = "red:power";
};
tp28 {
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
label = "ext:tp28";
default-state = "keep";
};
tp27 {
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
label = "ext:tp27";
default-state = "keep";
};
wlan2g {
gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
label = "blue:wlan2g";
linux,default-trigger = "phy0tpt";
};
wlan5g {
gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
label = "blue:wlan5g";
linux,default-trigger = "phy1tpt";
};
wps {
gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
label = "blue:wps";
};
voip {
gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
label = "blue:voip";
};
s1 {
gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
label = "blue:s1";
};
s2 {
gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
label = "blue:s2";
};
s3 {
gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
label = "blue:s3";
};
s4 {
gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
label = "blue:s4";
};
signal {
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
label = "red:signal";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
/*"n25q128a11" is required for proper nand recognition in u-boot. */
compatible = "jedec,spi-nor", "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
label = "0:BOOTCONFIG";
reg = <0x180000 0x10000>;
read-only;
};
};
};
flash@1 {
/*
* Factory U-boot looks in 0:BOOTCONFIG partition for active
* partitions settings and mangle partition config. So kernel
* /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
* It isn't a problem but we never can be sure where OFW put
* factory images. "spinand,mt29f" value is required for proper
* nand recognition in u-boot.
*/
compatible = "spi-nand","spinand,mt29f";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "rootfs";
reg = <0x400000 0x2000000>;
};
partition@2400000 {
label = "kernel_1";
reg = <0x2400000 0x400000>;
};
partition@2800000 {
label = "rootfs_1";
reg = <0x2800000 0x2000000>;
};
partition@4800000 {
label = "ubifs";
reg = <0x4800000 0x3800000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-u4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Unielec U4019 (32M)";
compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};

224
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
compatible = "unielec,u4019","qcom,ipq4019";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_status: led2 {
label = "green:led2";
gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial0-pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
led_pins: led_pinmux {
mux {
function = "gpio";
pins = "gpio68";
bias-disabled;
output-low;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Compex WPJ419";
compatible = "compex,wpj419", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
reserved-memory {
ranges;
rsvd1@87000000 {
/* Reserved for other subsystem */
reg = <0x87000000 0x500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
/* Reserved for other subsystem */
reg = <0x87B00000 0x500000>;
no-map;
};
};
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1 clk_ignore_unused";
};
soc {
pinctrl@1000000 {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
led_0_pins: led0_pinmux {
mux_1 {
pins = "gpio36";
function = "led0";
bias-pull-down;
};
mux_2 {
pins = "gpio40";
function = "led4";
bias-pull-down;
};
};
};
blsp_dma: dma@7884000 {
status = "okay";
};
spi_0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
num-cs = <2>;
flash0@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x040000 0x020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x060000 0x060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x0c0000 0x010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x0d0000 0x010000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0x0e0000 0x010000>;
};
partition@f0000 {
label = "u-boot";
reg = <0x0f0000 0x080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x010000>;
read-only;
};
};
};
nand@1 {
reg = <1>;
status = "okay";
compatible = "spi-nand";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* The device has 128MB, but we can only address
* 64MB because of the bootloader's default settings.
* This is due to the old mt29f driver,
* which detected the deivce with only 64MB
*/
partition@0 {
label = "ubi";
reg = <0x0000000 0x4000000>;
};
};
};
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
usb3_ss_phy: ssphy@9a000 {
status = "okay";
};
usb3_hs_phy: hsphy@a6000 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
usb2_hs_phy: hsphy@a8000 {
status = "okay";
};
usb2: usb2@60f8800 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x1e>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
qpic_bam: dma@7984000 {
status = "okay";
};
pcie0: pci@40000000 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

431
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts Normal file
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// SPDX-License-Identifier: ISC
/*
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Buffalo WTR-M2133HP";
compatible = "buffalo,wtr-m2133hp", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
chosen {
/*
* U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs" to
* kernel command line. But we use different partition names,
* so we have to set correct parameters.
*/
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
aliases {
led-boot = &led_power_blue;
led-failsafe = &led_power_orange;
led-running = &led_power_white;
led-upgrade = &led_power_blue;
label-mac-device = &gmac0;
};
soc {
rng@22000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x1c>;
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_power_white: power_white {
label = "white:power";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
};
led_power_orange: power_orange {
label = "orange:power";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
};
led_power_blue: power_blue {
label = "blue:power";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
router_white {
label = "white:router";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
};
router_orange {
label = "orange:router";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
internet_white {
label = "white:internet";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
};
internet_orange {
label = "orange:internet";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
wireless_white {
label = "white:wireless";
gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
};
wireless_orange {
label = "orange:wireless";
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
auto_mode {
label = "auto_mode";
gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
router_mode {
label = "router_mode";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
ap_mode {
label = "ap_mode";
gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_2>;
linux,input-type = <EV_SW>;
};
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "AOSS Button";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&tlmm {
serial_0_pins: serial0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
usb_power {
line-name = "USB power";
gpios = <34 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
};
};
};
&qpic_bam {
status = "okay";
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0000000 0x0100000>;
read-only;
};
partition@100000 {
label = "MIBIB";
reg = <0x0100000 0x0100000>;
read-only;
};
partition@200000 {
label = "BOOTCONFIG";
reg = <0x0200000 0x0100000>;
read-only;
};
partition@300000 {
label = "QSEE";
reg = <0x0300000 0x0100000>;
read-only;
};
partition@400000 {
label = "QSEE_1";
reg = <0x0400000 0x0100000>;
read-only;
};
partition@500000 {
label = "CDT";
reg = <0x0500000 0x0080000>;
read-only;
};
partition@580000 {
label = "CDT_1";
reg = <0x0580000 0x0080000>;
read-only;
};
partition@600000 {
label = "BOOTCONFIG1";
reg = <0x0600000 0x0080000>;
read-only;
};
partition@680000 {
label = "APPSBLENV";
reg = <0x0680000 0x0080000>;
};
partition@700000 {
label = "APPSBL";
reg = <0x0700000 0x0200000>;
read-only;
};
partition@900000 {
label = "APPSBL_1";
reg = <0x0900000 0x0200000>;
read-only;
};
art: partition@b00000 {
label = "ART";
reg = <0x0b00000 0x0080000>;
read-only;
};
partition@b80000 {
label = "ART_1";
reg = <0x0b80000 0x0080000>;
read-only;
};
orgdata: partition@c00000 {
label = "ORGDATA";
reg = <0x0c00000 0x0080000>;
read-only;
};
partition@c80000 {
label = "ORGDATA_1";
reg = <0x0c80000 0x0080000>;
read-only;
};
partition@d00000 {
label = "ubi";
reg = <0x0d00000 0x2900000>;
};
partition@3600000 {
label = "rootfs_recover";
reg = <0x3600000 0x2900000>;
read-only;
};
partition@5f00000 {
label = "user_property";
reg = <0x5f00000 0x1a20000>;
read-only;
};
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
ieee80211-freq-limit = <2400000 2483000>;
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
};
&gmac0 {
nvmem-cells = <&macaddr_orgdata_20>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_orgdata_20>;
nvmem-cell-names = "mac-address";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&orgdata {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_orgdata_20: macaddr@20 {
reg = <0x20 0x6>;
};
};

300
target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-xx8300.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for Linksys xx8300 (Dallas)
*
* Copyright (C) 2019 Jeff Kletsky
* Updated 2020 Hans Geiblinger
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
//
// OEM U-Boot provides either
// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
// root=ubi0:ubifs rootwait rw
// or the same with ubi.mtd=13,2048
//
/ {
chosen {
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "sbl1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "qsee";
reg = <0x200000 0x100000>;
read-only;
};
partition@300000 {
label = "cdt";
reg = <0x300000 0x80000>;
read-only;
};
partition@380000 {
label = "appsblenv";
reg = <0x380000 0x80000>;
read-only;
};
partition@400000 {
label = "ART";
reg = <0x400000 0x80000>;
read-only;
};
partition@480000 {
label = "appsbl";
reg = <0x480000 0x200000>;
read-only;
};
partition@680000 {
label = "u_env";
reg = <0x680000 0x80000>;
// writable -- U-Boot environment
};
partition@700000 {
label = "s_env";
reg = <0x700000 0x40000>;
// writable -- Boot counter records
};
partition@740000 {
label = "devinfo";
reg = <0x740000 0x40000>;
read-only;
};
partition@780000 {
label = "kernel";
reg = <0x780000 0x5800000>;
};
partition@a80000 {
label = "rootfs";
reg = <0xa80000 0x5500000>;
};
partition@5f80000 {
label = "alt_kernel";
reg = <0x5f80000 0x5800000>;
};
partition@6280000 {
label = "alt_rootfs";
reg = <0x6280000 0x5500000>;
};
partition@b780000 {
label = "sysdiag";
reg = <0xb780000 0x100000>;
read-only;
};
partition@b880000 {
label = "syscfg";
reg = <0xb880000 0x4680000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
serial_0_pins: serial0-pinmux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
// gpio61 controls led_usb
pulldowns {
pins = "gpio55", "gpio56", "gpio57",
"gpio60", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66",
"gpio67", "gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts Normal file
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Compex WPJ428";
compatible = "compex,wpj428";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &status;
led-failsafe = &status;
led-upgrade = &status;
};
leds {
compatible = "gpio-leds";
status: rss4 {
label = "green:rss4";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
rss3 {
label = "green:rss3";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
};
beeper: beeper {
compatible = "gpio-beeper";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition5@f0000 {
label = "0:APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition5@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition6@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x01e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Aruba AP-303";
compatible = "aruba,ap-303";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
};
leds {
compatible = "gpio-leds";
wifi_green {
label = "green:wifi";
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wifi_amber {
label = "amber:wifi";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 54 - out - active low to force HW reset
* 41 - out - active low to reset TPM
* 43 - out - active low to reset BLE radio
* 19 - in - active high when DC powered
*/
phy-reset {
line-name = "PHY-reset";
gpios = <42 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "ART";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0xf0000>;
read-only;
};
partition@1e0000 {
label = "mfginfo";
reg = <0x1e0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "apcd";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "osss";
reg = <0x200000 0x180000>;
read-only;
};
partition@380000 {
label = "appsblenv";
reg = <0x380000 0x10000>;
};
partition@390000 {
label = "pds";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
/* Called osss1 in smem */
label = "u-boot-env-bak";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
read-only;
};
};
};
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Aruba AP-303H";
compatible = "aruba,ap-303h";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_amber;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tpm@29 {
/* No Driver */
compatible = "atmel,at97sc3203";
reg = <0x29>;
read-only;
};
power-monitor@40 {
/* No driver */
compatible = "isl,isl28022";
reg = <0x40>;
};
};
};
leds {
compatible = "gpio-leds";
wifi_green {
label = "green:wifi";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wifi_amber {
label = "amber:wifi";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
pse {
label = "green:pse";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
};
led_system_amber: system_amber {
label = "amber:system";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
/* Texas Instruments CC2540T BLE radio */
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 39 - out - active low to force HW reset
* 32 - out - active low to reset TPM
* 43 - out - active low to reset BLE radio
* 41 - out - pulse to set warm reset status
* 34 - out - active low to enable PSE port
* 22 - in - active low when 802.3at powered
* 29 - in - active high when DC powered
* 40 - in - active low when reset due to cold HW reset
* 30 - in - active low when USB overcurrent detected
* 35 - in - interrupt line for power monitor chip
* 31 - in - active low when PSE port active
*/
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
drive-strength = <4>;
bias-disable;
};
};
serial_0_pins: serial_0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial_1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
usb-power {
line-name = "USB-power";
gpios = <23 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "appsblenv";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0x100000>;
read-only;
};
partition@1e0000 {
label = "ART";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "osss";
reg = <0x200000 0x170000>;
read-only;
};
partition@200000 {
label = "pds";
reg = <0x370000 0x10000>;
read-only;
};
partition@380000 {
label = "apcd";
reg = <0x380000 0x10000>;
read-only;
};
partition@390000 {
label = "mfginfo";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
/* Called osss1 in smem */
label = "u-boot-env-bak";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3c0000 0x40000>;
read-only;
};
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/* 'aos0' in Aruba firmware */
label = "aos0";
reg = <0x0 0x2000000>;
read-only;
};
partition@2000000 {
/* 'aos1' in Aruba firmware */
label = "ubi";
reg = <0x2000000 0x2000000>;
};
partition@4000000 {
label = "aruba-ubifs";
reg = <0x4000000 0x4000000>;
read-only;
};
};
};
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Aruba AP-365";
compatible = "aruba,ap-365";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
};
leds {
compatible = "gpio-leds";
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
system_amber {
label = "amber:system";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1000>;
always-running;
};
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 39 - out - pulse low to reset watchdog status flipflop
* 40 - out - active high to enable watchdog
* 41 - out - watchdog poke
* 42 - out - active low to reset BLE radio
* 43 - out - active low to reset TPM
* 47 - out - pulse low to reset warm reset status
* 54 - out - active low to force HW reset
* 18 - in - PHY interrupt line
* 45 - in - power monitor interrupt
* 48 - in - active low when cold reset
* 52 - in - active high when watchdog reset
*/
phy-reset {
line-name = "PHY-reset";
gpios = <42 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&i2c_0 {
power-monitor@40 {
/* No driver */
compatible = "isl,isl28022";
reg = <0x40>;
};
temperature-sensor@48 {
compatible = "adi,ad7416";
reg = <0x48>;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0xe0000 0x10000>;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0x100000>;
read-only;
};
partition@1f0000 {
label = "ART";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "osss";
reg = <0x200000 0x170000>;
read-only;
};
partition@370000 {
label = "pds";
reg = <0x370000 0x10000>;
read-only;
};
partition@380000 {
label = "apcd";
reg = <0x380000 0x10000>;
read-only;
};
partition@390000 {
label = "mfginfo";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "osss1";
reg = <0x3b0000 0x50000>;
read-only;
};
};
};
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@2;
/delete-node/ ethernet-phy@3;
/delete-node/ ethernet-phy@4;
/delete-node/ psgmii-phy@5;
ethernet-phy@5 {
reg = <0x5>;
};
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
qcom,single-phy;
qcom,num_gmac = <1>;
phy-mode = "rgmii-id";
status = "okay";
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tpm@29 {
/* No Driver */
compatible = "atmel,at97sc3203";
reg = <0x29>;
read-only;
};
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
/* Texas Instruments CC2540T BLE radio */
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <5>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c0";
drive-strength = <4>;
bias-disable;
};
};
serial_0_pins: serial_0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial_1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/* 'aos0' in Aruba firmware */
label = "aos0";
reg = <0x0 0x2000000>;
read-only;
};
partition@2000000 {
/* 'aos1' in Aruba firmware */
label = "ubi";
reg = <0x2000000 0x2000000>;
};
partition@4000000 {
label = "aruba-ubifs";
reg = <0x4000000 0x4000000>;
read-only;
};
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-B1300";
compatible = "glinet,gl-b1300";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x18>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power: power {
label = "green:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
mesh {
label = "green:mesh";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l25635f@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
MIBIB@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
QSEE@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
CDT@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
DDRPARAMS@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
APPSBLENV@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
APPSBL@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
ART@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B1300";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-S1300";
compatible = "glinet,gl-s1300";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x18>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "green:power";
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
mesh {
label = "green:mesh";
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
};
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
MIBIB@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
QSEE@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
CDT@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
DDRPARAMS@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
APPSBLENV@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
APPSBL@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
ART@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0xe80000>;
};
};
};
};
&blsp1_spi2 {
pinctrl-0 = <&spi_1_pins>;
pinctrl-names = "default";
status = "okay";
spidev1: spi@0 {
compatible = "siliconlabs,si3210";
reg = <0>;
spi-max-frequency = <24000000>;
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
};
pinconf {
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
spi_1_pins: spi_1_pinmux {
mux {
pins = "gpio44", "gpio46", "gpio47";
function = "blsp_spi1";
bias-disable;
};
host_int {
pins = "gpio42";
function = "gpio";
input;
};
cs {
pins = "gpio45";
function = "gpio";
bias-pull-up;
};
wake {
pins = "gpio40";
function = "gpio";
output-high;
};
reset {
pins = "gpio49";
function = "gpio";
output-high;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio28", "gpio29", "gpio30", "gpio31";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio32";
drive-strength = <10>;
bias-disable;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-S1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-S1300";
};

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-mr33.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for Meraki MR33 (Stinkbug)
*
* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
* Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
*
* Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Meraki MR33 Access Point";
compatible = "meraki,mr33";
aliases {
led-boot = &status_green;
led-failsafe = &status_red;
led-running = &status_green;
led-upgrade = &power_orange;
};
/* Do we really need this defined? */
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
/* It is a 56-bit counter that supplies the count to the ARM arch
timers and without upstream driver */
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "ti,cc2650";
enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
qcom,single-phy;
qcom,num_gmac = <1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power_orange: power {
label = "orange:power";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
panic-indicator;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <1>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
at24@50 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x50>;
read-only; /* This holds our MAC & Meraki board-data */
};
};
&blsp1_i2c4 {
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
led-controller@30 {
compatible = "ti,lp5562";
reg = <0x30>;
clock-mode = /bits/8 <2>;
enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
/* RGB led */
status_red: chan0 {
chan-name = "red:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
};
status_green: chan1 {
chan-name = "green:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
};
chan2 {
chan-name = "blue:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
};
chan3 {
chan-name = "white:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "sbl1";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "mibib";
reg = <0x00100000 0x00100000>;
read-only;
};
partition@200000 {
label = "bootconfig";
reg = <0x00200000 0x00100000>;
read-only;
};
partition@300000 {
label = "qsee";
reg = <0x00300000 0x00100000>;
read-only;
};
partition@400000 {
label = "qsee_alt";
reg = <0x00400000 0x00100000>;
read-only;
};
partition@500000 {
label = "cdt";
reg = <0x00500000 0x00080000>;
read-only;
};
partition@580000 {
label = "cdt_alt";
reg = <0x00580000 0x00080000>;
read-only;
};
partition@600000 {
label = "ddrparams";
reg = <0x00600000 0x00080000>;
read-only;
};
partition@700000 {
label = "u-boot";
reg = <0x00700000 0x00200000>;
read-only;
};
partition@900000 {
label = "u-boot-backup";
reg = <0x00900000 0x00200000>;
read-only;
};
partition@b00000 {
label = "ART";
reg = <0x00b00000 0x00080000>;
read-only;
};
partition@c00000 {
label = "ubi";
reg = <0x00c00000 0x07000000>;
/*
* Do not try to allocate the remaining
* 4 MiB to this ubi partition. It will
* confuse the u-boot and it might not
* find the kernel partition anymore.
*/
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
/*
* GPIO43 should be 0/1 whenever the unit is
* powered through PoE or AC-Adapter.
* That said, playing with this seems to
* reset the AP.
*/
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
/* We use the i2c-0 pins for serial_1 */
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
i2c_0_pins: i2c_0_pinmux {
pinmux {
function = "blsp_i2c0";
pins = "gpio20", "gpio21";
};
pinconf {
pins = "gpio20", "gpio21";
drive-strength = <16>;
bias-disable;
};
};
i2c_1_pins: i2c_1_pinmux {
pinmux {
function = "blsp_i2c1";
pins = "gpio34", "gpio35";
};
pinconf {
pins = "gpio34", "gpio35";
drive-strength = <16>;
bias-disable;
};
};
nand_pins: nand_pins {
/*
* There are 18 pins. 15 pins are common between LCD and NAND.
* The QPIC controller arbitrates between LCD and NAND. Of the
* remaining 4, 2 are for NAND and 2 are for LCD exclusively.
*
* The meraki source hints that the bluetooth module claims
* pin 52 as well. But sadly, there's no data whenever this
* is a NAND or LCD exclusive pin or not.
*/
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Meraki-MR33";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Meraki-MR33";
};

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#
## Makefile for the Qualcomm Atheros ethernet edma driver
#
obj-$(CONFIG_ESSEDMA) += essedma.o
essedma-objs := edma_axi.o edma.o edma_ethtool.o

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/*
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _EDMA_H_
#define _EDMA_H_
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/io.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/smp.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/sysctl.h>
#include <linux/phy.h>
#include <linux/of_net.h>
#include <net/checksum.h>
#include <net/ip6_checksum.h>
#include <asm-generic/bug.h>
#include "ess_edma.h"
#define EDMA_CPU_CORES_SUPPORTED 4
#define EDMA_MAX_PORTID_SUPPORTED 5
#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
#define EDMA_MAX_RECEIVE_QUEUE 8
#define EDMA_MAX_TRANSMIT_QUEUE 16
/* WAN/LAN adapter number */
#define EDMA_WAN 0
#define EDMA_LAN 1
/* VLAN tag */
#define EDMA_LAN_DEFAULT_VLAN 1
#define EDMA_WAN_DEFAULT_VLAN 2
#define EDMA_DEFAULT_GROUP1_VLAN 1
#define EDMA_DEFAULT_GROUP2_VLAN 2
#define EDMA_DEFAULT_GROUP3_VLAN 3
#define EDMA_DEFAULT_GROUP4_VLAN 4
#define EDMA_DEFAULT_GROUP5_VLAN 5
/* Queues exposed to linux kernel */
#define EDMA_NETDEV_TX_QUEUE 4
#define EDMA_NETDEV_RX_QUEUE 4
/* Number of queues per core */
#define EDMA_NUM_TXQ_PER_CORE 4
#define EDMA_NUM_RXQ_PER_CORE 2
#define EDMA_TPD_EOP_SHIFT 31
#define EDMA_PORT_ID_SHIFT 12
#define EDMA_PORT_ID_MASK 0x7
/* tpd word 3 bit 18-28 */
#define EDMA_TPD_PORT_BITMAP_SHIFT 18
#define EDMA_TPD_FROM_CPU_SHIFT 25
#define EDMA_FROM_CPU_MASK 0x80
#define EDMA_SKB_PRIORITY_MASK 0x38
/* TX/RX descriptor ring count */
/* should be a power of 2 */
#define EDMA_RX_RING_SIZE 128
#define EDMA_TX_RING_SIZE 128
/* Flags used in paged/non paged mode */
#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
#define EDMA_RX_HEAD_BUFF_SIZE 1540
/* MAX frame size supported by switch */
#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
/* Configurations */
#define EDMA_INTR_CLEAR_TYPE 0
#define EDMA_INTR_SW_IDX_W_TYPE 0
#define EDMA_FIFO_THRESH_TYPE 0
#define EDMA_RSS_TYPE 0
#define EDMA_RX_IMT 0x0020
#define EDMA_TX_IMT 0x0050
#define EDMA_TPD_BURST 5
#define EDMA_TXF_BURST 0x100
#define EDMA_RFD_BURST 8
#define EDMA_RFD_THR 16
#define EDMA_RFD_LTHR 0
/* RX/TX per CPU based mask/shift */
#define EDMA_TX_PER_CPU_MASK 0xF
#define EDMA_RX_PER_CPU_MASK 0x3
#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
#define EDMA_TX_CPU_START_SHIFT 0x2
#define EDMA_RX_CPU_START_SHIFT 0x1
/* FLags used in transmit direction */
#define EDMA_HW_CHECKSUM 0x00000001
#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
#define EDMA_SW_DESC_FLAG_LAST 0x1
#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
/* Ethtool specific list of EDMA supported features */
#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
| SUPPORTED_10baseT_Full \
| SUPPORTED_100baseT_Half \
| SUPPORTED_100baseT_Full \
| SUPPORTED_1000baseT_Full)
/* Recevie side atheros Header */
#define EDMA_RX_ATH_HDR_VERSION 0x2
#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
/* Transmit side atheros Header */
#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
#define EDMA_TXQ_START_CORE0 8
#define EDMA_TXQ_START_CORE1 12
#define EDMA_TXQ_START_CORE2 0
#define EDMA_TXQ_START_CORE3 4
#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
#define EDMA_ETH_HDR_LEN 12
#define EDMA_ETH_TYPE_MASK 0xFFFF
#define EDMA_RX_BUFFER_WRITE 16
#define EDMA_RFD_AVAIL_THR 80
#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
__be16 sport, __be16 dport,
uint8_t proto, u16 loadbalance, bool action);
struct edma_ethtool_statistics {
u32 tx_q0_pkt;
u32 tx_q1_pkt;
u32 tx_q2_pkt;
u32 tx_q3_pkt;
u32 tx_q4_pkt;
u32 tx_q5_pkt;
u32 tx_q6_pkt;
u32 tx_q7_pkt;
u32 tx_q8_pkt;
u32 tx_q9_pkt;
u32 tx_q10_pkt;
u32 tx_q11_pkt;
u32 tx_q12_pkt;
u32 tx_q13_pkt;
u32 tx_q14_pkt;
u32 tx_q15_pkt;
u32 tx_q0_byte;
u32 tx_q1_byte;
u32 tx_q2_byte;
u32 tx_q3_byte;
u32 tx_q4_byte;
u32 tx_q5_byte;
u32 tx_q6_byte;
u32 tx_q7_byte;
u32 tx_q8_byte;
u32 tx_q9_byte;
u32 tx_q10_byte;
u32 tx_q11_byte;
u32 tx_q12_byte;
u32 tx_q13_byte;
u32 tx_q14_byte;
u32 tx_q15_byte;
u32 rx_q0_pkt;
u32 rx_q1_pkt;
u32 rx_q2_pkt;
u32 rx_q3_pkt;
u32 rx_q4_pkt;
u32 rx_q5_pkt;
u32 rx_q6_pkt;
u32 rx_q7_pkt;
u32 rx_q0_byte;
u32 rx_q1_byte;
u32 rx_q2_byte;
u32 rx_q3_byte;
u32 rx_q4_byte;
u32 rx_q5_byte;
u32 rx_q6_byte;
u32 rx_q7_byte;
u32 tx_desc_error;
u32 rx_alloc_fail_ctr;
};
struct edma_mdio_data {
struct mii_bus *mii_bus;
void __iomem *membase;
int phy_irq[PHY_MAX_ADDR];
};
/* EDMA LINK state */
enum edma_link_state {
__EDMA_LINKUP, /* Indicate link is UP */
__EDMA_LINKDOWN /* Indicate link is down */
};
/* EDMA GMAC state */
enum edma_gmac_state {
__EDMA_UP /* use to indicate GMAC is up */
};
/* edma transmit descriptor */
struct edma_tx_desc {
__le16 len; /* full packet including CRC */
__le16 svlan_tag; /* vlan tag */
__le32 word1; /* byte 4-7 */
__le32 addr; /* address of buffer */
__le32 word3; /* byte 12 */
};
/* edma receive return descriptor */
struct edma_rx_return_desc {
u16 rrd0;
u16 rrd1;
u16 rrd2;
u16 rrd3;
u16 rrd4;
u16 rrd5;
u16 rrd6;
u16 rrd7;
};
/* RFD descriptor */
struct edma_rx_free_desc {
__le32 buffer_addr; /* buffer address */
};
/* edma hw specific data */
struct edma_hw {
u32 __iomem *hw_addr; /* inner register address */
struct edma_adapter *adapter; /* netdevice adapter */
u32 rx_intr_mask; /*rx interrupt mask */
u32 tx_intr_mask; /* tx interrupt nask */
u32 misc_intr_mask; /* misc interrupt mask */
u32 wol_intr_mask; /* wake on lan interrupt mask */
bool intr_clear_type; /* interrupt clear */
bool intr_sw_idx_w; /* interrupt software index */
u32 rx_head_buff_size; /* Rx buffer size */
u8 rss_type; /* rss protocol type */
};
/* edma_sw_desc stores software descriptor
* SW descriptor has 1:1 map with HW descriptor
*/
struct edma_sw_desc {
struct sk_buff *skb;
dma_addr_t dma; /* dma address */
u16 length; /* Tx/Rx buffer length */
u32 flags;
};
/* per core related information */
struct edma_per_cpu_queues_info {
struct napi_struct napi; /* napi associated with the core */
u32 tx_mask; /* tx interrupt mask */
u32 rx_mask; /* rx interrupt mask */
u32 tx_status; /* tx interrupt status */
u32 rx_status; /* rx interrupt status */
u32 tx_start; /* tx queue start */
u32 rx_start; /* rx queue start */
struct edma_common_info *edma_cinfo; /* edma common info */
};
/* edma specific common info */
struct edma_common_info {
struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
struct platform_device *pdev; /* device structure */
struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
struct ctl_table_header *edma_ctl_table_hdr;
int num_gmac;
struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
int num_rx_queues; /* number of rx queue */
u32 num_tx_queues; /* number of tx queue */
u32 tx_irq[16]; /* number of tx irq */
u32 rx_irq[8]; /* number of rx irq */
u32 from_cpu; /* from CPU TPD field */
u32 num_rxq_per_core; /* Rx queues per core */
u32 num_txq_per_core; /* Tx queues per core */
u16 tx_ring_count; /* Tx ring count */
u16 rx_ring_count; /* Rx ring*/
u16 rx_head_buffer_len; /* rx buffer length */
u16 rx_page_buffer_len; /* rx buffer length */
u32 page_mode; /* Jumbo frame supported flag */
u32 fraglist_mode; /* fraglist supported flag */
struct edma_hw hw; /* edma hw specific structure */
struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
spinlock_t stats_lock; /* protect edma stats area for updation */
struct timer_list edma_stats_timer;
bool is_single_phy;
void __iomem *ess_hw_addr;
struct clk *ess_clk;
};
/* transimit packet descriptor (tpd) ring */
struct edma_tx_desc_ring {
struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
/* Array of netdevs associated with the tpd ring */
void *hw_desc; /* descriptor ring virtual address */
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
int netdev_bmp; /* Bitmap for per-ring netdevs */
u32 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
dma_addr_t dma; /* descriptor ring physical address */
u16 sw_next_to_fill; /* next Tx descriptor to fill */
u16 sw_next_to_clean; /* next Tx descriptor to clean */
};
/* receive free descriptor (rfd) ring */
struct edma_rfd_desc_ring {
void *hw_desc; /* descriptor ring virtual address */
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
u16 size; /* bytes allocated to sw_desc */
u16 count; /* number of descriptors in the ring */
dma_addr_t dma; /* descriptor ring physical address */
u16 sw_next_to_fill; /* next descriptor to fill */
u16 sw_next_to_clean; /* next descriptor to clean */
u16 pending_fill; /* fill pending from previous iteration */
};
/* edma_rfs_flter_node - rfs filter node in hash table */
struct edma_rfs_filter_node {
struct flow_keys keys;
u32 flow_id; /* flow_id of filter provided by kernel */
u16 filter_id; /* filter id of filter returned by adaptor */
u16 rq_id; /* desired rq index */
struct hlist_node node; /* edma rfs list node */
};
/* edma_rfs_flow_tbl - rfs flow table */
struct edma_rfs_flow_table {
u16 max_num_filter; /* Maximum number of filters edma supports */
u16 hashtoclean; /* hash table index to clean next */
int filter_available; /* Number of free filters available */
struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
spinlock_t rfs_ftab_lock;
struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
};
/* EDMA net device structure */
struct edma_adapter {
struct net_device *netdev; /* netdevice */
struct platform_device *pdev; /* platform device */
struct edma_common_info *edma_cinfo; /* edma common info */
struct phy_device *phydev; /* Phy device */
struct edma_rfs_flow_table rfs; /* edma rfs flow table */
struct net_device_stats stats; /* netdev statistics */
set_rfs_filter_callback_t set_rfs_rule;
u32 flags;/* status flags */
unsigned long state_flags; /* GMAC up/down flags */
u32 forced_speed; /* link force speed */
u32 forced_duplex; /* link force duplex */
u32 link_state; /* phy link state */
u32 phy_mdio_addr; /* PHY device address on MII interface */
u32 poll_required; /* check if link polling is required */
u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
u32 default_vlan_tag; /* vlan tag */
u32 dp_bitmap;
uint8_t phy_id[MII_BUS_ID_SIZE + 3];
};
int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
int edma_open(struct net_device *netdev);
int edma_close(struct net_device *netdev);
void edma_free_tx_resources(struct edma_common_info *edma_c_info);
void edma_free_rx_resources(struct edma_common_info *edma_c_info);
int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
void edma_free_queues(struct edma_common_info *edma_cinfo);
void edma_irq_disable(struct edma_common_info *edma_cinfo);
int edma_reset(struct edma_common_info *edma_cinfo);
int edma_poll(struct napi_struct *napi, int budget);
netdev_tx_t edma_xmit(struct sk_buff *skb,
struct net_device *netdev);
int edma_configure(struct edma_common_info *edma_cinfo);
void edma_irq_enable(struct edma_common_info *edma_cinfo);
void edma_enable_tx_ctrl(struct edma_hw *hw);
void edma_enable_rx_ctrl(struct edma_hw *hw);
void edma_stop_rx_tx(struct edma_hw *hw);
void edma_free_irqs(struct edma_adapter *adapter);
irqreturn_t edma_interrupt(int irq, void *dev);
void edma_write_reg(u16 reg_addr, u32 reg_value);
void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
struct net_device_stats *edma_get_stats(struct net_device *netdev);
int edma_set_mac_addr(struct net_device *netdev, void *p);
int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
u16 rxq, u32 flow_id);
int edma_register_rfs_filter(struct net_device *netdev,
set_rfs_filter_callback_t set_filter);
void edma_flow_may_expire(struct timer_list *t);
void edma_set_ethtool_ops(struct net_device *netdev);
void edma_set_stp_rstp(bool tag);
void edma_assign_ath_hdr_type(int tag);
int edma_get_default_vlan_tag(struct net_device *netdev);
void edma_adjust_link(struct net_device *netdev);
int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
void edma_read_append_stats(struct edma_common_info *edma_cinfo);
void edma_change_tx_coalesce(int usecs);
void edma_change_rx_coalesce(int usecs);
void edma_get_tx_rx_coalesce(u32 *reg_val);
void edma_clear_irq_status(void);
void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
struct phy_device *phydev, uint8_t port_id);
#endif /* _EDMA_H_ */

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/*
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/string.h>
#include <linux/version.h>
#include "edma.h"
struct edma_ethtool_stats {
uint8_t stat_string[ETH_GSTRING_LEN];
uint32_t stat_offset;
};
#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
#define DRVINFO_LEN 32
/* Array of strings describing statistics
*/
static const struct edma_ethtool_stats edma_gstrings_stats[] = {
{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
{"tx_desc_error", EDMA_STAT(tx_desc_error)},
{"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
};
#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
/* edma_get_strset_count()
* Get strset count
*/
static int edma_get_strset_count(struct net_device *netdev,
int sset)
{
switch (sset) {
case ETH_SS_STATS:
return EDMA_STATS_LEN;
default:
netdev_dbg(netdev, "%s: Invalid string set", __func__);
return -EOPNOTSUPP;
}
}
/* edma_get_strings()
* get stats string
*/
static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
uint8_t *data)
{
uint8_t *p = data;
uint32_t i;
switch (stringset) {
case ETH_SS_STATS:
for (i = 0; i < EDMA_STATS_LEN; i++) {
memcpy(p, edma_gstrings_stats[i].stat_string,
min((size_t)ETH_GSTRING_LEN,
strlen(edma_gstrings_stats[i].stat_string)
+ 1));
p += ETH_GSTRING_LEN;
}
break;
}
}
/* edma_get_ethtool_stats()
* Get ethtool statistics
*/
static void edma_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *stats, uint64_t *data)
{
struct edma_adapter *adapter = netdev_priv(netdev);
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
int i;
uint8_t *p = NULL;
edma_read_append_stats(edma_cinfo);
for(i = 0; i < EDMA_STATS_LEN; i++) {
p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
edma_gstrings_stats[i].stat_offset;
data[i] = *(uint32_t *)p;
}
}
/* edma_get_drvinfo()
* get edma driver info
*/
static void edma_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
}
/* edma_nway_reset()
* Reset the phy, if available.
*/
static int edma_nway_reset(struct net_device *netdev)
{
return -EINVAL;
}
/* edma_get_wol()
* get wake on lan info
*/
static void edma_get_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
wol->supported = 0;
wol->wolopts = 0;
}
/* edma_get_msglevel()
* get message level.
*/
static uint32_t edma_get_msglevel(struct net_device *netdev)
{
return 0;
}
/* edma_get_settings()
* Get edma settings
*/
static int edma_get_settings(struct net_device *netdev,
struct ethtool_link_ksettings *cmd)
{
struct edma_adapter *adapter = netdev_priv(netdev);
if (adapter->poll_required) {
if ((adapter->forced_speed != SPEED_UNKNOWN)
&& !(adapter->poll_required))
return -EPERM;
phy_ethtool_ksettings_get(adapter->phydev, cmd);
if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, adapter->phydev->advertising))
cmd->base.port = PORT_FIBRE;
else
cmd->base.port = PORT_TP;
} else {
/* If the speed/duplex for this GMAC is forced and we
* are not polling for link state changes, return the
* values as specified by platform. This will be true
* for GMACs connected to switch, and interfaces that
* do not use a PHY.
*/
if (!(adapter->poll_required)) {
if (adapter->forced_speed != SPEED_UNKNOWN) {
/* set speed and duplex */
cmd->base.speed = SPEED_1000;
cmd->base.duplex = DUPLEX_FULL;
/* Populate capabilities advertised by self */
linkmode_zero(cmd->link_modes.advertising);
cmd->base.autoneg = 0;
cmd->base.port = PORT_TP;
cmd->base.transceiver = XCVR_EXTERNAL;
} else {
/* non link polled and non
* forced speed/duplex interface
*/
return -EIO;
}
}
}
return 0;
}
/* edma_set_settings()
* Set EDMA settings
*/
static int edma_set_settings(struct net_device *netdev,
const struct ethtool_link_ksettings *cmd)
{
struct edma_adapter *adapter = netdev_priv(netdev);
if ((adapter->forced_speed != SPEED_UNKNOWN) &&
!adapter->poll_required)
return -EPERM;
return phy_ethtool_ksettings_set(adapter->phydev, cmd);
}
/* edma_get_coalesce
* get interrupt mitigation
*/
static int edma_get_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ec)
{
u32 reg_val;
edma_get_tx_rx_coalesce(&reg_val);
/* We read the Interrupt Moderation Timer(IMT) register value,
* use lower 16 bit for rx and higher 16 bit for Tx. We do a
* left shift by 1, because IMT resolution timer is 2usecs.
* Hence the value given by the register is multiplied by 2 to
* get the actual time in usecs.
*/
ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
return 0;
}
/* edma_set_coalesce
* set interrupt mitigation
*/
static int edma_set_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ec)
{
if (ec->tx_coalesce_usecs)
edma_change_tx_coalesce(ec->tx_coalesce_usecs);
if (ec->rx_coalesce_usecs)
edma_change_rx_coalesce(ec->rx_coalesce_usecs);
return 0;
}
/* edma_set_priv_flags()
* Set EDMA private flags
*/
static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
{
return 0;
}
/* edma_get_priv_flags()
* get edma driver flags
*/
static u32 edma_get_priv_flags(struct net_device *netdev)
{
return 0;
}
/* edma_get_ringparam()
* get ring size
*/
static void edma_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct edma_adapter *adapter = netdev_priv(netdev);
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
ring->tx_max_pending = edma_cinfo->tx_ring_count;
ring->rx_max_pending = edma_cinfo->rx_ring_count;
}
/* Ethtool operations
*/
static const struct ethtool_ops edma_ethtool_ops = {
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,7,0)
.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
#endif
.get_drvinfo = &edma_get_drvinfo,
.get_link = &ethtool_op_get_link,
.get_msglevel = &edma_get_msglevel,
.nway_reset = &edma_nway_reset,
.get_wol = &edma_get_wol,
.get_link_ksettings = &edma_get_settings,
.set_link_ksettings = &edma_set_settings,
.get_strings = &edma_get_strings,
.get_sset_count = &edma_get_strset_count,
.get_ethtool_stats = &edma_get_ethtool_stats,
.get_coalesce = &edma_get_coalesce,
.set_coalesce = &edma_set_coalesce,
.get_priv_flags = edma_get_priv_flags,
.set_priv_flags = edma_set_priv_flags,
.get_ringparam = edma_get_ringparam,
};
/* edma_set_ethtool_ops
* Set ethtool operations
*/
void edma_set_ethtool_ops(struct net_device *netdev)
{
netdev->ethtool_ops = &edma_ethtool_ops;
}

389
target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/ess_edma.h Normal file
View File

@@ -0,0 +1,389 @@
/*
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ESS_EDMA_H_
#define _ESS_EDMA_H_
#include <linux/types.h>
struct edma_adapter;
struct edma_hw;
/* register definition */
#define EDMA_REG_MAS_CTRL 0x0
#define EDMA_REG_TIMEOUT_CTRL 0x004
#define EDMA_REG_DBG0 0x008
#define EDMA_REG_DBG1 0x00C
#define EDMA_REG_SW_CTRL0 0x100
#define EDMA_REG_SW_CTRL1 0x104
/* Interrupt Status Register */
#define EDMA_REG_RX_ISR 0x200
#define EDMA_REG_TX_ISR 0x208
#define EDMA_REG_MISC_ISR 0x210
#define EDMA_REG_WOL_ISR 0x218
#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
#define EDMA_WOL_ISR 0x00000001
/* Interrupt Mask Register */
#define EDMA_REG_MISC_IMR 0x214
#define EDMA_REG_WOL_IMR 0x218
#define EDMA_RX_IMR_NORMAL_MASK 0x1
#define EDMA_TX_IMR_NORMAL_MASK 0x1
#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
#define EDMA_WOL_IMR_NORMAL_MASK 0x1
/* Edma receive consumer index */
#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
/* Edma transmit consumer index */
#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
/* IRQ Moderator Initial Timer Register */
#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
/* Interrupt Control Register */
#define EDMA_REG_INTR_CTRL 0x284
#define EDMA_INTR_CLR_TYP_SHIFT 0
#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
#define EDMA_INTR_CLEAR_TYPE_W1 0
#define EDMA_INTR_CLEAR_TYPE_R 1
/* RX Interrupt Mask Register */
#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
/* TX Interrupt mask register */
#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
/* Load Ptr Register
* Software sets this bit after the initialization of the head and tail
*/
#define EDMA_REG_TX_SRAM_PART 0x400
#define EDMA_LOAD_PTR_SHIFT 16
/* TXQ Control Register */
#define EDMA_REG_TXQ_CTRL 0x404
#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
#define EDMA_TXQ_CTRL_TXQ_EN 0x20
#define EDMA_TXQ_CTRL_ENH_MODE 0x40
#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
/* WRR Control Register */
#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
/* Weight round robin(WRR), it takes queue as input, and computes
* starting bits where we need to write the weight for a particular
* queue
*/
#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
/* Tx Descriptor Control Register */
#define EDMA_REG_TPD_RING_SIZE 0x41C
#define EDMA_TPD_RING_SIZE_SHIFT 0
#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
/* Transmit descriptor base address */
#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
/* TPD Index Register */
#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
#define EDMA_TPD_PROD_IDX_SHIFT 0
#define EDMA_TPD_CONS_IDX_SHIFT 16
/* TX Virtual Queue Mapping Control Register */
#define EDMA_REG_VQ_CTRL0 0x4A0
#define EDMA_REG_VQ_CTRL1 0x4A4
/* Virtual QID shift, it takes queue as input, and computes
* Virtual QID position in virtual qid control register
*/
#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
/* Virtual Queue Default Value */
#define EDMA_VQ_REG_VALUE 0x240240
/* Tx side Port Interface Control Register */
#define EDMA_REG_PORT_CTRL 0x4A8
#define EDMA_PAD_EN_SHIFT 15
/* Tx side VLAN Configuration Register */
#define EDMA_REG_VLAN_CFG 0x4AC
#define EDMA_TX_CVLAN 16
#define EDMA_TX_INS_CVLAN 17
#define EDMA_TX_CVLAN_TAG_SHIFT 0
#define EDMA_TX_SVLAN 14
#define EDMA_TX_INS_SVLAN 15
#define EDMA_TX_SVLAN_TAG_SHIFT 16
/* Tx Queue Packet Statistic Register */
#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
/* Tx Queue Byte Statistic Register */
#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
/* Load Balance Based Ring Offset Register */
#define EDMA_REG_LB_RING 0x800
#define EDMA_LB_RING_ENTRY_MASK 0xff
#define EDMA_LB_RING_ID_MASK 0x7
#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
#define EDMA_LB_RING_ID_OFFSET 0
#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
#define EDMA_LB_REG_VALUE 0x6040200
/* Load Balance Priority Mapping Register */
#define EDMA_REG_LB_PRI_START 0x804
#define EDMA_REG_LB_PRI_END 0x810
#define EDMA_LB_PRI_REG_INC 4
#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
#define EDMA_LB_PRI_ENTRY_MASK 0xf
/* RSS Priority Mapping Register */
#define EDMA_REG_RSS_PRI 0x820
#define EDMA_RSS_PRI_ENTRY_MASK 0xf
#define EDMA_RSS_RING_ID_MASK 0x7
#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
/* RSS Indirection Register */
#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
#define EDMA_NUM_IDT 16
#define EDMA_RSS_IDT_VALUE 0x64206420
/* Default RSS Ring Register */
#define EDMA_REG_DEF_RSS 0x890
#define EDMA_DEF_RSS_MASK 0x7
/* RSS Hash Function Type Register */
#define EDMA_REG_RSS_TYPE 0x894
#define EDMA_RSS_TYPE_NONE 0x01
#define EDMA_RSS_TYPE_IPV4TCP 0x02
#define EDMA_RSS_TYPE_IPV6_TCP 0x04
#define EDMA_RSS_TYPE_IPV4_UDP 0x08
#define EDMA_RSS_TYPE_IPV6UDP 0x10
#define EDMA_RSS_TYPE_IPV4 0x20
#define EDMA_RSS_TYPE_IPV6 0x40
#define EDMA_RSS_HASH_MODE_MASK 0x7f
#define EDMA_REG_RSS_HASH_VALUE 0x8C0
#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
#define EDMA_HASH_TYPE_START 0
#define EDMA_HASH_TYPE_END 5
#define EDMA_HASH_TYPE_SHIFT 12
#define EDMA_RFS_FLOW_ENTRIES 1024
#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
/* RFD Base Address Register */
#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
/* RFD Index Register */
#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
#define EDMA_RFD_PROD_IDX_MASK 0xFFF
#define EDMA_RFD_CONS_IDX_MASK 0xFFF
#define EDMA_RFD_PROD_IDX_SHIFT 0
#define EDMA_RFD_CONS_IDX_SHIFT 16
/* Rx Descriptor Control Register */
#define EDMA_REG_RX_DESC0 0xA10
#define EDMA_RFD_RING_SIZE_MASK 0xFFF
#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
#define EDMA_RFD_RING_SIZE_SHIFT 0
#define EDMA_RX_BUF_SIZE_SHIFT 16
#define EDMA_REG_RX_DESC1 0xA14
#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
/* RXQ Control Register */
#define EDMA_REG_RXQ_CTRL 0xA18
#define EDMA_FIFO_THRESH_TYPE_SHIF 0
#define EDMA_FIFO_THRESH_128_BYTE 0x0
#define EDMA_FIFO_THRESH_64_BYTE 0x1
#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
#define EDMA_RXQ_CTRL_EN 0x0000FF00
/* AXI Burst Size Config */
#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
/* Rx Statistics Register */
#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
/* WoL Pattern Length Register */
#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
#define EDMA_WOL_PT_LEN_MASK 0xFF
#define EDMA_WOL_PT0_LEN_SHIFT 0
#define EDMA_WOL_PT1_LEN_SHIFT 8
#define EDMA_WOL_PT2_LEN_SHIFT 16
#define EDMA_WOL_PT3_LEN_SHIFT 24
#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
#define EDMA_WOL_PT4_LEN_SHIFT 0
#define EDMA_WOL_PT5_LEN_SHIFT 8
#define EDMA_WOL_PT6_LEN_SHIFT 16
/* WoL Control Register */
#define EDMA_REG_WOL_CTRL 0xC08
#define EDMA_WOL_WK_EN 0x00000001
#define EDMA_WOL_MG_EN 0x00000002
#define EDMA_WOL_PT0_EN 0x00000004
#define EDMA_WOL_PT1_EN 0x00000008
#define EDMA_WOL_PT2_EN 0x00000010
#define EDMA_WOL_PT3_EN 0x00000020
#define EDMA_WOL_PT4_EN 0x00000040
#define EDMA_WOL_PT5_EN 0x00000080
#define EDMA_WOL_PT6_EN 0x00000100
/* MAC Control Register */
#define EDMA_REG_MAC_CTRL0 0xC20
#define EDMA_REG_MAC_CTRL1 0xC24
/* WoL Pattern Register */
#define EDMA_REG_WOL_PATTERN_START 0x5000
#define EDMA_PATTERN_PART_REG_OFFSET 0x40
/* TX descriptor fields */
#define EDMA_TPD_HDR_SHIFT 0
#define EDMA_TPD_PPPOE_EN 0x00000100
#define EDMA_TPD_IP_CSUM_EN 0x00000200
#define EDMA_TPD_TCP_CSUM_EN 0x0000400
#define EDMA_TPD_UDP_CSUM_EN 0x00000800
#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
#define EDMA_TPD_LSO_EN 0x00001000
#define EDMA_TPD_LSO_V2_EN 0x00002000
#define EDMA_TPD_IPV4_EN 0x00010000
#define EDMA_TPD_MSS_MASK 0x1FFF
#define EDMA_TPD_MSS_SHIFT 18
#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
/* RRD descriptor fields */
#define EDMA_RRD_NUM_RFD_MASK 0x000F
#define EDMA_RRD_SVLAN 0x8000
#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
#define EDMA_RRD_CVLAN 0x0001
#define EDMA_RRD_DESC_VALID 0x8000
#define EDMA_RRD_PRIORITY_SHIFT 4
#define EDMA_RRD_PRIORITY_MASK 0x7
#define EDMA_RRD_PORT_TYPE_SHIFT 7
#define EDMA_RRD_PORT_TYPE_MASK 0x1F
#define ESS_RGMII_CTRL 0x0004
/* Port status registers */
#define ESS_PORT0_STATUS 0x007C
#define ESS_PORT1_STATUS 0x0080
#define ESS_PORT2_STATUS 0x0084
#define ESS_PORT3_STATUS 0x0088
#define ESS_PORT4_STATUS 0x008C
#define ESS_PORT5_STATUS 0x0090
#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
#define ESS_PORT_STATUS_RX_MAC_EN 0x08
#define ESS_PORT_STATUS_TX_MAC_EN 0x04
#define ESS_PORT_STATUS_SPEED_INV 0x03
#define ESS_PORT_STATUS_SPEED_1000 0x02
#define ESS_PORT_STATUS_SPEED_100 0x01
#define ESS_PORT_STATUS_SPEED_10 0x00
#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
#define PHY_STATUS_REG 0x11
#define PHY_STATUS_SPEED 0xC000
#define PHY_STATUS_SPEED_SHIFT 14
#define PHY_STATUS_DUPLEX 0x2000
#define PHY_STATUS_DUPLEX_SHIFT 13
#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
#define PHY_STATUS_CARRIER 0x0400
#define PHY_STATUS_CARRIER_SHIFT 10
/* Port lookup control registers */
#define ESS_PORT0_LOOKUP_CTRL 0x0660
#define ESS_PORT1_LOOKUP_CTRL 0x066C
#define ESS_PORT2_LOOKUP_CTRL 0x0678
#define ESS_PORT3_LOOKUP_CTRL 0x0684
#define ESS_PORT4_LOOKUP_CTRL 0x0690
#define ESS_PORT5_LOOKUP_CTRL 0x069C
#define ESS_PORT0_HEADER_CTRL 0x009C
#define ESS_PORTS_ALL 0x3f
#define ESS_FWD_CTRL1 0x0624
#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define ESS_FWD_CTRL1_UC_FLOOD_S 0
#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define ESS_FWD_CTRL1_MC_FLOOD_S 8
#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define ESS_FWD_CTRL1_BC_FLOOD_S 16
#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
#define ESS_FWD_CTRL1_IGMP_S 24
#endif /* _ESS_EDMA_H_ */

829
target/linux/ipq40xx/files/drivers/net/phy/qca807x.c Normal file
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@@ -0,0 +1,829 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2020 Sartura Ltd.
*
* Author: Robert Marko <robert.marko@sartura.hr>
*
* Qualcomm QCA8072 and QCA8075 PHY driver
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/bitfield.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
#include <linux/ethtool_netlink.h>
#endif
#include <linux/gpio.h>
#include <linux/sfp.h>
#include <dt-bindings/net/qcom-qca807x.h>
#define PHY_ID_QCA8072 0x004dd0b2
#define PHY_ID_QCA8075 0x004dd0b1
#define PHY_ID_QCA807X_PSGMII 0x06820805
/* Downshift */
#define QCA807X_SMARTSPEED_EN BIT(5)
#define QCA807X_SMARTSPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
#define QCA807X_SMARTSPEED_RETRY_LIMIT_DEFAULT 5
#define QCA807X_SMARTSPEED_RETRY_LIMIT_MIN 2
#define QCA807X_SMARTSPEED_RETRY_LIMIT_MAX 9
/* Cable diagnostic test (CDT) */
#define QCA807X_CDT 0x16
#define QCA807X_CDT_ENABLE BIT(15)
#define QCA807X_CDT_ENABLE_INTER_PAIR_SHORT BIT(13)
#define QCA807X_CDT_STATUS BIT(11)
#define QCA807X_CDT_MMD3_STATUS 0x8064
#define QCA807X_CDT_MDI0_STATUS_MASK GENMASK(15, 12)
#define QCA807X_CDT_MDI1_STATUS_MASK GENMASK(11, 8)
#define QCA807X_CDT_MDI2_STATUS_MASK GENMASK(7, 4)
#define QCA807X_CDT_MDI3_STATUS_MASK GENMASK(3, 0)
#define QCA807X_CDT_RESULTS_INVALID 0x0
#define QCA807X_CDT_RESULTS_OK 0x1
#define QCA807X_CDT_RESULTS_OPEN 0x2
#define QCA807X_CDT_RESULTS_SAME_SHORT 0x3
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK 0x4
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK 0x8
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK 0xc
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN 0x6
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN 0xa
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN 0xe
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT 0x7
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT 0xb
#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT 0xf
#define QCA807X_CDT_RESULTS_BUSY 0x9
#define QCA807X_CDT_MMD3_MDI0_LENGTH 0x8065
#define QCA807X_CDT_MMD3_MDI1_LENGTH 0x8066
#define QCA807X_CDT_MMD3_MDI2_LENGTH 0x8067
#define QCA807X_CDT_MMD3_MDI3_LENGTH 0x8068
#define QCA807X_CDT_SAME_SHORT_LENGTH_MASK GENMASK(15, 8)
#define QCA807X_CDT_CROSS_SHORT_LENGTH_MASK GENMASK(7, 0)
#define QCA807X_CHIP_CONFIGURATION 0x1f
#define QCA807X_BT_BX_REG_SEL BIT(15)
#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK GENMASK(3, 0)
#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII 4
#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER 3
#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER 0
#define QCA807X_MEDIA_SELECT_STATUS 0x1a
#define QCA807X_MEDIA_DETECTED_COPPER BIT(5)
#define QCA807X_MEDIA_DETECTED_1000_BASE_X BIT(4)
#define QCA807X_MEDIA_DETECTED_100_BASE_FX BIT(3)
#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION 0x807e
#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN BIT(0)
#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a
#define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0)
#define QCA807X_MMD7_LED_100N_1 0x8074
#define QCA807X_MMD7_LED_100N_2 0x8075
#define QCA807X_MMD7_LED_1000N_1 0x8076
#define QCA807X_MMD7_LED_1000N_2 0x8077
#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10)
#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9)
#define QCA807X_LED_GT_ON_EN_2 BIT(6)
#define QCA807X_LED_HT_ON_EN_2 BIT(5)
#define QCA807X_LED_BT_ON_EN_2 BIT(4)
#define QCA807X_GPIO_FORCE_EN BIT(15)
#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13)
#define QCA807X_INTR_ENABLE 0x12
#define QCA807X_INTR_STATUS 0x13
#define QCA807X_INTR_ENABLE_AUTONEG_ERR BIT(15)
#define QCA807X_INTR_ENABLE_SPEED_CHANGED BIT(14)
#define QCA807X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
#define QCA807X_INTR_ENABLE_LINK_FAIL BIT(11)
#define QCA807X_INTR_ENABLE_LINK_SUCCESS BIT(10)
#define QCA807X_FUNCTION_CONTROL 0x10
#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5)
#define QCA807X_FC_MDI_CROSSOVER_AUTO 3
#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX 1
#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI 0
#define QCA807X_PHY_SPECIFIC_STATUS 0x11
#define QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED BIT(11)
#define QCA807X_SS_SPEED_MASK GENMASK(15, 14)
#define QCA807X_SS_SPEED_1000 2
#define QCA807X_SS_SPEED_100 1
#define QCA807X_SS_SPEED_10 0
#define QCA807X_SS_DUPLEX BIT(13)
#define QCA807X_SS_MDIX BIT(6)
/* PSGMII PHY specific */
#define PSGMII_QSGMII_DRIVE_CONTROL_1 0xb
#define PSGMII_QSGMII_TX_DRIVER_MASK GENMASK(7, 4)
#define PSGMII_MODE_CTRL 0x6d
#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK GENMASK(3, 0)
#define PSGMII_MMD3_SERDES_CONTROL 0x805a
struct qca807x_gpio_priv {
struct phy_device *phy;
};
static int qca807x_get_downshift(struct phy_device *phydev, u8 *data)
{
int val, cnt, enable;
val = phy_read(phydev, MII_NWAYTEST);
if (val < 0)
return val;
enable = FIELD_GET(QCA807X_SMARTSPEED_EN, val);
cnt = FIELD_GET(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, val) + 2;
*data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
return 0;
}
static int qca807x_set_downshift(struct phy_device *phydev, u8 cnt)
{
int ret, val;
if (cnt > QCA807X_SMARTSPEED_RETRY_LIMIT_MAX ||
(cnt < QCA807X_SMARTSPEED_RETRY_LIMIT_MIN && cnt != DOWNSHIFT_DEV_DISABLE))
return -EINVAL;
if (!cnt) {
ret = phy_clear_bits(phydev, MII_NWAYTEST, QCA807X_SMARTSPEED_EN);
} else {
val = QCA807X_SMARTSPEED_EN;
val |= FIELD_PREP(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, cnt - 2);
phy_modify(phydev, MII_NWAYTEST,
QCA807X_SMARTSPEED_EN |
QCA807X_SMARTSPEED_RETRY_LIMIT_MASK,
val);
}
ret = genphy_soft_reset(phydev);
return ret;
}
static int qca807x_get_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return qca807x_get_downshift(phydev, data);
default:
return -EOPNOTSUPP;
}
}
static int qca807x_set_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return qca807x_set_downshift(phydev, *(const u8 *)data);
default:
return -EOPNOTSUPP;
}
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
static bool qca807x_distance_valid(int result)
{
switch (result) {
case QCA807X_CDT_RESULTS_OPEN:
case QCA807X_CDT_RESULTS_SAME_SHORT:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
return true;
}
return false;
}
static int qca807x_report_length(struct phy_device *phydev,
int pair, int result)
{
int length;
int ret;
ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_MDI0_LENGTH + pair);
if (ret < 0)
return ret;
switch (result) {
case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
length = (FIELD_GET(QCA807X_CDT_SAME_SHORT_LENGTH_MASK, ret) * 800) / 10;
break;
case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
length = (FIELD_GET(QCA807X_CDT_CROSS_SHORT_LENGTH_MASK, ret) * 800) / 10;
break;
}
ethnl_cable_test_fault_length(phydev, pair, length);
return 0;
}
static int qca807x_cable_test_report_trans(int result)
{
switch (result) {
case QCA807X_CDT_RESULTS_OK:
return ETHTOOL_A_CABLE_RESULT_CODE_OK;
case QCA807X_CDT_RESULTS_OPEN:
return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
case QCA807X_CDT_RESULTS_SAME_SHORT:
return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
default:
return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
}
}
static int qca807x_cable_test_report(struct phy_device *phydev)
{
int pair0, pair1, pair2, pair3;
int ret;
ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_STATUS);
if (ret < 0)
return ret;
pair0 = FIELD_GET(QCA807X_CDT_MDI0_STATUS_MASK, ret);
pair1 = FIELD_GET(QCA807X_CDT_MDI1_STATUS_MASK, ret);
pair2 = FIELD_GET(QCA807X_CDT_MDI2_STATUS_MASK, ret);
pair3 = FIELD_GET(QCA807X_CDT_MDI3_STATUS_MASK, ret);
ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
qca807x_cable_test_report_trans(pair0));
ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
qca807x_cable_test_report_trans(pair1));
ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
qca807x_cable_test_report_trans(pair2));
ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
qca807x_cable_test_report_trans(pair3));
if (qca807x_distance_valid(pair0))
qca807x_report_length(phydev, 0, qca807x_cable_test_report_trans(pair0));
if (qca807x_distance_valid(pair1))
qca807x_report_length(phydev, 1, qca807x_cable_test_report_trans(pair1));
if (qca807x_distance_valid(pair2))
qca807x_report_length(phydev, 2, qca807x_cable_test_report_trans(pair2));
if (qca807x_distance_valid(pair3))
qca807x_report_length(phydev, 3, qca807x_cable_test_report_trans(pair3));
return 0;
}
static int qca807x_cable_test_get_status(struct phy_device *phydev,
bool *finished)
{
int val;
*finished = false;
val = phy_read(phydev, QCA807X_CDT);
if (!((val & QCA807X_CDT_ENABLE) && (val & QCA807X_CDT_STATUS))) {
*finished = true;
return qca807x_cable_test_report(phydev);
}
return 0;
}
static int qca807x_cable_test_start(struct phy_device *phydev)
{
int val, ret;
val = phy_read(phydev, QCA807X_CDT);
/* Enable inter-pair short check as well */
val &= ~QCA807X_CDT_ENABLE_INTER_PAIR_SHORT;
val |= QCA807X_CDT_ENABLE;
ret = phy_write(phydev, QCA807X_CDT, val);
return ret;
}
#endif
#ifdef CONFIG_GPIOLIB
static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,5,0)
return GPIO_LINE_DIRECTION_OUT;
#else
return GPIOF_DIR_OUT;
#endif
}
static int qca807x_gpio_get_reg(unsigned int offset)
{
return QCA807X_MMD7_LED_100N_2 + (offset % 2) * 2;
}
static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
int val;
val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
}
static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
int val;
val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
val |= QCA807X_GPIO_FORCE_EN;
val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
phy_write_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset), val);
}
static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
{
qca807x_gpio_set(gc, offset, value);
return 0;
}
static int qca807x_gpio(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
struct qca807x_gpio_priv *priv;
struct gpio_chip *gc;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->phy = phydev;
gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
if (!gc)
return -ENOMEM;
gc->label = dev_name(dev);
gc->base = -1;
gc->ngpio = 2;
gc->parent = dev;
gc->owner = THIS_MODULE;
gc->can_sleep = true;
gc->get_direction = qca807x_gpio_get_direction;
gc->direction_output = qca807x_gpio_dir_out;
gc->get = qca807x_gpio_get;
gc->set = qca807x_gpio_set;
return devm_gpiochip_add_data(dev, gc, priv);
}
#endif
static int qca807x_read_copper_status(struct phy_device *phydev, bool combo_port)
{
int ss, err, page, old_link = phydev->link;
/* Only combo port has dual pages */
if (combo_port) {
/* Check whether copper page is set and set if needed */
page = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
if (!(page & QCA807X_BT_BX_REG_SEL)) {
page |= QCA807X_BT_BX_REG_SEL;
phy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);
}
}
/* Update the link, but return if there was an error */
err = genphy_update_link(phydev);
if (err)
return err;
/* why bother the PHY if nothing can have changed */
if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
return 0;
phydev->speed = SPEED_UNKNOWN;
phydev->duplex = DUPLEX_UNKNOWN;
phydev->pause = 0;
phydev->asym_pause = 0;
err = genphy_read_lpa(phydev);
if (err < 0)
return err;
/* Read the QCA807x PHY-Specific Status register copper page,
* which indicates the speed and duplex that the PHY is actually
* using, irrespective of whether we are in autoneg mode or not.
*/
ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
if (ss < 0)
return ss;
if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
int sfc;
sfc = phy_read(phydev, QCA807X_FUNCTION_CONTROL);
if (sfc < 0)
return sfc;
switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
case QCA807X_SS_SPEED_10:
phydev->speed = SPEED_10;
break;
case QCA807X_SS_SPEED_100:
phydev->speed = SPEED_100;
break;
case QCA807X_SS_SPEED_1000:
phydev->speed = SPEED_1000;
break;
}
if (ss & QCA807X_SS_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
if (ss & QCA807X_SS_MDIX)
phydev->mdix = ETH_TP_MDI_X;
else
phydev->mdix = ETH_TP_MDI;
switch (FIELD_GET(QCA807X_FC_MDI_CROSSOVER_MODE_MASK, sfc)) {
case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI:
phydev->mdix_ctrl = ETH_TP_MDI;
break;
case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX:
phydev->mdix_ctrl = ETH_TP_MDI_X;
break;
case QCA807X_FC_MDI_CROSSOVER_AUTO:
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
break;
}
}
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
phy_resolve_aneg_pause(phydev);
return 0;
}
static int qca807x_read_fiber_status(struct phy_device *phydev, bool combo_port)
{
int ss, err, page, lpa, old_link = phydev->link;
/* Check whether fiber page is set and set if needed */
page = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
if (page & QCA807X_BT_BX_REG_SEL) {
page &= ~QCA807X_BT_BX_REG_SEL;
phy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);
}
/* Update the link, but return if there was an error */
err = genphy_update_link(phydev);
if (err)
return err;
/* why bother the PHY if nothing can have changed */
if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
return 0;
phydev->speed = SPEED_UNKNOWN;
phydev->duplex = DUPLEX_UNKNOWN;
phydev->pause = 0;
phydev->asym_pause = 0;
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
lpa = phy_read(phydev, MII_LPA);
if (lpa < 0)
return lpa;
linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->lp_advertising, lpa & LPA_LPACK);
linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
phydev->lp_advertising, lpa & LPA_1000XFULL);
linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
phydev->lp_advertising, lpa & LPA_1000XPAUSE);
linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
phydev->lp_advertising,
lpa & LPA_1000XPAUSE_ASYM);
phy_resolve_aneg_linkmode(phydev);
}
/* Read the QCA807x PHY-Specific Status register fiber page,
* which indicates the speed and duplex that the PHY is actually
* using, irrespective of whether we are in autoneg mode or not.
*/
ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
if (ss < 0)
return ss;
if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
case QCA807X_SS_SPEED_100:
phydev->speed = SPEED_100;
break;
case QCA807X_SS_SPEED_1000:
phydev->speed = SPEED_1000;
break;
}
if (ss & QCA807X_SS_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
}
return 0;
}
static int qca807x_read_status(struct phy_device *phydev)
{
int val;
/* Check for Combo port */
if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
/* Check for fiber mode first */
if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
/* Check for actual detected media */
val = phy_read(phydev, QCA807X_MEDIA_SELECT_STATUS);
if (val & QCA807X_MEDIA_DETECTED_COPPER) {
qca807x_read_copper_status(phydev, true);
} else if ((val & QCA807X_MEDIA_DETECTED_1000_BASE_X) ||
(val & QCA807X_MEDIA_DETECTED_100_BASE_FX)) {
qca807x_read_fiber_status(phydev, true);
}
} else {
qca807x_read_copper_status(phydev, true);
}
} else {
qca807x_read_copper_status(phydev, false);
}
return 0;
}
static int qca807x_config_intr(struct phy_device *phydev)
{
int ret, val;
val = phy_read(phydev, QCA807X_INTR_ENABLE);
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
/* Check for combo port as it has fewer interrupts */
if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
val |= QCA807X_INTR_ENABLE_LINK_FAIL;
val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
} else {
val |= QCA807X_INTR_ENABLE_AUTONEG_ERR;
val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
val |= QCA807X_INTR_ENABLE_DUPLEX_CHANGED;
val |= QCA807X_INTR_ENABLE_LINK_FAIL;
val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
}
ret = phy_write(phydev, QCA807X_INTR_ENABLE, val);
} else {
ret = phy_write(phydev, QCA807X_INTR_ENABLE, 0);
}
return ret;
}
static int qca807x_ack_intr(struct phy_device *phydev)
{
int ret;
ret = phy_read(phydev, QCA807X_INTR_STATUS);
return (ret < 0) ? ret : 0;
}
static int qca807x_led_config(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
bool led_config = false;
int val;
val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1);
if (val < 0)
return val;
if (of_property_read_bool(node, "qcom,single-led-1000")) {
val |= QCA807X_LED_TXACT_BLK_EN_2;
val |= QCA807X_LED_RXACT_BLK_EN_2;
val |= QCA807X_LED_GT_ON_EN_2;
led_config = true;
}
if (of_property_read_bool(node, "qcom,single-led-100")) {
val |= QCA807X_LED_HT_ON_EN_2;
led_config = true;
}
if (of_property_read_bool(node, "qcom,single-led-10")) {
val |= QCA807X_LED_BT_ON_EN_2;
led_config = true;
}
if (led_config)
return phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1, val);
else
return 0;
}
static const struct sfp_upstream_ops qca807x_sfp_ops = {
.attach = phy_sfp_attach,
.detach = phy_sfp_detach,
};
static int qca807x_config(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
int control_dac, ret = 0;
u32 of_control_dac;
/* Check for Combo port */
if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
int fiber_mode_autodect;
int psgmii_serdes;
int chip_config;
if (of_property_read_bool(node, "qcom,fiber-enable")) {
/* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
fiber_mode_autodect = phy_read_mmd(phydev, MDIO_MMD_AN,
QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION);
fiber_mode_autodect |= QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN;
phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
fiber_mode_autodect);
/* Enable 4 copper + combo port mode */
chip_config = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
chip_config &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;
chip_config |= FIELD_PREP(QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
phy_write(phydev, QCA807X_CHIP_CONFIGURATION, chip_config);
linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
}
/* Prevent PSGMII going into hibernation via PSGMII self test */
psgmii_serdes = phy_read_mmd(phydev, MDIO_MMD_PCS, PSGMII_MMD3_SERDES_CONTROL);
psgmii_serdes &= ~BIT(1);
ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
PSGMII_MMD3_SERDES_CONTROL,
psgmii_serdes);
}
if (!of_property_read_u32(node, "qcom,control-dac", &of_control_dac)) {
control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
control_dac &= ~QCA807X_CONTROL_DAC_MASK;
control_dac |= FIELD_PREP(QCA807X_CONTROL_DAC_MASK, of_control_dac);
ret = phy_write_mmd(phydev, MDIO_MMD_AN,
QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
control_dac);
}
/* Optionally configure LED-s */
if (IS_ENABLED(CONFIG_GPIOLIB)) {
/* Check whether PHY-s pins are used as GPIO-s */
if (!of_property_read_bool(node, "gpio-controller"))
ret = qca807x_led_config(phydev);
} else {
ret = qca807x_led_config(phydev);
}
return ret;
}
static int qca807x_probe(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
int ret = 0;
if (IS_ENABLED(CONFIG_GPIOLIB)) {
/* Do not register a GPIO controller unless flagged for it */
if (of_property_read_bool(node, "gpio-controller"))
ret = qca807x_gpio(phydev);
}
/* Attach SFP bus on combo port*/
if (of_property_read_bool(node, "qcom,fiber-enable")) {
if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION))
ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
}
return ret;
}
static int qca807x_psgmii_config(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
int psgmii_az, tx_amp, ret = 0;
u32 tx_driver_strength;
/* Workaround to enable AZ transmitting ability */
if (of_property_read_bool(node, "qcom,psgmii-az")) {
psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);
psgmii_az &= ~PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;
psgmii_az |= FIELD_PREP(PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK, 0xc);
ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL, psgmii_az);
psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);
}
/* PSGMII/QSGMII TX amp set to DT defined value instead of default 600mV */
if (!of_property_read_u32(node, "qcom,tx-driver-strength", &tx_driver_strength)) {
tx_amp = phy_read(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1);
tx_amp &= ~PSGMII_QSGMII_TX_DRIVER_MASK;
tx_amp |= FIELD_PREP(PSGMII_QSGMII_TX_DRIVER_MASK, tx_driver_strength);
ret = phy_write(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1, tx_amp);
}
return ret;
}
static struct phy_driver qca807x_drivers[] = {
{
PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
.name = "Qualcomm QCA8072",
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
.flags = PHY_POLL_CABLE_TEST,
#endif
/* PHY_GBIT_FEATURES */
.probe = qca807x_probe,
.config_init = qca807x_config,
.read_status = qca807x_read_status,
.config_intr = qca807x_config_intr,
.ack_interrupt = qca807x_ack_intr,
.soft_reset = genphy_soft_reset,
.get_tunable = qca807x_get_tunable,
.set_tunable = qca807x_set_tunable,
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
.cable_test_start = qca807x_cable_test_start,
.cable_test_get_status = qca807x_cable_test_get_status,
#endif
},
{
PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
.name = "Qualcomm QCA8075",
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
.flags = PHY_POLL_CABLE_TEST,
#endif
/* PHY_GBIT_FEATURES */
.probe = qca807x_probe,
.config_init = qca807x_config,
.read_status = qca807x_read_status,
.config_intr = qca807x_config_intr,
.ack_interrupt = qca807x_ack_intr,
.soft_reset = genphy_soft_reset,
.get_tunable = qca807x_get_tunable,
.set_tunable = qca807x_set_tunable,
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
.cable_test_start = qca807x_cable_test_start,
.cable_test_get_status = qca807x_cable_test_get_status,
#endif
},
{
PHY_ID_MATCH_EXACT(PHY_ID_QCA807X_PSGMII),
.name = "Qualcomm QCA807x PSGMII",
.probe = qca807x_psgmii_config,
},
};
module_phy_driver(qca807x_drivers);
static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
{ PHY_ID_MATCH_MODEL(PHY_ID_QCA807X_PSGMII) },
{ }
};
MODULE_AUTHOR("Robert Marko");
MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
MODULE_LICENSE("GPL");

1
target/linux/ipq40xx/generic/target.mk Normal file
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@@ -0,0 +1 @@
BOARDNAME:=Generic

17
target/linux/ipq40xx/image/Makefile Normal file
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@@ -0,0 +1,17 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Device/Default
PROFILES := Default
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_LOADADDR := 0x80208000
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata
IMAGE/sysupgrade.bin/squashfs :=
endef
include $(SUBTARGET).mk
$(eval $(call BuildImage))

831
target/linux/ipq40xx/image/generic.mk Normal file
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@@ -0,0 +1,831 @@
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
DEVICE_VARS += RAS_BOARD RAS_ROOTFS_SIZE RAS_VERSION
DEVICE_VARS += WRGG_DEVNAME WRGG_SIGNATURE
define Device/FitImage
KERNEL_SUFFIX := -fit-uImage.itb
KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/FitImageLzma
KERNEL_SUFFIX := -fit-uImage.itb
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/FitzImage
KERNEL_SUFFIX := -fit-zImage.itb
KERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := zImage
endef
define Device/UbiFit
KERNEL_IN_UBI := 1
IMAGES := nand-factory.ubi nand-sysupgrade.bin
IMAGE/nand-factory.ubi := append-ubi
IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
endef
define Device/DniImage
$(call Device/FitzImage)
NETGEAR_BOARD_ID :=
NETGEAR_HW_ID :=
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | append-rootfs | pad-rootfs | netgear-dni
IMAGE/sysupgrade.bin := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | \
append-rootfs | pad-rootfs | check-size | append-metadata
endef
define Build/append-rootfshdr
mkimage -A $(LINUX_KARCH) \
-O linux -T filesystem \
-C lzma -a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
-n root.squashfs -d $(IMAGE_ROOTFS) $@.new
dd if=$@.new bs=64 count=1 >> $(IMAGE_KERNEL)
endef
define Build/mkmylofw_32m
$(eval device_id=$(word 1,$(1)))
$(eval revision=$(word 2,$(1)))
let \
size="$$(stat -c%s $@)" \
pad="$(subst k,* 1024,$(BLOCKSIZE))" \
pad="(pad - (size % pad)) % pad" \
newsize='size + pad'; \
$(STAGING_DIR_HOST)/bin/mkmylofw \
-B WPE72 -i 0x11f6:$(device_id):0x11f6:$(device_id) -r $(revision) \
-s 0x2000000 -p0x180000:$$newsize:al:0x80208000:"OpenWrt":$@ \
$@.new
@mv $@.new $@
endef
define Build/wac5xx-netgear-tar
mkdir $@.tmp
mv $@ $@.tmp/wac5xx-ubifs-root.img
md5sum $@.tmp/wac5xx-ubifs-root.img > $@.tmp/wac5xx-ubifs-root.md5sum
echo "WAC505 WAC510" > $@.tmp/metadata.txt
echo "WAC505_V9.9.9.9" > $@.tmp/version
tar -C $@.tmp/ -cf $@ .
rm -rf $@.tmp
endef
define Build/qsdk-ipq-factory-nand-askey
$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh $@.its\
askey_kernel $(IMAGE_KERNEL) \
askey_fs $(IMAGE_ROOTFS) \
ubifs $@
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
@mv $@.new $@
endef
define Build/SenaoFW
-$(STAGING_DIR_HOST)/bin/mksenaofw \
-n $(BOARD_NAME) -r $(VENDOR_ID) -p $(1) \
-c $(DATECODE) -w $(2) -x $(CW_VER) -t 0 \
-e $@ \
-o $@.new
@cp $@.new $@
endef
define Build/wrgg-image
mkwrggimg -i $@ \
-o $@.new \
-d "$(WRGG_DEVNAME)" \
-s "$(WRGG_SIGNATURE)" \
-v "" -m "" -B ""
mv $@.new $@
endef
define Device/8dev_habanero-dvk
$(call Device/FitImageLzma)
DEVICE_VENDOR := 8devices
DEVICE_MODEL := Habanero DVK
IMAGE_SIZE := 30976k
SOC := qcom-ipq4019
DEVICE_PACKAGES := ipq-wifi-8dev_habanero-dvk
IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | check-size | append-metadata
endef
TARGET_DEVICES += 8dev_habanero-dvk
define Device/8dev_jalapeno-common
$(call Device/FitImage)
$(call Device/UbiFit)
BLOCKSIZE := 128k
PAGESIZE := 2048
SOC := qcom-ipq4018
endef
define Device/8dev_jalapeno
$(call Device/8dev_jalapeno-common)
DEVICE_VENDOR := 8devices
DEVICE_MODEL := Jalapeno
endef
TARGET_DEVICES += 8dev_jalapeno
define Device/alfa-network_ap120c-ac
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := ALFA Network
DEVICE_MODEL := AP120C-AC
SOC := qcom-ipq4018
DEVICE_PACKAGES := kmod-usb-acm kmod-tpm-i2c-atmel
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
IMAGES := nand-factory.bin nand-sysupgrade.bin
IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand
endef
TARGET_DEVICES += alfa-network_ap120c-ac
define Device/aruba_glenmorangie
$(call Device/FitImageLzma)
DEVICE_VENDOR := Aruba
SOC := qcom-ipq4029
DEVICE_PACKAGES := ipq-wifi-aruba_ap-303
endef
define Device/aruba_ap-303
$(call Device/aruba_glenmorangie)
DEVICE_MODEL := AP-303
endef
TARGET_DEVICES += aruba_ap-303
define Device/aruba_ap-303h
$(call Device/aruba_glenmorangie)
DEVICE_MODEL := AP-303H
endef
TARGET_DEVICES += aruba_ap-303h
define Device/aruba_ap-365
$(call Device/aruba_glenmorangie)
DEVICE_MODEL := AP-365
DEVICE_PACKAGES += kmod-hwmon-ad7418
endef
TARGET_DEVICES += aruba_ap-365
define Device/asus_map-ac2200
$(call Device/FitImageLzma)
DEVICE_VENDOR := ASUS
DEVICE_MODEL := Lyra (MAP-AC2200)
SOC := qcom-ipq4019
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct kmod-ath3k
endef
TARGET_DEVICES += asus_map-ac2200
define Device/asus_rt-ac58u
$(call Device/FitImageLzma)
DEVICE_VENDOR := ASUS
DEVICE_MODEL := RT-AC58U
SOC := qcom-ipq4018
BLOCKSIZE := 128k
PAGESIZE := 2048
DTB_SIZE := 65536
IMAGE_SIZE := 20439364
FILESYSTEMS := squashfs
# Someone - in their infinite wisdom - decided to put the firmware
# version in front of the image name \03\00\00\04 => Version 3.0.0.4
# Since u-boot works with strings we either need another fixup step
# to add a version... or we are very careful not to add '\0' into that
# string and call it a day.... Yeah, we do the latter!
UIMAGE_NAME:=$(shell echo -e '\03\01\01\01RT-AC58U')
DEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers \
kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += asus_rt-ac58u
define Device/avm_fritzbox-4040
$(call Device/FitImageLzma)
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!Box 4040
SOC := qcom-ipq4018
BOARD_NAME := fritz4040
IMAGE_SIZE := 29056k
UBOOT_PATH := $(STAGING_DIR_IMAGE)/uboot-fritz4040.bin
UBOOT_PARTITION_SIZE := 524288
IMAGES += eva.bin
IMAGE/eva.bin := append-uboot | pad-to $$$$(UBOOT_PARTITION_SIZE) | append-kernel | append-rootfs | pad-rootfs
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata
DEVICE_PACKAGES := fritz-tffs fritz-caldata
endef
TARGET_DEVICES += avm_fritzbox-4040
define Device/avm_fritzbox-7530
$(call Device/FitImageLzma)
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!Box 7530
SOC := qcom-ipq4019
DEVICE_PACKAGES := fritz-caldata fritz-tffs-nand
endef
TARGET_DEVICES += avm_fritzbox-7530
define Device/avm_fritzrepeater-1200
$(call Device/FitImageLzma)
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!Repeater 1200
SOC := qcom-ipq4019
DEVICE_PACKAGES := fritz-caldata fritz-tffs-nand ipq-wifi-avm_fritzrepeater-1200
endef
TARGET_DEVICES += avm_fritzrepeater-1200
define Device/avm_fritzrepeater-3000
$(call Device/FitImageLzma)
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!Repeater 3000
SOC := qcom-ipq4019
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct fritz-caldata fritz-tffs-nand
endef
TARGET_DEVICES += avm_fritzrepeater-3000
define Device/buffalo_wtr-m2133hp
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WTR-M2133HP
SOC := qcom-ipq4019
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ipq-wifi-buffalo_wtr-m2133hp
BLOCKSIZE := 128k
PAGESIZE := 2048
endef
TARGET_DEVICES += buffalo_wtr-m2133hp
define Device/cellc_rtl30vw
KERNEL_SUFFIX := -fit-uImage.itb
KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb | uImage lzma | pad-to 2048
KERNEL_NAME := Image
KERNEL_IN_UBI :=
IMAGES := nand-factory.bin nand-sysupgrade.bin
IMAGE/nand-factory.bin := append-rootfshdr | append-ubi | qsdk-ipq-factory-nand-askey
IMAGE/nand-sysupgrade.bin := append-rootfshdr | sysupgrade-tar | append-metadata
DEVICE_VENDOR := Cell C
DEVICE_MODEL := RTL30VW
SOC := qcom-ipq4019
DEVICE_DTS_CONFIG := config@5
KERNEL_INSTALL := 1
KERNEL_SIZE := 4096k
IMAGE_SIZE := 57344k
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi ipq-wifi-cellc_rtl30vw
endef
TARGET_DEVICES += cellc_rtl30vw
define Device/cilab_meshpoint-one
$(call Device/8dev_jalapeno-common)
DEVICE_VENDOR := Crisis Innovation Lab
DEVICE_MODEL := MeshPoint.One
DEVICE_PACKAGES := kmod-i2c-gpio kmod-iio-bmp280-i2c kmod-hwmon-ina2xx kmod-rtc-pcf2127
endef
TARGET_DEVICES += cilab_meshpoint-one
define Device/compex_wpj419
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Compex
DEVICE_MODEL := WPJ419
SOC := qcom-ipq4019
DEVICE_DTS_CONFIG := config@12
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
FILESYSTEMS := squashfs
endef
TARGET_DEVICES += compex_wpj419
define Device/compex_wpj428
$(call Device/FitImage)
DEVICE_VENDOR := Compex
DEVICE_MODEL := WPJ428
SOC := qcom-ipq4028
DEVICE_DTS_CONFIG := config@4
BLOCKSIZE := 64k
IMAGE_SIZE := 31232k
KERNEL_SIZE := 4096k
IMAGES += cpximg-6a04.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
IMAGE/cpximg-6a04.bin := append-kernel | append-rootfs | pad-rootfs | mkmylofw_32m 0x8A2 3
DEVICE_PACKAGES := kmod-gpio-beeper
endef
TARGET_DEVICES += compex_wpj428
define Device/devolo_magic-2-wifi-next
$(call Device/FitImage)
DEVICE_VENDOR := devolo
DEVICE_MODEL := Magic 2 WiFi next
SOC := qcom-ipq4018
KERNEL_SIZE := 4096k
# If the bootloader sees 0xDEADC0DE and this trailer at the 64k boundary of a TFTP image
# it will bootm it, just like we want for the initramfs.
KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to 64k |\
append-string -e '\xDE\xAD\xC0\xDE{"fl_initramfs":""}\x00'
IMAGE_SIZE := 26624k
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
DEVICE_PACKAGES := ipq-wifi-devolo_magic-2-wifi-next
endef
TARGET_DEVICES += devolo_magic-2-wifi-next
define Device/dlink_dap-2610
$(call Device/FitImageLzma)
DEVICE_VENDOR := D-Link
DEVICE_MODEL := DAP-2610
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@ap.dk01.1-c1
BLOCKSIZE := 64k
WRGG_DEVNAME := /dev/mtdblock/8
WRGG_SIGNATURE := wapac30_dkbs_dap2610
IMAGE_SIZE := 14080k
IMAGES += factory.bin
# Bootloader expects a special 160 byte header which is added by
# wrgg-image.
# Factory image size must be larger than 6MB, and size in wrgg header must
# match actual factory image size to be flashable from D-Link http server.
# Bootloader verifies checksum of wrgg image before booting, thus jffs2
# cannot be part of the wrgg image. This is solved in the factory image by
# having the rootfs at the end of the image (without pad-rootfs). And in
# the sysupgrade image only the kernel is included in the wrgg checksum,
# but this is not flashable from the D-link http server.
# append-rootfs must start on an erase block boundary.
IMAGE/factory.bin := append-kernel | pad-offset 6144k 160 | append-rootfs | wrgg-image | check-size
IMAGE/sysupgrade.bin := append-kernel | wrgg-image | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size | append-metadata
DEVICE_PACKAGES := ipq-wifi-dlink_dap2610
endef
TARGET_DEVICES += dlink_dap-2610
define Device/edgecore_ecw5211
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edgecore
DEVICE_MODEL := ECW5211
SOC := qcom-ipq4018
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ap.dk01.1-c2
DEVICE_PACKAGES := kmod-tpm-i2c-atmel kmod-usb-acm
endef
TARGET_DEVICES += edgecore_ecw5211
define Device/edgecore_oap100
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edgecore
DEVICE_MODEL := OAP100
SOC := qcom-ipq4019
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGES := nand-sysupgrade.bin
DEVICE_DTS_CONFIG := config@ap.dk07.1-c1
DEVICE_PACKAGES := ipq-wifi-edgecore_oap100 kmod-usb-acm kmod-usb-net kmod-usb-net-cdc-qmi uqmi
endef
TARGET_DEVICES += edgecore_oap100
define Device/engenius_eap1300
$(call Device/FitImage)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := EAP1300
DEVICE_DTS_CONFIG := config@4
BOARD_NAME := eap1300
SOC := qcom-ipq4018
KERNEL_SIZE := 5120k
IMAGE_SIZE := 25344k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += engenius_eap1300
define Device/engenius_eap2200
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := EAP2200
SOC := qcom-ipq4019
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-engenius_eap2200 -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers
endef
TARGET_DEVICES += engenius_eap2200
define Device/engenius_emd1
$(call Device/FitImage)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := EMD1
DEVICE_DTS_CONFIG := config@4
SOC := qcom-ipq4018
IMAGE_SIZE := 30720k
IMAGES += factory.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
IMAGE/factory.bin := qsdk-ipq-factory-nor | check-size
DEVICE_PACKAGES := ipq-wifi-engenius_emd1
endef
TARGET_DEVICES += engenius_emd1
define Device/engenius_emr3500
$(call Device/FitImage)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := EMR3500
DEVICE_DTS_CONFIG := config@4
SOC := qcom-ipq4018
KERNEL_SIZE := 4096k
IMAGE_SIZE := 30720k
IMAGES += factory.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
IMAGE/factory.bin := qsdk-ipq-factory-nor | check-size
DEVICE_PACKAGES := ipq-wifi-engenius_emr3500
endef
TARGET_DEVICES += engenius_emr3500
define Device/engenius_ens620ext
$(call Device/FitImage)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := ENS620EXT
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@4
BLOCKSIZE := 64k
PAGESIZE := 256
BOARD_NAME := ENS620EXT
VENDOR_ID := 0x0101
PRODUCT_ID := 0x79
PRODUCT_ID_NEW := 0xA4
DATECODE := 190507
FW_VER := 3.1.2
FW_VER_NEW := 3.5.6
CW_VER := 1.8.99
IMAGE_SIZE := 21312k
KERNEL_SIZE := 5120k
FILESYSTEMS := squashfs
IMAGES += factory_30.bin factory_35.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata
IMAGE/factory_30.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | check-size | SenaoFW $$$$(PRODUCT_ID) $$$$(FW_VER)
IMAGE/factory_35.bin := qsdk-ipq-factory-nor | check-size | SenaoFW $$$$(PRODUCT_ID_NEW) $$$$(FW_VER_NEW)
endef
TARGET_DEVICES += engenius_ens620ext
define Device/ezviz_cs-w3-wd1200g-eup
$(call Device/FitImage)
DEVICE_VENDOR := EZVIZ
DEVICE_MODEL := CS-W3-WD1200G
DEVICE_VARIANT := EUP
DEVICE_DTS_CONFIG := config@4
IMAGE_SIZE := 14848k
SOC := qcom-ipq4018
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \
append-metadata
DEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers \
ipq-wifi-ezviz_cs-w3-wd1200g-eup
endef
TARGET_DEVICES += ezviz_cs-w3-wd1200g-eup
define Device/glinet_gl-ap1300
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-AP1300
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@ap.dk01.1-c2
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 131072k
KERNEL_INSTALL := 1
DEVICE_PACKAGES := ipq-wifi-glinet_gl-ap1300
endef
TARGET_DEVICES += glinet_gl-ap1300
define Device/glinet_gl-b1300
$(call Device/FitzImage)
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-B1300
BOARD_NAME := gl-b1300
SOC := qcom-ipq4029
KERNEL_SIZE := 4096k
IMAGE_SIZE := 26624k
IMAGE/sysupgrade.bin := append-kernel |append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += glinet_gl-b1300
define Device/glinet_gl-s1300
$(call Device/FitzImage)
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-S1300
SOC := qcom-ipq4029
KERNEL_SIZE := 4096k
IMAGE_SIZE := 26624k
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
DEVICE_PACKAGES := ipq-wifi-glinet_gl-s1300 kmod-fs-ext4 kmod-mmc kmod-spi-dev
endef
TARGET_DEVICES += glinet_gl-s1300
define Device/linksys_ea6350v3
# The Linksys EA6350v3 has a uboot bootloader that does not
# support either booting lzma kernel images nor booting UBI
# partitions. This uboot, however, supports raw kernel images and
# gzipped images.
#
# As for the time of writing this, the device will boot the kernel
# from a fixed address with a fixed length of 3MiB. Also, the
# device has a hard-coded kernel command line that requieres the
# rootfs and alt_rootfs to be in mtd11 and mtd13 respectively.
# Oh... and the kernel partition overlaps with the rootfs
# partition (the same for alt_kernel and alt_rootfs).
#
# If you are planing re-partitioning the device, you may want to
# keep those details in mind:
# 1. The kernel adresses you should honor are 0x00000000 and
# 0x02800000 respectively.
# 2. The kernel size (plus the dtb) cannot exceed 3.00MiB in size.
# 3. You can use 'zImage', but not a raw 'Image' packed with lzma.
# 4. The kernel command line from uboot is harcoded to boot with
# rootfs either in mtd11 or mtd13.
$(call Device/FitzImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA6350
DEVICE_VARIANT := v3
SOC := qcom-ipq4018
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 3072k
IMAGE_SIZE := 37888k
UBINIZE_OPTS := -E 5
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=EA6350v3
endef
TARGET_DEVICES += linksys_ea6350v3
define Device/linksys_ea8300
$(call Device/FitzImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA8300
SOC := qcom-ipq4019
KERNEL_SIZE := 3072k
IMAGE_SIZE := 87040k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5 # EOD marks to "hide" factory sig at EOF
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=EA8300
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-linksys_ea8300 kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += linksys_ea8300
define Device/linksys_mr8300
$(call Device/FitzImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := MR8300
SOC := qcom-ipq4019
KERNEL_SIZE := 3072k
IMAGE_SIZE := 87040k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5 # EOD marks to "hide" factory sig at EOF
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MR8300
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-linksys_mr8300-v0 kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += linksys_mr8300
define Device/luma_wrtq-329acn
$(call Device/FitImage)
DEVICE_VENDOR := Luma Home
DEVICE_MODEL := WRTQ-329ACN
SOC := qcom-ipq4018
DEVICE_PACKAGES := ipq-wifi-luma_wrtq-329acn kmod-ath3k kmod-eeprom-at24 kmod-i2c-gpio
IMAGE_SIZE := 76632k
BLOCKSIZE := 128k
PAGESIZE := 2048
endef
TARGET_DEVICES += luma_wrtq-329acn
define Device/meraki_mr33
$(call Device/FitImage)
DEVICE_VENDOR := Cisco Meraki
DEVICE_MODEL := MR33
SOC := qcom-ipq4029
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := -swconfig ath10k-firmware-qca9887-ct
endef
TARGET_DEVICES += meraki_mr33
define Device/mobipromo_cm520-79f
$(call Device/FitzImage)
$(call Device/UbiFit)
DEVICE_VENDOR := MobiPromo
DEVICE_MODEL := CM520-79F
SOC := qcom-ipq4019
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ipq-wifi-mobipromo_cm520-79f kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += mobipromo_cm520-79f
define Device/netgear_ex61x0v2
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_DTS_CONFIG := config@4
NETGEAR_BOARD_ID := EX6150v2series
NETGEAR_HW_ID := 29765285+16+0+128+2x2
IMAGE_SIZE := 14400k
SOC := qcom-ipq4018
endef
define Device/netgear_ex6100v2
$(call Device/netgear_ex61x0v2)
DEVICE_MODEL := EX6100
DEVICE_VARIANT := v2
endef
TARGET_DEVICES += netgear_ex6100v2
define Device/netgear_ex6150v2
$(call Device/netgear_ex61x0v2)
DEVICE_MODEL := EX6150
DEVICE_VARIANT := v2
endef
TARGET_DEVICES += netgear_ex6150v2
define Device/netgear_wac510
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Netgear
DEVICE_MODEL := WAC510
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGES += nand-factory.tar
IMAGE/nand-factory.tar := append-ubi | wac5xx-netgear-tar
DEVICE_PACKAGES := uboot-envtools
endef
TARGET_DEVICES += netgear_wac510
define Device/openmesh_a42
$(call Device/FitImageLzma)
DEVICE_VENDOR := OpenMesh
DEVICE_MODEL := A42
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@om.a42
BLOCKSIZE := 64k
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
IMAGE_SIZE := 15616k
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
endef
TARGET_DEVICES += openmesh_a42
define Device/openmesh_a62
$(call Device/FitImageLzma)
DEVICE_VENDOR := OpenMesh
DEVICE_MODEL := A62
SOC := qcom-ipq4019
DEVICE_DTS_CONFIG := config@om.a62
BLOCKSIZE := 64k
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
IMAGE_SIZE := 15552k
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A62
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct
endef
TARGET_DEVICES += openmesh_a62
define Device/plasmacloud_pa1200
$(call Device/FitImageLzma)
DEVICE_VENDOR := Plasma Cloud
DEVICE_MODEL := PA1200
SOC := qcom-ipq4018
DEVICE_DTS_CONFIG := config@pc.pa1200
BLOCKSIZE := 64k
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
IMAGE_SIZE := 15616k
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA1200
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ipq-wifi-plasmacloud_pa1200
endef
TARGET_DEVICES += plasmacloud_pa1200
define Device/plasmacloud_pa2200
$(call Device/FitImageLzma)
DEVICE_VENDOR := Plasma Cloud
DEVICE_MODEL := PA2200
SOC := qcom-ipq4019
DEVICE_DTS_CONFIG := config@pc.pa2200
BLOCKSIZE := 64k
KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
IMAGE_SIZE := 15552k
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA2200
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-plasmacloud_pa2200
endef
TARGET_DEVICES += plasmacloud_pa2200
define Device/qcom_ap-dk01.1-c1
DEVICE_VENDOR := Qualcomm Atheros
DEVICE_MODEL := AP-DK01.1
DEVICE_VARIANT := C1
BOARD_NAME := ap-dk01.1-c1
SOC := qcom-ipq4019
DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
KERNEL_INSTALL := 1
KERNEL_SIZE := 4096k
IMAGE_SIZE := 26624k
$(call Device/FitImage)
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += qcom_ap-dk01.1-c1
define Device/qcom_ap-dk04.1-c1
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm Atheros
DEVICE_MODEL := AP-DK04.1
DEVICE_VARIANT := C1
SOC := qcom-ipq4019
DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
KERNEL_INSTALL := 1
KERNEL_SIZE := 4048k
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap-dk04.1-c1
endef
TARGET_DEVICES += qcom_ap-dk04.1-c1
define Device/qxwlan_e2600ac-c1
$(call Device/FitImage)
DEVICE_VENDOR := Qxwlan
DEVICE_MODEL := E2600AC
DEVICE_VARIANT := C1
BOARD_NAME := e2600ac-c1
SOC := qcom-ipq4019
KERNEL_SIZE := 4096k
IMAGE_SIZE := 31232k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
DEVICE_PACKAGES := ipq-wifi-qxwlan_e2600ac
endef
TARGET_DEVICES += qxwlan_e2600ac-c1
define Device/qxwlan_e2600ac-c2
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qxwlan
DEVICE_MODEL := E2600AC
DEVICE_VARIANT := C2
SOC := qcom-ipq4019
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ipq-wifi-qxwlan_e2600ac
endef
TARGET_DEVICES += qxwlan_e2600ac-c2
define Device/unielec_u4019-32m
$(call Device/FitImage)
DEVICE_VENDOR := Unielec
DEVICE_MODEL := U4019
DEVICE_VARIANT := 32M
BOARD_NAME := u4019-32m
SOC := qcom-ipq4019
KERNEL_SIZE := 4096k
IMAGE_SIZE := 31232k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += unielec_u4019-32m
define Device/zyxel_nbg6617
$(call Device/FitImageLzma)
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := NBG6617
SOC := qcom-ipq4018
KERNEL_SIZE := 4096k
ROOTFS_SIZE := 24960k
RAS_BOARD := NBG6617
RAS_ROOTFS_SIZE := 19840k
RAS_VERSION := "$(VERSION_DIST) $(REVISION)"
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
IMAGES += factory.bin
# The ZyXEL firmware allows flashing thru the web-gui only when the rootfs is
# at least as large as the one of the initial firmware image (not the current
# one on the device). This only applies to the Web-UI, the bootlaoder ignores
# this minimum-size. However, the larger image can be flashed both ways.
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k | check-size $$$$(ROOTFS_SIZE) | zyxel-ras-image separate-kernel
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | check-size $$$$(ROOTFS_SIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += zyxel_nbg6617
define Device/zyxel_wre6606
$(call Device/FitImage)
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := WRE6606
DEVICE_DTS_CONFIG := config@4
SOC := qcom-ipq4018
IMAGE_SIZE := 13184k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata
DEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers
endef
TARGET_DEVICES += zyxel_wre6606

28
target/linux/ipq40xx/image/mikrotik.mk Normal file
View File

@@ -0,0 +1,28 @@
define Device/mikrotik_nor
DEVICE_VENDOR := MikroTik
BLOCKSIZE := 64k
IMAGE_SIZE := 16128k
KERNEL_NAME := vmlinux
KERNEL := kernel-bin | append-dtb-elf
IMAGES = sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 | \
pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
check-size | append-metadata
endef
define Device/mikrotik_hap-ac2
$(call Device/mikrotik_nor)
DEVICE_MODEL := hAP ac2
SOC := qcom-ipq4018
DEVICE_PACKAGES := ipq-wifi-mikrotik_hap-ac2 -kmod-ath10k-ct \
kmod-ath10k-ct-smallbuffers
endef
TARGET_DEVICES += mikrotik_hap-ac2
define Device/mikrotik_sxtsq-5-ac
$(call Device/mikrotik_nor)
DEVICE_MODEL := SXTsq 5 ac (RBSXTsqG-5acD)
SOC := qcom-ipq4018
DEVICE_PACKAGES := ipq-wifi-mikrotik_sxtsq-5-ac rssileds
endef
TARGET_DEVICES += mikrotik_sxtsq-5-ac

4
target/linux/ipq40xx/mikrotik/config-default Normal file
View File

@@ -0,0 +1,4 @@
CONFIG_MIKROTIK=y
CONFIG_MIKROTIK_RB_SYSFS=y
CONFIG_MTD_ROUTERBOOT_PARTS=y
CONFIG_MTD_SPLIT_MINOR_FW=y

4
target/linux/ipq40xx/mikrotik/target.mk Normal file
View File

@@ -0,0 +1,4 @@
BOARDNAME:=MikroTik
FEATURES += minor
KERNEL_IMAGES:=vmlinux
IMAGES_DIR:=compressed

99
target/linux/ipq40xx/patches-5.10/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch Normal file
View File

@@ -0,0 +1,99 @@
From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Sep 2020 18:38:31 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -605,5 +605,79 @@
reg = <4>;
};
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3: usb3@8af8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
+ <&gcc GCC_USB3_SLEEP_CLK>,
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2: usb2@60f8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
+ <&gcc GCC_USB2_SLEEP_CLK>,
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@6000000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};

44
target/linux/ipq40xx/patches-5.10/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch Normal file
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@@ -0,0 +1,44 @@
From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 9 Sep 2020 21:56:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
Lets add labels to more commonly used nodes for easier modification in board DTS files.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -190,7 +190,7 @@
reg = <0x1800000 0x60000>;
};
- rng@22000 {
+ prng: rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
@@ -300,7 +300,7 @@
status = "disabled";
};
- crypto@8e3a000 {
+ crypto: crypto@8e3a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x08e3a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
@@ -386,7 +386,7 @@
dma-names = "rx", "tx";
};
- watchdog@b017000 {
+ watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
reg = <0xb017000 0x40>;
clocks = <&sleep_clk>;

35
target/linux/ipq40xx/patches-5.10/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch Normal file
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@@ -0,0 +1,35 @@
From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 7 Sep 2020 12:19:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
Since we now have driver for the SDHCI VQMMC LDO needed
for I/0 voltage levels lets introduce the necessary node for it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -209,6 +209,16 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
+ vqmmc: regulator@1948000 {
+ compatible = "qcom,vqmmc-ipq4019-regulator";
+ reg = <0x01948000 0x4>;
+ regulator-name = "vqmmc";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ status = "disabled";
+ };
+
sdhci: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;

115
target/linux/ipq40xx/patches-5.10/104-clk-fix-apss-cpu-overclocking.patch Normal file
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@@ -0,0 +1,115 @@
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Sun, 11 Mar 2018 14:41:31 +0100
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
There's an interaction issue between the clk changes:"
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
" and the cpufreq-dt.
cpufreq-dt is now spamming the kernel-log with the following:
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
for freq 761142857 (-34)
This only happens on certain devices like the Compex WPJ428
and AVM FritzBox!4040. However, other devices like the Asus
RT-AC58U and Meraki MR33 work just fine.
The issue stem from the fact that all higher CPU-Clocks
are achieved by switching the clock-parent to the P_DDRPLLAPSS
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
as part of the DDR calibration.
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
This patch attempts to fix the issue by modifying
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
to use a new qcom_find_freq_close() function, which returns the closest
matching frequency, instead of the next higher. This way, the SoC in
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
try to overclock to 761 MHz.
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *last = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate == f->freq)
+ return f;
+
+ if (f->freq > rate) {
+ if (!last ||
+ (f->freq - rate) < (rate - last->freq))
+ return f;
+ else
+ return last;
+ }
+ last = f;
+ }
+
+ return last;
+}
+
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
u32 mask;
int ret;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1305,6 +1328,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ const struct freq_tbl *f;
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
- return rate;
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return rate;
+
+ return f->freq;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {

52
target/linux/ipq40xx/patches-5.10/300-clk-qcom-ipq4019-add-ess-reset.patch Normal file
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@@ -0,0 +1,52 @@
From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Tue, 28 Mar 2017 22:35:33 +0530
Subject: [PATCH] clk: qcom: ipq4019: add ess reset
Added the ESS reset in IPQ4019 GCC.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
2 files changed, 22 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -165,5 +165,16 @@
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
+#define ESS_MAC1_ARES 72
+#define ESS_MAC2_ARES 73
+#define ESS_MAC3_ARES 74
+#define ESS_MAC4_ARES 75
+#define ESS_MAC5_ARES 76
+#define ESS_PSGMII_ARES 77
+#define ESS_MAC1_CLK_DIS 78
+#define ESS_MAC2_CLK_DIS 79
+#define ESS_MAC3_CLK_DIS 80
+#define ESS_MAC4_CLK_DIS 81
+#define ESS_MAC5_CLK_DIS 82
#endif

48
target/linux/ipq40xx/patches-5.10/301-arm-compressed-add-appended-DTB-section.patch Normal file
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@@ -0,0 +1,48 @@
From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 30 Oct 2020 13:36:31 +0100
Subject: [PATCH] arm: compressed: add appended DTB section
This adds a appended_dtb section to the ARM decompressor
linker script.
This allows using the existing ARM zImage appended DTB support for
appending a DTB to the raw ELF kernel.
Its size is set to 1MB max to match the zImage appended DTB size limit.
To use it to pass the DTB to the kernel, objcopy is used:
objcopy --set-section-flags=.appended_dtb=alloc,contents \
--update-section=.appended_dtb=<target>.dtb vmlinux
This is based off the following patch:
https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -101,6 +101,13 @@ SECTIONS
_edata = .;
+ .appended_dtb : {
+ /* leave space for appended DTB */
+ . += 0x100000;
+ }
+
+ _edata_dtb = .;
+
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
@@ -138,4 +145,4 @@ SECTIONS
ARM_ASSERTS
}
-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");

66
target/linux/ipq40xx/patches-5.10/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch Normal file
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@@ -0,0 +1,66 @@
From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Fri, 23 Oct 2020 19:42:36 +1000
Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
For IPQ40XX systems where the SoC watchdog is activated before linux,
the watchdog timer may be too small for linux to finish uncompress,
boot, and watchdog management start.
If the watchdog is enabled, set the timeout for it to 30 seconds.
The functionality and offsets were copied from:
drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
The watchdog memory address was taken from:
arch/arm/boot/dts/qcom-ipq4019.dtsi
This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
RouterBoot bootloader.
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
---
arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -601,6 +601,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+ /* offsets:
+ * 0x04 reset (=1 resets countdown)
+ * 0x08 enable (=0 disables)
+ * 0x0c status (=1 when SoC was reset by watchdog)
+ * 0x10 bark (=timeout warning in ticks)
+ * 0x14 bite (=timeout reset in ticks)
+ * clock rate is 1<<15 hertz
+ */
+ .equ watchdog, 0x0b017000 @Store watchdog base address
+ movw r0, #:lower16:watchdog
+ movt r0, #:upper16:watchdog
+ ldr r1, [r0, #0x08] @Get enabled?
+ cmp r1, #1 @If not enabled, do not change
+ bne watchdog_finished
+ mov r1, #0
+ str r1, [r0, #0x08] @Disable the watchdog
+ mov r1, #1
+ str r1, [r0, #0x04] @Pet the watchdog
+ mov r1, #30 @30 seconds timeout
+ lsl r1, r1, #15 @converted to ticks
+ str r1, [r0, #0x10] @Set the bark timeout
+ str r1, [r0, #0x14] @Set the bite timeout
+ mov r1, #1
+ str r1, [r0, #0x08] @Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
/*
* The C runtime environment should now be setup sufficiently.
* Set up some pointers, and start decompressing.

24
target/linux/ipq40xx/patches-5.10/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch Normal file
View File

@@ -0,0 +1,24 @@
From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Dec 2020 13:35:35 +0100
Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
When using sdhci_msm_set_clock clock setting will fail, so lets
use the generic sdhci_set_clock.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/host/sdhci-msm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
- .set_clock = sdhci_msm_set_clock,
+ .set_clock = sdhci_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,

46
target/linux/ipq40xx/patches-5.10/702-dts-ipq4019-add-PHY-switch-nodes.patch Normal file
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@@ -0,0 +1,46 @@
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 02:20:54 +0100
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
nodes which are needed for the ar40xx.c driver to initialize the
switch.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -616,6 +616,29 @@
};
};
+ ess-switch@c000000 {
+ compatible = "qcom,ess-switch";
+ reg = <0xc000000 0x80000>;
+ switch_access_mode = "local bus";
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
+ switch_initvlas = <0x7c 0x54>;
+ status = "disabled";
+ };
+
+ ess-psgmii@98000 {
+ compatible = "qcom,ess-psgmii";
+ reg = <0x98000 0x800>;
+ psgmii_access_mode = "local bus";
+ status = "disabled";
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;

53
target/linux/ipq40xx/patches-5.10/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch Normal file
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@@ -0,0 +1,53 @@
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
From: Rakesh Nair <ranair@codeaurora.org>
Date: Wed, 20 Jul 2016 15:02:01 +0530
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
netdev_ops
Add callback support to get default vlan tag and register
receive flow steering filter.
Used by IPQ4019 ess-edma driver.
BUG=chrome-os-partner:33096
TEST=none
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/362203
Commit-Ready: Grant Grundler <grundler@chromium.org>
Tested-by: Grant Grundler <grundler@chromium.org>
Reviewed-by: Grant Grundler <grundler@chromium.org>
---
include/linux/netdevice.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -765,6 +765,16 @@ struct xps_map {
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
- sizeof(struct xps_map)) / sizeof(u16))
+#ifdef CONFIG_RFS_ACCEL
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
+ __be32 src,
+ __be32 dst,
+ __be16 sport,
+ __be16 dport,
+ u8 proto,
+ u16 rxq_index,
+ u32 action);
+#endif
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.
*/
@@ -1445,6 +1455,9 @@ struct net_device_ops {
const struct sk_buff *skb,
u16 rxq_index,
u32 flow_id);
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
+ set_rfs_filter_callback_t set_filter);
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
#endif
int (*ndo_add_slave)(struct net_device *dev,
struct net_device *slave_dev,

27
target/linux/ipq40xx/patches-5.10/705-net-add-qualcomm-ar40xx-phy.patch Normal file
View File

@@ -0,0 +1,27 @@
--- a/drivers/net/mdio/Kconfig
+++ b/drivers/net/mdio/Kconfig
@@ -27,6 +27,13 @@ config OF_MDIO
help
OpenFirmware MDIO bus (Ethernet PHY) accessors
+config AR40XX_PHY
+ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
+ depends on HAS_IOMEM && OF && OF_MDIO
+ select SWCONFIG
+ help
+ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
+
if MDIO_BUS
config MDIO_DEVRES
--- a/drivers/net/mdio/Makefile
+++ b/drivers/net/mdio/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.
obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
+obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
+
obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o

61
target/linux/ipq40xx/patches-5.10/706-dt-bindings-net-add-QCA807x-PHY.patch Normal file
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@@ -0,0 +1,61 @@
From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
--- /dev/null
+++ b/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device Tree constants for the Qualcomm QCA807X PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
+#define _DT_BINDINGS_QCOM_QCA807X_H
+
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+/* Default value */
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/* Full amplitude, full bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+/* Both amplitude and bias current follow DSP */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+/* Full amplitude, half bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
+ * otherwise half bias current
+ */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+/* Full amplitude; same bias current setting with “010” and “011”,
+ * but half more bias is reduced when cable <10m
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+/* Amplitude follow DSP; same bias current setting with “110”, default value */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif

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