Initial commit

This commit is contained in:
domenico
2025-06-24 13:14:22 +02:00
commit 4002f145fc
9002 changed files with 1731834 additions and 0 deletions

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# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2012-2015 OpenWrt.org
include $(TOPDIR)/rules.mk
BOARD:=mvebu
BOARDNAME:=Marvell EBU Armada
FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard
SUBTARGETS:=cortexa9 cortexa53 cortexa72
KERNEL_PATCHVER:=5.10
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += uboot-envtools kmod-gpio-button-hotplug
$(eval $(call BuildTarget))

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# Copyright (C) 2015 OpenWrt.org
. /lib/functions.sh
. /lib/upgrade/common.sh
move_config() {
local partdev
if export_bootdevice && export_partdevice partdev 1; then
case $(board_name) in
cznic,turris-omnia)
insmod nls_cp437
insmod nls_iso8859-1
insmod fat
insmod vfat
;;
esac
mkdir -p /boot
mount -o rw,noatime "/dev/$partdev" /boot
[ -f "/boot/$BACKUP_FILE" ] && mv -f "/boot/$BACKUP_FILE" /
umount /boot
fi
}
boot_hook_add preinit_mount_root move_config

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CONFIG_AHCI_MVEBU=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARMADA_370_CLK=y
CONFIG_ARMADA_370_XP_IRQ=y
CONFIG_ARMADA_370_XP_TIMER=y
# CONFIG_ARMADA_37XX_WATCHDOG is not set
CONFIG_ARMADA_38X_CLK=y
CONFIG_ARMADA_THERMAL=y
CONFIG_ARMADA_XP_CLK=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATA=y
CONFIG_ATAGS=y
CONFIG_ATA_LEDS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_FEROCEON_L2 is not set
CONFIG_CACHE_L2X0=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PJ4B=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_MARVELL=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRYPTO_ESSIV=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM=y
CONFIG_CRYPTO_SHA1_ARM_NEON=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MVEBU_UART0=y
# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0xd0012000
CONFIG_DEBUG_UART_VIRT=0xfec12000
CONFIG_DEBUG_UNCOMPRESS=y
CONFIG_DEBUG_USER=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_MVEBU=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HOTPLUG_CPU=y
CONFIG_HWBM=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_PXA is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_IWMMXT is not set
CONFIG_JBD2=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MACH_ARMADA_370=y
# CONFIG_MACH_ARMADA_375 is not set
CONFIG_MACH_ARMADA_38X=y
# CONFIG_MACH_ARMADA_39X is not set
CONFIG_MACH_ARMADA_XP=y
# CONFIG_MACH_DOVE is not set
CONFIG_MACH_MVEBU_ANY=y
CONFIG_MACH_MVEBU_V7=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MANGLE_BOOTARGS=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_I2C=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_MVSDIO=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_PXAV3=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_MVEBU_CLK_COMMON=y
CONFIG_MVEBU_CLK_COREDIV=y
CONFIG_MVEBU_CLK_CPU=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_MVEBU_MBUS=y
CONFIG_MVMDIO=y
CONFIG_MVNETA=y
CONFIG_MVNETA_BM=y
CONFIG_MVNETA_BM_ENABLE=y
# CONFIG_MVPP2 is not set
CONFIG_MV_XOR=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
CONFIG_NET_DSA_TAG_DSA=y
CONFIG_NET_DSA_TAG_EDSA=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_ORION_WATCHDOG=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PCI=y
CONFIG_PCI_BRIDGE_EMUL=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_MVEBU=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
CONFIG_PHY_MVEBU_A38X_COMPHY=y
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_370=y
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_PINCTRL_ARMADA_XP=y
CONFIG_PINCTRL_MVEBU=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PJ4B_ERRATA_4742=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PLAT_ORION=y
CONFIG_PM_OPP=y
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_ARMADA38X=y
CONFIG_RTC_DRV_MV=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_SATA_HOST=y
CONFIG_SATA_MV=y
CONFIG_SATA_PMP=y
CONFIG_SCSI=y
CONFIG_SENSORS_PWM_FAN=y
CONFIG_SENSORS_TMP421=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MVEBU_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SFP=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOC_BUS=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
# CONFIG_SPI_ARMADA_3700 is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_ORION=y
CONFIG_SRAM=y
CONFIG_SRAM_EXEC=y
CONFIG_SRCU=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_ORION=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

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# SPDX-License-Identifier: GPL-2.0-only
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
glinet,gl-mv1000)
ucidef_set_led_netdev "wan" "WAN" "green:wan" "wan"
;;
esac
board_config_flush
exit 0

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#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc)
ucidef_set_interfaces_lan_wan "lan0 lan1" "wan"
;;
globalscale,espressobin-ultra)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "wan"
;;
marvell,armada-3720-db|\
methode,udpu)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
*)
ucidef_set_interface_lan "eth0"
;;
esac
board_config_flush
exit 0

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#
# Copyright (C) 2014-2019 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
preinit_mount_udpu() {
. /lib/functions.sh
. /lib/upgrade/common.sh
case $(board_name) in
methode,udpu)
# Check which device is detected
[ -b "/dev/mmcblk0" ] && mmcdev="/dev/mmcblk0" || mmcdev="/dev/mmcblk1"
if [ -b "${mmcdev}p4" ]; then
mkdir /misc
mount -t f2fs ${mmcdev}p4 /misc
[ -f "/misc/$BACKUP_FILE" ] && {
echo "- Restoring configuration files -"
tar xzf "/misc/$BACKUP_FILE" -C /
rm -f "/misc/$BACKUP_FILE"
sync
}
[ -f "/misc/firmware/recovery.itb" ] && {
echo "- Updating /recovery partition -"
mkfs.ext4 -q ${mmcdev}p2 | echo y &> /dev/null
mkdir -p /tmp/recovery
mount ${mmcdev}p2 /tmp/recovery
cp /misc/firmware/recovery.itb /tmp/recovery
[ -f "/misc/firmware/boot.scr" ] && \
cp /misc/firmware/boot.scr /tmp/recovery
sync
umount /tmp/recovery
rm -rf /tmp/recovery
# Replace previous backup with the new one
[ -d "/misc/firmware_old" ] && rm -rf /misc/firmware_old
[ -d "/misc/firmware" ] && mv /misc/firmware /misc/firmware_old
}
fi
# Legacy support - if rootfs was booted, instruct u-boot to keep the current root dev
[ "$(df | grep /dev/root)" ] && fw_setenv root_ok '2'
;;
esac
}
boot_hook_add preinit_main preinit_mount_udpu

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#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc)
legacy_sdcard_check_image "$1"
;;
*)
return 0
;;
esac
}
platform_do_upgrade() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc)
legacy_sdcard_do_upgrade "$1"
;;
methode,udpu)
platform_do_upgrade_uDPU "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}
platform_copy_config() {
case "$(board_name)" in
glinet,gl-mv1000|\
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc)
legacy_sdcard_copy_config
;;
methode,udpu)
platform_copy_config_uDPU
;;
esac
}

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udpu_check_emmc() {
# uDPU uses combined ext4 and f2fs partitions.
# partition layout:
# 1. boot (ext4)
# 2. recovery (ext4)
# 3. rootfs (f2fs)
# 4. misc (f2fs)
# Check which device is available, depending on the board revision
if [ -b "/dev/mmcblk1" ]; then
emmc_dev=/dev/mmcblk1
elif [ -b "/dev/mmcblk0" ]; then
emmc_dev=/dev/mmcblk0
else
echo "Cannot detect eMMC flash, aborting.."
exit 1
fi
}
udpu_part_prep() {
if [ "$(grep $1 /proc/mounts)" ]; then
mounted_part="$(grep $1 /proc/mounts | awk '{print $2}' | head -1)"
umount $mounted_part
[ "$(grep -wo $mounted_part /proc/mounts)" ] && umount -l $mounted_part
fi
}
udpu_do_part_check() {
local emmc_parts="1 2 3 4"
local part_valid="1"
# Check if the block devices exist
for num in ${emmc_parts}; do
[ ! -b ${emmc_dev}p${num} ] && part_valid="0"
done
# If partitions are missing create a new partition table
if [ "$part_valid" != "1" ]; then
printf "Invalid partition table, creating a new one\n"
printf "o\nn\np\n1\n\n+256M\nn\np\n2\n\n+256M\nn\np\n3\n\n+1536M\nn\np\n\n\nw\n" | fdisk -W always $emmc_dev > /dev/null 2>&1
# Format the /misc part right away as we will need it for the firmware
printf "Formating /misc partition, this make take a while..\n"
udpu_part_prep ${emmc_dev}p4
mkfs.f2fs -q -l misc ${emmc_dev}p4
[ $? -eq 0 ] && printf "/misc partition formated successfully\n" || printf "/misc partition formatting failed\n"
udpu_do_initial_setup
else
printf "Partition table looks ok\n"
fi
}
udpu_do_misc_prep() {
if [ ! "$(grep -wo /misc /proc/mounts)" ]; then
mkdir -p /misc
mount ${emmc_dev}p4 /misc
# If the mount fails, try to reformat partition
# Leaving possiblity for multiple iterations
if [ $? -ne 0 ]; then
printf "Error while mounting /misc, trying to reformat..\n"
format_count=0
while [ "$format_count" -lt "1" ]; do
udpu_part_prep ${emmc_dev}p4
mkfs.f2fs -q -l misc ${emmc_dev}p4
mount ${emmc_dev}p4 /misc
if [ $? -ne 0 ]; then
umount -l /misc
printf "Failed while mounting /misc\n"
format_count=$((format_count +1))
else
printf "Mounted /misc successfully\n"
break
fi
done
fi
fi
}
udpu_do_initial_setup() {
# Prepare /recovery parition
udpu_part_prep ${emmc_dev}p2
mkfs.ext4 -q ${emmc_dev}p2 | echo y &> /dev/null
# Prepare /boot partition
udpu_part_prep ${emmc_dev}p1
mkfs.ext4 -q ${emmc_dev}p1 | echo y &> /dev/null
# Prepare /root partition
printf "Formating /root partition, this may take a while..\n"
udpu_part_prep ${emmc_dev}p3
mkfs.f2fs -q -l rootfs ${emmc_dev}p3
[ $? -eq 0 ] && printf "/root partition reformated\n"
}
udpu_do_regular_upgrade() {
# Clean /boot partition - mfks.ext4 is not available in chroot
[ "$(grep -wo /boot /proc/mounts)" ] && umount /boot
mkdir -p /tmp/boot
mount ${emmc_dev}p1 /tmp/boot
rm -rf /tmp/boot/*
# Clean /root partition - mkfs.f2fs is not available in chroot
[ "$(grep -wo /dev/root /proc/mounts)" ] && umount /
mkdir -p /tmp/rootpart
mount ${emmc_dev}p3 /tmp/rootpart
rm -rf /tmp/rootpart/*
}
platform_do_upgrade_uDPU() {
udpu_check_emmc
# Prepare and extract firmware on /misc partition
udpu_do_misc_prep
[ -f "/misc/firmware" ] && rm -r /misc/firmware
mkdir -p /misc/firmware
tar xzf "$1" -C /misc/firmware/
udpu_do_regular_upgrade
printf "Updating /boot partition\n"
tar xzf /misc/firmware/boot.tgz -C /tmp/boot
[ $? -eq 0 ] && printf "/boot partition updated successfully\n" || printf "/boot partition update failed\n"
sync
printf "Updating /root partition\n"
tar xzf /misc/firmware/rootfs.tgz -C /tmp/rootpart
[ $? -eq 0 ] && printf "/root partition updated successfully\n" || printf "/root partition update failed\n"
sync
# Saving configuration files over sysupgrade
platform_copy_config_uDPU
# Remove tmp mounts
tmp_parts=$(grep "${emmc_dev}" /proc/mounts | awk '{print $2}')
for part in ${tmp_parts}; do
umount $part
# Force umount is necessary
[ "$(grep "${part}" /proc/mounts)" ] && umount -l $part
done
# Sysupgrade complains about /tmp and /dev, so we can detach them here
umount -l /tmp
umount -l /dev
}
platform_copy_config_uDPU() {
# Config is saved on the /misc partition and copied on the rootfs after the reboot
if [ -f "$UPGRADE_BACKUP" ]; then
cp -f "$UPGRADE_BACKUP" "/misc/$BACKUP_FILE"
sync
fi
}

View File

@@ -0,0 +1,79 @@
CONFIG_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_DMA_DIRECT_REMAP=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FRAME_POINTER=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_PINCONF=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI_AARDVARK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_A3700_COMPHY=y
CONFIG_PHY_MVEBU_A3700_UTMI=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POWER_RESET=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_REGULATOR_GPIO=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPI_ARMADA_3700=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

View File

@@ -0,0 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2017 Hauke Mehrtens
include $(TOPDIR)/rules.mk
ARCH:=aarch64
BOARDNAME:=Marvell Armada 3700LP (ARM64)
CPU_TYPE:=cortex-a53
FEATURES+=ext4
DEFAULT_PACKAGES+=e2fsprogs ethtool mkf2fs partx-utils
KERNELNAME:=Image dtbs

View File

@@ -0,0 +1,39 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
globalscale,mochabin)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth0 eth2"
;;
iei,puzzle-m901)
ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
;;
iei,puzzle-m902)
ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
;;
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
ucidef_set_interfaces_lan_wan "eth0 eth1 eth3" "eth2"
;;
marvell,armada8040-db)
ucidef_set_interfaces_lan_wan "eth0 eth2 eth3" "eth1"
;;
marvell,armada7040-db)
ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1"
;;
*)
ucidef_set_interface_lan "eth0"
;;
esac
board_config_flush
exit 0

View File

@@ -0,0 +1,36 @@
platform_do_upgrade_emmc() {
local board=$(board_name)
local diskdev partdev
export_bootdevice && export_partdevice diskdev 0 || {
v "Unable to determine upgrade device"
return 1
}
sync
if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
get_partitions "/dev/$diskdev" bootdisk
v "Extract boot sector from the image"
get_image_dd "$1" of=/tmp/image.bs count=1 bs=512b
get_partitions /tmp/image.bs image
fi
#iterate over each partition from the image and write it to the boot disk
while read part start size; do
if export_partdevice partdev $part; then
if [ "$partdev" = "mmcblk0p2" ]; then
v "Writing image mmcblk0p3 for /dev/$partdev $start $size"
get_image_dd "$1" of="/dev/mmcblk0p3" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
elif [ "$partdev" = "mmcblk0p1" ]; then
v "Writing image mmcblk0p1 for /dev/$partdev $start $size"
get_image_dd "$1" of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
fi
else
v "Unable to find partition $part device, skipped."
fi
done < /tmp/partmap.image
v "Writing new UUID to /dev/$diskdev..."
get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
sleep 1
}

View File

@@ -0,0 +1,51 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
globalscale,mochabin|\
iei,puzzle-m901|\
iei,puzzle-m902|\
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
legacy_sdcard_check_image "$1"
;;
*)
return 0
;;
esac
}
platform_do_upgrade() {
case "$(board_name)" in
iei,puzzle-m901|\
iei,puzzle-m902)
platform_do_upgrade_emmc "$1"
;;
globalscale,mochabin|\
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
legacy_sdcard_do_upgrade "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}
platform_copy_config() {
case "$(board_name)" in
globalscale,mochabin|\
iei,puzzle-m901|\
iei,puzzle-m902|\
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
legacy_sdcard_copy_config
;;
esac
}

View File

@@ -0,0 +1,93 @@
CONFIG_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
# CONFIG_ARM64_PTR_AUTH is not set
CONFIG_ARM64_SVE=y
# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DMA_DIRECT_REMAP=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FRAME_POINTER=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_PINCONF=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_HW_RANDOM_OMAP=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LEDS_IS31FL319X=y
CONFIG_MARVELL_10G_PHY=y
CONFIG_MDIO_DEVRES=y
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_MVPP2=y
CONFIG_MV_XOR_V2=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCI_AARDVARK is not set
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POWER_RESET=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_XXHASH=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

View File

@@ -0,0 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2018 Sartura Ltd.
include $(TOPDIR)/rules.mk
ARCH:=aarch64
BOARDNAME:=Marvell Armada 7k/8k (ARM64)
CPU_TYPE:=cortex-a72
FEATURES+=ext4
DEFAULT_PACKAGES+=e2fsprogs ethtool mkf2fs partx-utils
KERNELNAME:=Image dtbs

View File

@@ -0,0 +1,57 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
boardname="${board##*,}"
case "$board" in
kobol,helios4)
ucidef_set_led_usbport "USB" "USB" "helios4:green:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1" "usb5-port1"
;;
linksys,wrt1200ac)
ucidef_set_led_netdev "wan" "WAN" "pca963x:caiman:white:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "pca963x:caiman:white:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "pca963x:caiman:white:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "pca963x:caiman:white:usb3_2" "usb3-port1"
;;
linksys,wrt1900ac-v1)
ucidef_set_led_netdev "wan" "WAN" "mamba:white:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "mamba:white:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "mamba:white:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "mamba:white:usb3_2" "usb3-port2"
;;
linksys,wrt1900ac-v2)
ucidef_set_led_netdev "wan" "WAN" "pca963x:cobra:white:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "pca963x:cobra:white:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "pca963x:cobra:white:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "pca963x:cobra:white:usb3_2" "usb3-port1"
;;
linksys,wrt1900acs)
ucidef_set_led_netdev "wan" "WAN" "pca963x:shelby:white:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "pca963x:shelby:white:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "pca963x:shelby:white:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "pca963x:shelby:white:usb3_2" "usb3-port1"
;;
linksys,wrt3200acm)
ucidef_set_led_netdev "wan" "WAN" "pca963x:rango:white:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "pca963x:rango:white:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "pca963x:rango:white:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "pca963x:rango:white:usb3_2" "usb3-port1"
;;
linksys,wrt32x)
ucidef_set_led_netdev "wan" "WAN" "pca963x:venom:blue:wan" "wan"
ucidef_set_led_usbport "usb1" "USB 1" "pca963x:venom:blue:usb2" "usb1-port1"
ucidef_set_led_usbport "usb2" "USB 2" "pca963x:venom:blue:usb3_1" "usb2-port1" "usb3-port1"
ucidef_set_led_usbport "usb2_ss" "USB 2 SS" "pca963x:venom:blue:usb3_2" "usb3-port1"
;;
esac
board_config_flush
exit 0

View File

@@ -0,0 +1,87 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
mvebu_setup_interfaces()
{
local board="$1"
case "$board" in
cznic,turris-omnia)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 lan4" "eth2"
;;
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
marvell,a385-db-ap)
ucidef_set_interfaces_lan_wan "eth0 eth1" "eth2"
;;
marvell,axp-gp)
ucidef_set_interface_lan "eth0 eth1 eth2 eth3"
;;
solidrun,clearfog-base-a1)
# eth0 is standalone ethernet
# eth1 is standalone ethernet
# eth2 is SFP
ucidef_set_interfaces_lan_wan "eth1" "eth0 eth2"
;;
solidrun,clearfog-pro-a1)
# eth0 is standalone ethernet
# eth1 is switch
# eth2 is SFP
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5 lan6" "eth0 eth2"
;;
*)
ucidef_set_interface_lan "eth0"
;;
esac
}
mvebu_setup_macs()
{
local board="$1"
local lan_mac=""
local wan_mac=""
local label_mac=""
case "$board" in
buffalo,ls421de)
lan_mac=$(mtd_get_mac_ascii u-boot-env eth1addr)
;;
linksys,wrt1200ac|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
wan_mac=$(macaddr_setbit_la $label_mac)
;;
linksys,wrt1900ac-v1)
label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
lan_mac=$label_mac
wan_mac=$label_mac
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
}
board_config_update
board=$(board_name)
mvebu_setup_interfaces $board
mvebu_setup_macs $board
board_config_flush
exit 0

View File

@@ -0,0 +1,25 @@
#
# Copyright (C) 2020 OpenWrt.org
#
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x|\
solidrun,clearfog-base-a1|\
solidrun,clearfog-pro-a1)
ucidef_set_compat_version "1.1"
;;
esac
board_config_flush
exit 0

View File

@@ -0,0 +1,41 @@
#!/bin/sh
# The pcie-controller device was renamed to pcie in Linux kernel 4.14
# commit 28fbb9c539e2 ("ARM: dts: marvell: fix PCI bus dtc warnings").
# This script migrates the path in the UCI configuration from the old
# name to the new name and also back, when am upgrade or downgrade is
# done. It checks if the name exists before changing the configuration.
# This has to be done before the 10-wifi-detect script from mac80211 is
# executed because this would add the devices again under the new path
# name.
. /lib/functions.sh
PATH_CHANGED=0
rename_wifi_path() {
local path_old=$(uci get wireless.${1}.path)
local path_new=$(echo ${path_old} | sed "${2}")
if [ -e "/sys/devices/platform/${path_new}" ] && [ ${path_old} != ${path_new} ]
then
uci set wireless.${1}.path=${path_new}
PATH_CHANGED=1
fi
}
rename_wifi_path_list() {
# migration from kernel 4.9 to 4.14
rename_wifi_path $1 "s/soc:pcie-controller/soc:pcie/"
# migration from kernel 4.14 to 4.9
rename_wifi_path $1 "s/soc:pcie/soc:pcie-controller/"
}
[ "${ACTION}" = "add" ] && {
[ ! -e /etc/config/wireless ] && return
config_load wireless
config_foreach rename_wifi_path_list wifi-device
[ "$PATH_CHANGED" = "1" ] && uci commit wireless
}

View File

@@ -0,0 +1,16 @@
#!/bin/sh /etc/rc.common
START=99
boot() {
case $(board_name) in
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
mtd resetbc s_env || true
;;
esac
}

View File

@@ -0,0 +1,60 @@
#
# Copyright (C) 2015 OpenWrt.org
#
[ ! -e /etc/config/wireless ] && exit 0
. /lib/functions.sh
. /lib/functions/system.sh
board=$(board_name)
case "$board" in
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
SKU=$(strings /dev/mtd3|sed -ne 's/^cert_region=//p')
WIFIMAC2G=$(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1)
WIFIMAC5G=$(macaddr_add $WIFIMAC2G 1)
case "$SKU" in
AP)
REGD=CN
;;
AU)
REGD=AU
;;
CA)
REGD=CA
;;
EU)
REGD=FR
;;
US)
REGD=US
;;
esac
case "$board" in
linksys,wrt1900ac-v1)
WIFIMAC0=$WIFIMAC2G
WIFIMAC1=$WIFIMAC5G
;;
*)
WIFIMAC0=$WIFIMAC5G
WIFIMAC1=$WIFIMAC2G
;;
esac
uci get wireless.radio0.country || uci set wireless.radio0.country=$REGD
uci get wireless.@wifi-iface[0].macaddr || uci set wireless.@wifi-iface[0].macaddr=$WIFIMAC0
uci get wireless.radio1.country || uci set wireless.radio1.country=$REGD
uci get wireless.@wifi-iface[1].macaddr || uci set wireless.@wifi-iface[1].macaddr=$WIFIMAC1
;;
esac
uci commit wireless
exit 0

View File

@@ -0,0 +1,22 @@
#
# Copyright (C) 2017 LEDE-Project.org
#
. /lib/functions.sh
board=$(board_name)
case "$board" in
linksys,wrt1900ac-v1)
# Set fan script execution in crontab
grep -s -q fan_ctrl.sh /etc/crontabs/root && exit 0
echo "# mamba fan script runs every 5 minutes" >> /etc/crontabs/root
echo "*/5 * * * * /sbin/fan_ctrl.sh" >> /etc/crontabs/root
# Execute one time after initial flash (instead of waiting 5 min for cron)
/sbin/fan_ctrl.sh
;;
esac
exit 0

View File

@@ -0,0 +1,11 @@
. /lib/functions.sh
case "$(board_name)" in
linksys,wrt1900ac-v1|\
linksys,wrt32x)
uci set system.@system[0].compat_version="2.0"
uci commit system
;;
esac
exit 0

View File

@@ -0,0 +1,44 @@
# This must be sourced after 30_uboot-envtools
. /lib/functions.sh
board=$(board_name)
case "$board" in
cznic,turris-omnia)
# Do nothing if this is not the old U-Boot
grep -q 'U-Boot 2015.10-rc2' /dev/mtd0 || exit 0
# Do nothing if we already have distro_bootcmd
fw_printenv distro_bootcmd >/dev/null 2>/dev/null && exit 0
# Set the complete environment, since U-Boot does not merge the default environment from its own image!
fw_setenv -s - <<-"EOF"
baudrate 115200
bootdelay 3
ethact neta2
fdt_high 0x10000000
initrd_high 0x10000000
bootargs earlyprintk console=ttyS0,115200 rootfstype=btrfs rootdelay=2 root=b301 rootflags=subvol=@,commit=5 rw
bootcmd i2c dev 1; i2c read 0x2a 0x9 1 0x00FFFFF0; setexpr.b rescue *0x00FFFFF0; if test $rescue -ge 1; then echo BOOT RESCUE; run rescueboot; else echo BOOT eMMC FS; run mmcboot; setenv bootargs; run distro_bootcmd; fi
rescueboot i2c mw 0x2a.1 0x3 0x1c 1; i2c mw 0x2a.1 0x4 0x1c 1; mw.l 0x01000000 0x00ff000c; i2c write 0x01000000 0x2a.1 0x5 4 -s; setenv bootargs "$bootargs omniarescue=$rescue"; sf probe; sf read 0x1000000 0x100000 0x700000; bootz 0x1000000
mmcboot btrload mmc 0 ${kernel_addr_r} boot/zImage @ && btrload mmc 0 ${fdt_addr_r} boot/dtb @ && setenv bootargs ${bootargs} cfg80211.freg=${regdomain} && bootz ${kernel_addr_r} - ${fdt_addr_r}
kernel_addr_r 0x1000000
scriptaddr 0x1800000
fdt_addr_r 0x2000000
boot_targets mmc0 scsi0
boot_prefixes / /boot/
boot_scripts boot.scr
distro_bootcmd scsi_need_init=true; for target in ${boot_targets}; do run bootcmd_${target}; done
bootcmd_mmc0 devnum=0; run mmc_boot
mmc_boot if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
bootcmd_scsi0 devnum=0; run scsi_boot
scsi_boot run scsi_init; if scsi dev ${devnum}; then devtype=scsi; run scan_dev_for_boot_part; fi
scsi_init if ${scsi_need_init}; then scsi_need_init=false; scsi scan; fi
scan_dev_for_boot_part for distro_bootpart in 1; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done
scan_dev_for_boot echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_scripts; done
scan_dev_for_scripts for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done
boot_a_script load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
EOF
;;
esac
exit 0

View File

@@ -0,0 +1,42 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
preinit_mount_syscfg() {
. /lib/functions.sh
. /lib/upgrade/common.sh
case $(board_name) in
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
needs_recovery=0
syscfg_part=$(grep syscfg /proc/mtd |cut -c4)
ubiattach -m $syscfg_part || needs_recovery=1
if [ $needs_recovery -eq 1 ]
then
echo "ubifs syscfg partition is damaged, reformatting"
ubidetach -m $syscfg_part
ubiformat -y -O 2048 -q /dev/mtd$syscfg_part
ubiattach -m $syscfg_part
ubimkvol /dev/ubi1 -n 0 -N syscfg -t dynamic --maxavsize
fi
mkdir /tmp/syscfg
mount -t ubifs ubi1:syscfg /tmp/syscfg
[ -f "/tmp/syscfg/$BACKUP_FILE" ] && {
echo "- config restore -"
cd /
mv "/tmp/syscfg/$BACKUP_FILE" /tmp
tar xzf "/tmp/$BACKUP_FILE"
rm -f "/tmp/$BACKUP_FILE"
sync
}
;;
esac
}
boot_hook_add preinit_main preinit_mount_syscfg

View File

@@ -0,0 +1,98 @@
#
# Copyright (C) 2014-2015 OpenWrt.org
#
linksys_get_target_firmware() {
local cur_boot_part mtd_ubi0
cur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)
if [ -z "${cur_boot_part}" ] ; then
mtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)
case $(egrep ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in
kernel1|rootfs1)
cur_boot_part=1
;;
kernel2|rootfs2)
cur_boot_part=2
;;
esac
>&2 printf "Current boot_part='%s' selected from ubi0/mtd_num='%s'" \
"${cur_boot_part}" "${mtd_ubi0}"
fi
case $cur_boot_part in
1)
fw_setenv -s - <<-EOF
boot_part 2
bootcmd "run altnandboot"
EOF
printf "kernel2"
return
;;
2)
fw_setenv -s - <<-EOF
boot_part 1
bootcmd "run nandboot"
EOF
printf "kernel1"
return
;;
*)
return
;;
esac
}
linksys_get_root_magic() {
(get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null
}
platform_do_upgrade_linksys() {
local magic_long="$(get_magic_long "$1")"
mkdir -p /var/lock
local part_label="$(linksys_get_target_firmware)"
touch /var/lock/fw_printenv.lock
if [ ! -n "$part_label" ]
then
v "cannot find target partition"
exit 1
fi
local target_mtd=$(find_mtd_part $part_label)
[ "$magic_long" = "73797375" ] && {
CI_KERNPART="$part_label"
if [ "$part_label" = "kernel1" ]
then
CI_UBIPART="rootfs1"
else
CI_UBIPART="rootfs2"
fi
nand_upgrade_tar "$1"
}
[ "$magic_long" = "27051956" -o "$magic_long" = "0000a0e1" ] && {
# check firmwares' rootfs types
local target_mtd=$(find_mtd_part $part_label)
local oldroot="$(linksys_get_root_magic $target_mtd)"
local newroot="$(linksys_get_root_magic "$1")"
if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ]
# we're upgrading from a firmware with UBI to one with UBI
then
# erase everything to be safe
mtd erase $part_label
get_image "$1" | mtd -n write - $part_label
else
get_image "$1" | mtd write - $part_label
fi
}
}
platform_copy_config_linksys() {
cp -f "$UPGRADE_BACKUP" "/tmp/syscfg/$BACKUP_FILE"
sync
}

View File

@@ -0,0 +1,65 @@
#
# Copyright (C) 2014-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-Project.org
#
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
cznic,turris-omnia|\
kobol,helios4|\
solidrun,clearfog-base-a1|\
solidrun,clearfog-pro-a1)
legacy_sdcard_check_image "$1"
;;
*)
return 0
;;
esac
}
platform_do_upgrade() {
case "$(board_name)" in
buffalo,ls421de)
nand_do_upgrade "$1"
;;
cznic,turris-omnia|\
kobol,helios4|\
solidrun,clearfog-base-a1|\
solidrun,clearfog-pro-a1)
legacy_sdcard_do_upgrade "$1"
;;
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
platform_do_upgrade_linksys "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}
platform_copy_config() {
case "$(board_name)" in
cznic,turris-omnia|\
kobol,helios4|\
solidrun,clearfog-base-a1|\
solidrun,clearfog-pro-a1)
legacy_sdcard_copy_config
;;
linksys,wrt1200ac|\
linksys,wrt1900ac-v1|\
linksys,wrt1900ac-v2|\
linksys,wrt1900acs|\
linksys,wrt3200acm|\
linksys,wrt32x)
platform_copy_config_linksys
;;
esac
}

View File

@@ -0,0 +1,28 @@
#!/bin/sh
CPU_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon2/temp1_input)
DDR_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon1/temp1_input)
WIFI_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon1/temp2_input)
CPU_LOW=85
CPU_HIGH=95
DDR_LOW=65
DDR_HIGH=75
WIFI_LOW=100
WIFI_HIGH=115
if [ -d /sys/devices/pwm_fan ];then
FAN_CTRL=/sys/devices/pwm_fan/hwmon/hwmon0/pwm1
elif [ -d /sys/devices/platform/pwm_fan ];then
FAN_CTRL=/sys/devices/platform/pwm_fan/hwmon/hwmon0/pwm1
else
exit 0
fi
if [ "$CPU_TEMP" -ge "$CPU_HIGH" -o "$DDR_TEMP" -ge "$DDR_HIGH" -o "$WIFI_TEMP" -ge "$WIFI_HIGH" ];then
echo "255" > $FAN_CTRL
elif [ "$CPU_TEMP" -ge "$CPU_LOW" -o "$DDR_TEMP" -ge "$DDR_LOW" -o "$WIFI_TEMP" -ge "$WIFI_LOW" ];then
echo "100" > $FAN_CTRL
else
echo "0" > $FAN_CTRL
fi

View File

@@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2017 Hauke Mehrtens
include $(TOPDIR)/rules.mk
ARCH:=arm
BOARDNAME:=Marvell Armada 37x/38x/XP
CPU_TYPE:=cortex-a9
CPU_SUBTYPE:=vfpv3-d16
KERNELNAME:=zImage dtbs

View File

@@ -0,0 +1,448 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device Tree file for Buffalo LinkStation LS421DE
*
* Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
*/
/dts-v1/;
#include "armada-370.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Buffalo LinkStation LS421DE";
compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp";
aliases {
led-boot = &led_boot;
led-failsafe = &led_failsafe;
led-running = &led_power;
led-upgrade = &led_upgrade;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
append-rootblock = "nullparameter="; /* override the bootloader args */
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
};
system_fan: gpio_fan {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
&gpio0 14 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
};
thermal-zones {
hdd-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
trips {
hdd_alert1: trip1 {
temperature = <36000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert2: trip2 {
temperature = <44000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert3: trip3 {
temperature = <52000>;
hysteresis = <2000>;
type = "passive";
};
hdd_crit: trip4 {
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&hdd_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&hdd_alert2>;
cooling-device = <&system_fan 2 2>;
};
map3 {
trip = <&hdd_alert3>;
cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
};
};
};
ethphy-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&ethphy0>;
trips {
ethphy_alert1: trip1 {
temperature = <65000>;
hysteresis = <4000>;
type = "passive";
};
ethphy_crit: trip2 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&ethphy_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
power {
label = "Power Switch";
linux,code = <KEY_POWER>;
linux,input-type = <EV_SW>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
function {
label = "Function Button";
linux,code = <KEY_CONFIG>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
system_red {
label = "ls421de:red:system";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
led_power: power_white {
label = "ls421de:white:power";
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_failsafe: power_red {
label = "ls421de:red:power";
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
led_upgrade: power_orange {
label = "ls421de:orange:power";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
led_boot: system_white {
label = "ls421de:white:system";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
hdd1_red {
label = "ls421de:red:hdd1";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata1";
};
hdd2_red {
label = "ls421de:red:hdd2";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata2";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;
pinctrl-names = "default";
usb_power: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "USB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
};
sata1_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "HDD1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
};
sata2_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "HDD2";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
};
&coherencyfab {
broken-idle;
};
&eth1 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
rs5c372a: rs5c372a@32 {
compatible = "ricoh,rs5c372a";
reg = <0x32>;
wakeup-source;
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
reg = <0>;
marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
<0x3 0x10 0x0000 0x1991>, /* LED function */
<0x3 0x11 0x0000 0x4401>, /* LED polarity */
<0x3 0x12 0x0000 0x4905>; /* LED timer */
#thermal-sensor-cells = <0>;
};
};
&pciec {
status = "okay";
pinctrl-0 = <&pmx_pcie>;
pinctrl-names = "default";
/* Connected to uPD720202 USB 3.0 Host */
pcie@1,0 {
status = "okay";
};
};
&pmsu {
pinctrl-0 = <&pmx_power_cpu>;
pinctrl-names = "default";
};
&rtc {
status = "disabled";
};
&sata {
nr-ports = <2>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hdd0_temp: sata-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
hdd1_temp: sata-port@1 {
reg = <1>;
#thermal-sensor-cells = <0>;
};
};
&sdio {
pinctrl-0 = <&sdio_pins2>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
broken-cd;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x02000000>; /* 32 MiB */
};
partition@2000000 {
label = "ubi";
reg = <0x02000000 0x1e000000>; /* 480 MiB */
};
};
};
};
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0xf0000>; /* 960 KiB*/
label = "u-boot";
read-only;
};
partition@f0000 {
reg = <0xf0000 0x10000>; /* 64 KiB */
label = "u-boot-env";
};
};
};
};
&pinctrl {
pmx_power_cpu: pmx-power-cpu {
marvell,pins = "mpp4";
marvell,function = "vdd";
};
pmx_power_usb: pmx-power-usb {
marvell,pins = "mpp5";
marvell,function = "gpo";
};
pmx_power_hdd1: pmx-power-hdd1 {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
pmx_power_hdd2: pmx-power-hdd2 {
marvell,pins = "mpp9";
marvell,function = "gpo";
};
pmx_fan_lock: pmx-fan-lock {
marvell,pins = "mpp10";
marvell,function = "gpio";
};
pmx_hdd_present: pmx-hdd-present {
marvell,pins = "mpp11", "mpp12";
marvell,function = "gpio";
};
pmx_fan_high: pmx-fan-high {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
pmx_fan_low: pmx-fan-low {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
pmx_buttons: pmx-buttons {
marvell,pins = "mpp15", "mpp16";
marvell,function = "gpio";
};
pmx_leds1: pmx-leds {
marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
marvell,function = "gpo";
};
pmx_leds2: pmx-leds {
marvell,pins = "mpp55", "mpp57", "mpp62";
marvell,function = "gpio";
};
pmx_pcie: pmx-pcie {
marvell,pins = "mpp56", "mpp60";
marvell,function = "pcie";
};
};

View File

@@ -0,0 +1,213 @@
/*
* Device Tree file for the Linksys WRT32X (Venom)
*
* Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT32X";
compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385",
"marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
append-rootblock = "root=/dev/mtdblock";
};
};
&expander0 {
wan_amber@0 {
label = "venom:amber:wan";
reg = <0x0>;
};
wan_blue@1 {
label = "venom:blue:wan";
reg = <0x1>;
};
usb2@5 {
label = "venom:blue:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "venom:blue:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "venom:blue:usb3_2";
reg = <0x7>;
};
wps_blue@8 {
label = "venom:blue:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "venom:amber:wps";
reg = <0x9>;
};
};
&gpio_leds {
power {
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
label = "venom:blue:power";
};
sata {
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
label = "venom:blue:sata";
};
wlan_2g {
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_2g";
};
wlan_5g {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_5g";
};
};
&gpio_leds_pins {
marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
};
&nand {
/* Spansion S34ML02G2 256MiB, OEM Layout */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x200000>; /* 2MB */
read-only;
};
partition@200000 {
label = "u_env";
reg = <0x200000 0x20000>; /* 128KB */
};
partition@220000 {
label = "s_env";
reg = <0x220000 0x40000>; /* 256KB */
};
partition@180000 {
label = "unused_area";
reg = <0x260000 0x5c0000>; /* 5.75MB */
};
partition@7e0000 {
label = "devinfo";
reg = <0x7e0000 0x40000>; /* 256KB */
read-only;
};
/* kernel1 overlaps with rootfs1 by design */
partition@900000 {
label = "kernel1";
reg = <0x900000 0x7b00000>; /* 123MB */
};
partition@f00000 {
label = "rootfs1";
reg = <0xf00000 0x7500000>; /* 117MB */
};
/* kernel2 overlaps with rootfs2 by design */
partition@8400000 {
label = "kernel2";
reg = <0x8400000 0x7b00000>; /* 123MB */
};
partition@8a00000 {
label = "rootfs2";
reg = <0x8a00000 0x7500000>; /* 117MB */
};
/* last MB is for the BBT, not writable */
partition@ff00000 {
label = "BBT";
reg = <0xff00000 0x100000>;
};
};
};
&pcie1 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&pcie2 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
no-1-8-v;
non-removable;
wp-inverted;
bus-width = <8>;
status = "okay";
};
&usb3_1_vbus {
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
&usb3_1_vbus_pins {
marvell,pins = "mpp44";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for ESPRESSObin-Ultra
* Copyright (C) 2019 Globalscale technologies, Inc.
*
* Jason Hung <jhung@globalscaletechnologies.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Ultra Board";
compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
"marvell,armada3710";
aliases {
/* for dsa slave device */
ethernet1 = &switch0port1;
ethernet2 = &switch0port2;
ethernet3 = &switch0port3;
ethernet4 = &switch0port4;
ethernet5 = &switch0port5;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_usb3_vbus>;
};
leds {
pinctrl-names = "default";
compatible = "gpio-leds";
/* No assigned functions to the LEDs by default */
led1 {
label = "ebin-ultra:blue:led1";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
led2 {
label = "ebin-ultra:green:led2";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led3 {
label = "ebin-ultra:red:led3";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
led4 {
label = "ebin-ultra:yellow:led4";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
};
};
&pcie0 {
status = "okay";
};
&sata {
status = "okay";
};
&sdhci0 {
status = "okay";
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x3e0000>;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <100000>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
};
&usb2 {
status = "okay";
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&mdio {
status = "okay";
extphy: ethernet-phy@0 {
reg = <1>;
};
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
switch0port1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
switch0port2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
switch0port3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy3>;
};
switch0port4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy4>;
};
switch0port5: port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
phy-mode = "sgmii";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@11 {
reg = <0x11>;
};
switch0phy2: switch0phy2@12 {
reg = <0x12>;
};
switch0phy3: switch0phy3@13 {
reg = <0x13>;
};
switch0phy4: switch0phy4@14 {
reg = <0x14>;
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-372x.dtsi"
/ {
model = "GL.iNet GL-MV1000";
compatible = "glinet,gl-mv1000", "marvell,armada3720";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
switch {
label = "switch";
linux,code = <BTN_0>;
gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
vpn {
label = "green:vpn";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
wan {
label = "green:wan";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led_power: power {
label = "green:power";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0xf0000>;
};
partition@f0000 {
label = "u-boot-env";
reg = <0Xf0000 0x8000>;
};
factory: partition@f8000 {
label = "factory";
reg = <0xf8000 0x8000>;
};
};
};
};
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
no-1-8-v;
vqmmc-supply = <&vcc_sd_reg1>;
status = "okay";
};
&sdhci0 {
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
marvell,pad-type = "fixed-1-8v";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_factory_0>;
nvmem-cell-names = "mac-address";
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_factory_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree file for Globalscale MOCHAbin
* Copyright (C) 2019 Globalscale technologies, Inc.
* Copyright (C) 2021 Sartura Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"
/ {
model = "Globalscale MOCHAbin";
compatible = "globalscale,mochabin", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &swport1;
ethernet4 = &swport2;
ethernet5 = &swport3;
ethernet6 = &swport4;
};
/* SFP+ 10G */
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
};
/* SFP 1G */
sfp_eth2: sfp-eth2 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c0>;
los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
};
};
/* microUSB UART console */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* eMMC */
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
non-removable;
/delete-property/ marvell,xenon-phy-slow-mode;
no-1-8-v;
};
&cp0_pinctrl {
cp0_uart0_pins: cp0-uart0-pins {
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
cp0_spi0_pins: cp0-spi0-pins {
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
marvell,function = "spi0";
};
cp0_spi1_pins: cp0-spi1-pins {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp0_i2c0_pins: cp0-i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c1";
};
pca9554_int_pins: pca9554-int-pins {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
cp0_rgmii1_pins: cp0-rgmii1-pins {
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
is31_sdb_pins: is31-sdb-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = "mpp9";
marvell,function = "gpio";
};
cp0_switch_pins: cp0-switch-pins {
marvell,pins = "mpp0", "mpp1";
marvell,function = "gpio";
};
cp0_phy_pins: cp0-phy-pins {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
};
/* mikroBUS UART */
&cp0_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_uart0_pins>;
};
/* mikroBUS SPI */
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
};
/* SPI-NOR */
&cp0_spi1{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x3e0000>;
read-only;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
/* mikroBUS, 1G SFP and GPIO expander */
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
sfp_gpio: pca9554@39 {
compatible = "nxp,pca9554";
pinctrl-names = "default";
pinctrl-0 = <&pca9554_int_pins>;
reg = <0x39>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/*
* IO0_0: SFP+_TX_FAULT
* IO0_1: SFP+_TX_DISABLE
* IO0_2: SFP+_PRSNT
* IO0_3: SFP+_LOSS
* IO0_4: SFP_TX_FAULT
* IO0_5: SFP_TX_DISABLE
* IO0_6: SFP_PRSNT
* IO0_7: SFP_LOSS
*/
};
};
/* IS31FL3199, mini-PCIe and 10G SFP+ */
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
clock-frequency = <100000>;
leds@64 {
compatible = "issi,is31fl3199";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&is31_sdb_pins>;
shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
reg = <0x64>;
led1_red: led@1 {
label = "red:led1";
reg = <1>;
led-max-microamp = <20000>;
};
led1_green: led@2 {
label = "green:led1";
reg = <2>;
};
led1_blue: led@3 {
label = "blue:led1";
reg = <3>;
};
led2_red: led@4 {
label = "red:led2";
reg = <4>;
};
led2_green: led@5 {
label = "green:led2";
reg = <5>;
};
led2_blue: led@6 {
label = "blue:led2";
reg = <6>;
};
led3_red: led@7 {
label = "red:led3";
reg = <7>;
};
led3_green: led@8 {
label = "green:led3";
reg = <8>;
};
led3_blue: led@9 {
label = "blue:led3";
reg = <9>;
};
};
};
&cp0_mdio {
status = "okay";
/* 88E1512 PHY */
eth2phy: ethernet-phy@1 {
reg = <1>;
sfp = <&sfp_eth2>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_phy_pins>;
reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
};
/* 88E6141 Topaz switch */
switch: switch@3 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_switch_pins>;
reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
swport1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
swport2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
swport3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
swport4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy1: swphy1@17 {
reg = <17>;
};
swphy2: swphy2@18 {
reg = <18>;
};
swphy3: swphy3@19 {
reg = <19>;
};
swphy4: swphy4@20 {
reg = <20>;
};
};
};
};
&cp0_ethernet {
status = "okay";
};
/* 10G SFP+ */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-r";
phys = <&cp0_comphy4 0>;
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
/* Topaz switch uplink */
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy0 1>;
fixed-link {
speed = <2500>;
full-duplex;
};
};
/* 1G SFP or 1G RJ45 */
&cp0_eth2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_rgmii1_pins>;
phy = <&eth2phy>;
phy-mode = "rgmii-id";
};
/* SMSC USB5434B hub */
&cp0_usb3_0 {
status = "okay";
phys = <&cp0_comphy1 0>;
phy-names = "cp0-usb3h0-comphy";
};
/* miniPCI-E USB */
&cp0_usb3_1 {
status = "okay";
};
&cp0_sata0 {
status = "okay";
/* 7 + 12 SATA connector (J24) */
sata-port@0 {
phys = <&cp0_comphy2 0>;
phy-names = "cp0-sata0-0-phy";
};
/* M.2-2250 B-key (J39) */
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
};
};
/* miniPCI-E (J5) */
&cp0_pcie2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_pcie_reset_pins>;
phys = <&cp0_comphy5 2>;
phy-names = "cp0-pcie2-x1-phy";
reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
};

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@@ -0,0 +1,319 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "iEi Puzzle-M901";
compatible = "iei,puzzle-m901",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy2 0>;
managed = "in-band-status";
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
managed = "in-band-status";
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy5 2>;
managed = "in-band-status";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
status = "okay";
num-lanes = <2>;
num-viewport = <8>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy2 0>;
managed = "in-band-status";
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
managed = "in-band-status";
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy5 2>;
managed = "in-band-status";
};
&cp1_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp1_comphy0 1>;
};
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
cp1_sfp_pins: sfp-pins {
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
marvell,function = "gpio";
};
};
};
&cp1_usb3_1 {
status = "okay";
phys = <&cp1_comphy3 1>;
phy-names = "usb";
};

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "iEi Puzzle-M902";
compatible = "iei,puzzle-m902",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
gpio5 = &cp2_gpio1;
gpio6 = &cp2_gpio2;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
ethernet6 = &cp2_eth0;
ethernet7 = &cp2_eth1;
ethernet8 = &cp2_eth2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
serial1 = &cp0_uart0;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy0: cp2_usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus0>;
};
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy1: cp2_usb3_phy1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus1>;
};
cp2_sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp2_sfpp0_i2c>;
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp0_comphy2 0>;
managed = "in-band-status";
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
managed = "in-band-status";
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy1 2>;
managed = "in-band-status";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
&cp0_i2c1 {
clock-frequency = <100000>;
};
/* SLM-1521-V2, CON6 */
&cp0_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp0_comphy0 1>;
};
};
&cp0_pcie2 {
status = "okay";
num-lanes = <1>;
num-viewport = <8>;
phys = <&cp0_comphy5 2>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
&cp0_usb3_1 {
status = "okay";
phys = <&cp0_comphy3 1>;
phy-names = "usb";
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp1_comphy2 0>;
managed = "in-band-status";
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
managed = "in-band-status";
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy1 2>;
managed = "in-band-status";
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
};
};
/*
* Instantiate the second connected CP115
*/
#define CP11X_NAME cp2
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp2_crypto {
status = "okay";
};
&cp2_ethernet {
status = "okay";
};
&cp2_xmdio {
status = "okay";
cp2_nbaset_phy0: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp2_nbaset_phy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp2_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
/* SLM-1521-V2, CON9 */
&cp2_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp2_comphy2 0>;
managed = "in-band-status";
};
&cp2_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy4 1>;
managed = "in-band-status";
};
&cp2_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy1 2>;
managed = "in-band-status";
};
&cp2_gpio1 {
status = "okay";
};
&cp2_gpio2 {
status = "okay";
};
&cp2_i2c0 {
clock-frequency = <100000>;
/* SLM-1521-V2 - U3 */
i2c-mux@72 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
cp2_sfpp0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* U12 */
cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
};
};
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2012-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-project.org
JFFS2_BLOCKSIZE = 128k
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
DEVICE_VARS += BOOT_SCRIPT UBOOT
KERNEL_LOADADDR := 0x00008000
define Build/boot-scr
rm -f $@-boot.scr
sed \
-e 's#@ROOT@#$(IMG_PART_SIGNATURE)#g' \
-e 's#@DTB@#$(firstword $(DEVICE_DTS))#g' \
$(BOOT_SCRIPT).bootscript > $@-new.bootscript
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $@-new.bootscript $@-boot.scr
endef
define Build/boot-img
rm -f $@.boot
mkfs.fat -C $@.boot $$(( $(CONFIG_TARGET_KERNEL_PARTSIZE) * 1024 ))
$(foreach dts,$(DEVICE_DTS), mcopy -i $@.boot $(KDIR)/image-$(dts).dtb ::$(dts).dtb;)
mcopy -i $@.boot $(IMAGE_KERNEL) ::$(KERNEL_NAME)
-mcopy -i $@.boot $@-boot.scr ::boot.scr
endef
define Build/boot-img-ext4
rm -fR $@.boot
mkdir -p $@.boot
$(foreach dts,$(DEVICE_DTS), $(CP) $(KDIR)/image-$(dts).dtb $@.boot/$(dts).dtb;)
$(CP) $(IMAGE_KERNEL) $@.boot/$(KERNEL_NAME)
-$(CP) $@-boot.scr $@.boot/boot.scr
make_ext4fs -J -L kernel -l $(CONFIG_TARGET_KERNEL_PARTSIZE)M $@.bootimg $@.boot
endef
define Build/buffalo-kernel-jffs2
rm -rf $(KDIR)/kernel_jffs2 $@.fakerd
mkdir -p $(KDIR)/kernel_jffs2
dd if=/dev/zero of=$@.fakerd bs=131008 count=1 conv=sync
$(STAGING_DIR_HOST)/bin/mkimage \
-T ramdisk -A $(LINUX_KARCH) -O linux -C gzip -n 'fake initrd' \
-d $@.fakerd $(KDIR)/kernel_jffs2/initrd.buffalo
cp $@ $(KDIR)/kernel_jffs2/uImage.buffalo
$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
--little-endian -v --squash-uids -q -f -n -x lzma -x rtime -m none \
--eraseblock=128KiB --pad=$(KERNEL_SIZE) -d $(KDIR)/kernel_jffs2 -o $@
rm -rf $(KDIR)/kernel_jffs2 $@.fakerd
endef
define Build/sdcard-img
SIGNATURE="$(IMG_PART_SIGNATURE)" \
./gen_mvebu_sdcard_img.sh $@ \
$(if $(UBOOT),$(STAGING_DIR_IMAGE)/$(UBOOT)) \
c $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
83 $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS)
endef
define Build/sdcard-img-ext4
SIGNATURE="$(IMG_PART_SIGNATURE)" \
./gen_mvebu_sdcard_img.sh $@ \
$(if $(UBOOT),$(STAGING_DIR_IMAGE)/$(UBOOT)) \
83 $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.bootimg \
83 $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS)
endef
define Build/omnia-medkit-initramfs
$(TAR) -c -T /dev/null -f $@
rm -rf $(dir $(IMAGE_KERNEL))boot
mkdir -p $(dir $(IMAGE_KERNEL))boot/boot/
cp $(KDIR)/zImage-initramfs $(dir $(IMAGE_KERNEL))boot/boot/zImage
cp $(KDIR)/image-$(DEVICE_DTS).dtb $(dir $(IMAGE_KERNEL))boot/boot/dtb
$(TAR) -rp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
--file=$@ -C $(dir $(IMAGE_KERNEL))boot/ .
endef
define Build/uDPU-firmware
(rm -fR $@-fw; mkdir -p $@-fw)
$(CP) $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-initramfs.itb $@-fw/recovery.itb
$(CP) $@-boot.scr $@-fw/boot.scr
$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-f $@-fw/rootfs.tgz -C $(TARGET_DIR) .
$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-f $@-fw/boot.tgz -C $@.boot .
$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-f $(KDIR_TMP)/$(DEVICE_IMG_PREFIX)-firmware.tgz -C $@-fw .
endef
define Device/Default
PROFILES := Default
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_DIR := $(DTS_DIR)
BOARD_NAME = $$(DEVICE_DTS)
KERNEL_NAME := zImage
KERNEL := kernel-bin | append-dtb | uImage none
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
UBINIZE_OPTS := -E 5
UBOOT :=
BOOT_SCRIPT :=
endef
define Device/Default-arm64
BOOT_SCRIPT := generic-arm64
DEVICE_DTS_DIR := $(DTS_DIR)/marvell
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
KERNEL_NAME := Image
KERNEL := kernel-bin
endef
define Device/NAND-128K
BLOCKSIZE := 128k
PAGESIZE := 2048
SUBPAGESIZE := 512
VID_HDR_OFFSET := 2048
endef
define Device/NAND-256K
BLOCKSIZE := 256k
PAGESIZE := 4096
endef
define Device/NAND-512K
BLOCKSIZE := 512k
PAGESIZE := 4096
endef
include $(SUBTARGET).mk
$(eval $(call BuildImage))

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# Standard Boot-Script
# use only well-known variable names provided by U-Boot Distro boot
# This script assumes that there is a boot partition,
# and that the root partition is always the next one.
# rootfs is always on the next partition
setexpr openwrt_rootpart ${distro_bootpart} + 1
# figure out partition uuid to pass to the kernel as root=
part uuid ${devtype} ${devnum}:${openwrt_rootpart} uuid
# generate bootargs (rootfs)
setenv bootargs ${bootargs} root=PARTUUID=${uuid} rootfstype=auto rootwait
# add console= option to bootargs, if any
if test -n "${console}"; then
setenv bootargs ${bootargs} console=${console}
fi
echo "Booting Linux with ${bootargs}"
load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} @DTB@.dtb
load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} zImage
bootz ${kernel_addr_r} - ${fdt_addr_r}

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define Device/glinet_gl-mv1000
$(call Device/Default-arm64)
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-MV1000
SOC := armada-3720
endef
TARGET_DEVICES += glinet_gl-mv1000
define Device/globalscale_espressobin
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := ESPRESSObin
DEVICE_VARIANT := Non-eMMC
DEVICE_ALT0_VENDOR := Marvell
DEVICE_ALT0_MODEL := Armada 3700 Community Board
DEVICE_ALT0_VARIANT := Non-eMMC
SOC := armada-3720
BOOT_SCRIPT := espressobin
endef
TARGET_DEVICES += globalscale_espressobin
define Device/globalscale_espressobin-emmc
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := ESPRESSObin
DEVICE_VARIANT := eMMC
DEVICE_ALT0_VENDOR := Marvell
DEVICE_ALT0_MODEL := Armada 3700 Community Board
DEVICE_ALT0_VARIANT := eMMC
SOC := armada-3720
BOOT_SCRIPT := espressobin
endef
TARGET_DEVICES += globalscale_espressobin-emmc
define Device/globalscale_espressobin-ultra
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := ESPRESSObin
DEVICE_VARIANT := Ultra
DEVICE_PACKAGES += kmod-i2c-pxa kmod-rtc-pcf8563
SOC := armada-3720
BOOT_SCRIPT := espressobin
endef
TARGET_DEVICES += globalscale_espressobin-ultra
define Device/globalscale_espressobin-v7
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := ESPRESSObin
DEVICE_VARIANT := V7 Non-eMMC
DEVICE_ALT0_VENDOR := Marvell
DEVICE_ALT0_MODEL := Armada 3700 Community Board
DEVICE_ALT0_VARIANT := V7 Non-eMMC
SOC := armada-3720
BOOT_SCRIPT := espressobin
endef
TARGET_DEVICES += globalscale_espressobin-v7
define Device/globalscale_espressobin-v7-emmc
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := ESPRESSObin
DEVICE_VARIANT := V7 eMMC
DEVICE_ALT0_VENDOR := Marvell
DEVICE_ALT0_MODEL := Armada 3700 Community Board
DEVICE_ALT0_VARIANT := V7 eMMC
SOC := armada-3720
BOOT_SCRIPT := espressobin
endef
TARGET_DEVICES += globalscale_espressobin-v7-emmc
define Device/marvell_armada-3720-db
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 3720 Development Board (DB-88F3720-DDR3)
DEVICE_DTS := armada-3720-db
endef
TARGET_DEVICES += marvell_armada-3720-db
define Device/methode_udpu
$(call Device/Default-arm64)
DEVICE_VENDOR := Methode
DEVICE_MODEL := micro-DPU (uDPU)
DEVICE_DTS := armada-3720-uDPU
KERNEL_LOADADDR := 0x00080000
KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
KERNEL_INITRAMFS_SUFFIX := .itb
DEVICE_PACKAGES += f2fs-tools fdisk kmod-i2c-pxa
DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(2)
IMAGES := firmware.tgz
IMAGE/firmware.tgz := boot-scr | boot-img-ext4 | uDPU-firmware | append-metadata
BOOT_SCRIPT := udpu
endef
TARGET_DEVICES += methode_udpu

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define Device/globalscale_mochabin
$(call Device/Default-arm64)
DEVICE_VENDOR := Globalscale
DEVICE_MODEL := MOCHAbin
SOC := armada-7040
endef
TARGET_DEVICES += globalscale_mochabin
define Device/marvell_armada7040-db
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 7040 Development Board
DEVICE_DTS := armada-7040-db
IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
endef
TARGET_DEVICES += marvell_armada7040-db
define Device/marvell_armada8040-db
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 8040 Development Board
DEVICE_DTS := armada-8040-db
IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
endef
TARGET_DEVICES += marvell_armada8040-db
define Device/marvell_macchiatobin-doubleshot
$(call Device/Default-arm64)
DEVICE_VENDOR := SolidRun
DEVICE_MODEL := MACCHIATObin
DEVICE_VARIANT := Double Shot
DEVICE_ALT0_VENDOR := SolidRun
DEVICE_ALT0_MODEL := Armada 8040 Community Board
DEVICE_ALT0_VARIANT := Double Shot
DEVICE_PACKAGES += kmod-i2c-mux-pca954x
DEVICE_DTS := armada-8040-mcbin
SUPPORTED_DEVICES := marvell,armada8040-mcbin-doubleshot marvell,armada8040-mcbin
endef
TARGET_DEVICES += marvell_macchiatobin-doubleshot
define Device/marvell_macchiatobin-singleshot
$(call Device/Default-arm64)
DEVICE_VENDOR := SolidRun
DEVICE_MODEL := MACCHIATObin
DEVICE_VARIANT := Single Shot
DEVICE_ALT0_VENDOR := SolidRun
DEVICE_ALT0_MODEL := Armada 8040 Community Board
DEVICE_ALT0_VARIANT := Single Shot
DEVICE_PACKAGES += kmod-i2c-mux-pca954x
DEVICE_DTS := armada-8040-mcbin-singleshot
SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
endef
TARGET_DEVICES += marvell_macchiatobin-singleshot
define Device/iei_puzzle-m901
$(call Device/Default-arm64)
DEVICE_VENDOR := iEi
DEVICE_MODEL := Puzzle-M901
SOC := cn9131
IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
endef
TARGET_DEVICES += iei_puzzle-m901
define Device/iei_puzzle-m902
$(call Device/Default-arm64)
DEVICE_VENDOR := iEi
DEVICE_MODEL := Puzzle-M902
SOC := cn9132
IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
endef
TARGET_DEVICES += iei_puzzle-m902

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# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2012-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-project.org
define Device/dsa-migration
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA
endef
define Device/kernel-size-migration
DEVICE_COMPAT_VERSION := 2.0
DEVICE_COMPAT_MESSAGE := Partition design has changed compared to older versions (up to 19.07) due to kernel size restrictions. \
Upgrade via sysupgrade mechanism is not possible, so new installation via factory style image is required.
endef
define Device/buffalo_ls421de
$(Device/NAND-128K)
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := LinkStation LS421DE
SUBPAGESIZE :=
KERNEL_SIZE := 33554432
FILESYSTEMS := squashfs ubifs
KERNEL := kernel-bin | append-dtb | uImage none | buffalo-kernel-jffs2
KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none
DEVICE_DTS := armada-370-buffalo-ls421de
DEVICE_PACKAGES := \
kmod-rtc-rs5c372a kmod-hwmon-gpiofan kmod-hwmon-drivetemp kmod-usb3 \
kmod-linkstation-poweroff kmod-md-raid0 kmod-md-raid1 kmod-md-mod \
kmod-fs-xfs mkf2fs e2fsprogs partx-utils
endef
TARGET_DEVICES += buffalo_ls421de
define Device/cznic_turris-omnia
DEVICE_VENDOR := CZ.NIC
DEVICE_MODEL := Turris Omnia
KERNEL_INSTALL := 1
SOC := armada-385
KERNEL := kernel-bin
KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
DEVICE_PACKAGES := \
mkf2fs e2fsprogs kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 \
wpad-basic-wolfssl kmod-ath9k kmod-ath10k-ct ath10k-firmware-qca988x-ct \
partx-utils kmod-i2c-mux-pca954x
IMAGES := $$(DEVICE_IMG_PREFIX)-sysupgrade.img.gz omnia-medkit-$$(DEVICE_IMG_PREFIX)-initramfs.tar.gz
IMAGE/$$(DEVICE_IMG_PREFIX)-sysupgrade.img.gz := boot-scr | boot-img | sdcard-img | gzip | append-metadata
IMAGE/omnia-medkit-$$(DEVICE_IMG_PREFIX)-initramfs.tar.gz := omnia-medkit-initramfs | gzip
DEVICE_IMG_NAME = $$(2)
SUPPORTED_DEVICES += armada-385-turris-omnia
BOOT_SCRIPT := turris-omnia
endef
TARGET_DEVICES += cznic_turris-omnia
define Device/globalscale_mirabox
$(Device/NAND-512K)
DEVICE_VENDOR := Globalscale
DEVICE_MODEL := Mirabox
SOC := armada-370
SUPPORTED_DEVICES += mirabox
endef
TARGET_DEVICES += globalscale_mirabox
define Device/kobol_helios4
DEVICE_VENDOR := Kobol
DEVICE_MODEL := Helios4
KERNEL_INSTALL := 1
KERNEL := kernel-bin
DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
SOC := armada-388
UBOOT := helios4-u-boot-spl.kwb
BOOT_SCRIPT := clearfog
endef
TARGET_DEVICES += kobol_helios4
define Device/linksys
$(Device/NAND-128K)
DEVICE_VENDOR := Linksys
DEVICE_PACKAGES := kmod-mwlwifi wpad-basic-wolfssl
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
append-ubi | pad-to $$$$(PAGESIZE)
KERNEL_SIZE := 6144k
endef
define Device/linksys_wrt1200ac
$(call Device/linksys)
$(Device/dsa-migration)
DEVICE_MODEL := WRT1200AC
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := Caiman
DEVICE_DTS := armada-385-linksys-caiman
DEVICE_PACKAGES += mwlwifi-firmware-88w8864
SUPPORTED_DEVICES += armada-385-linksys-caiman linksys,caiman
endef
TARGET_DEVICES += linksys_wrt1200ac
define Device/linksys_wrt1900acs
$(call Device/linksys)
$(Device/dsa-migration)
DEVICE_MODEL := WRT1900ACS
DEVICE_VARIANT := v1
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := WRT1900ACS
DEVICE_ALT0_VARIANT := v2
DEVICE_ALT1_VENDOR := Linksys
DEVICE_ALT1_MODEL := Shelby
DEVICE_DTS := armada-385-linksys-shelby
DEVICE_PACKAGES += mwlwifi-firmware-88w8864
SUPPORTED_DEVICES += armada-385-linksys-shelby linksys,shelby
endef
TARGET_DEVICES += linksys_wrt1900acs
define Device/linksys_wrt1900ac-v1
$(call Device/linksys)
$(Device/kernel-size-migration)
DEVICE_MODEL := WRT1900AC
DEVICE_VARIANT := v1
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := Mamba
DEVICE_DTS := armada-xp-linksys-mamba
DEVICE_PACKAGES += mwlwifi-firmware-88w8864
KERNEL_SIZE := 4096k
SUPPORTED_DEVICES += armada-xp-linksys-mamba linksys,mamba
endef
TARGET_DEVICES += linksys_wrt1900ac-v1
define Device/linksys_wrt1900ac-v2
$(call Device/linksys)
$(Device/dsa-migration)
DEVICE_MODEL := WRT1900AC
DEVICE_VARIANT := v2
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := Cobra
DEVICE_DTS := armada-385-linksys-cobra
DEVICE_PACKAGES += mwlwifi-firmware-88w8864
SUPPORTED_DEVICES += armada-385-linksys-cobra linksys,cobra
endef
TARGET_DEVICES += linksys_wrt1900ac-v2
define Device/linksys_wrt3200acm
$(call Device/linksys)
$(Device/dsa-migration)
DEVICE_MODEL := WRT3200ACM
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := Rango
DEVICE_DTS := armada-385-linksys-rango
DEVICE_PACKAGES += kmod-btmrvl kmod-mwifiex-sdio mwlwifi-firmware-88w8964
SUPPORTED_DEVICES += armada-385-linksys-rango linksys,rango
endef
TARGET_DEVICES += linksys_wrt3200acm
define Device/linksys_wrt32x
$(call Device/linksys)
$(Device/kernel-size-migration)
DEVICE_MODEL := WRT32X
DEVICE_ALT0_VENDOR := Linksys
DEVICE_ALT0_MODEL := Venom
DEVICE_DTS := armada-385-linksys-venom
DEVICE_PACKAGES += kmod-btmrvl kmod-mwifiex-sdio mwlwifi-firmware-88w8964
KERNEL_SIZE := 6144k
KERNEL := kernel-bin | append-dtb
SUPPORTED_DEVICES += armada-385-linksys-venom linksys,venom
endef
TARGET_DEVICES += linksys_wrt32x
define Device/marvell_a370-db
$(Device/NAND-512K)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 370 Development Board (DB-88F6710-BP-DDR3)
DEVICE_DTS := armada-370-db
SUPPORTED_DEVICES += armada-370-db
endef
TARGET_DEVICES += marvell_a370-db
define Device/marvell_a370-rd
$(Device/NAND-512K)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 370 RD (RD-88F6710-A1)
DEVICE_DTS := armada-370-rd
SUPPORTED_DEVICES += armada-370-rd
endef
TARGET_DEVICES += marvell_a370-rd
define Device/marvell_a385-db-ap
$(Device/NAND-256K)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 385 Development Board AP (DB-88F6820-AP)
DEVICE_DTS := armada-385-db-ap
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
append-ubi | pad-to $$$$(PAGESIZE)
KERNEL_SIZE := 8192k
SUPPORTED_DEVICES += armada-385-db-ap
endef
TARGET_DEVICES += marvell_a385-db-ap
define Device/marvell_a388-rd
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada 388 RD (RD-88F6820-AP)
DEVICE_DTS := armada-388-rd
IMAGES := firmware.bin
IMAGE/firmware.bin := append-kernel | pad-to 256k | append-rootfs | pad-rootfs
SUPPORTED_DEVICES := armada-388-rd marvell,a385-rd
endef
TARGET_DEVICES += marvell_a388-rd
define Device/marvell_axp-db
$(Device/NAND-512K)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada XP Development Board (DB-78460-BP)
DEVICE_DTS := armada-xp-db
SUPPORTED_DEVICES += armada-xp-db
endef
TARGET_DEVICES += marvell_axp-db
define Device/marvell_axp-gp
$(Device/NAND-512K)
DEVICE_VENDOR := Marvell
DEVICE_MODEL := Armada Armada XP GP (DB-MV784MP-GP)
DEVICE_DTS := armada-xp-gp
SUPPORTED_DEVICES += armada-xp-gp
endef
TARGET_DEVICES += marvell_axp-gp
define Device/plathome_openblocks-ax3-4
DEVICE_VENDOR := Plat'Home
DEVICE_MODEL := OpenBlocks AX3
DEVICE_VARIANT := 4 ports
SOC := armada-xp
SUPPORTED_DEVICES += openblocks-ax3-4
BLOCKSIZE := 128k
PAGESIZE := 1
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-to $$(BLOCKSIZE) | append-ubi
endef
TARGET_DEVICES += plathome_openblocks-ax3-4
define Device/solidrun_clearfog-base-a1
DEVICE_VENDOR := SolidRun
DEVICE_MODEL := ClearFog Base
KERNEL_INSTALL := 1
KERNEL := kernel-bin
DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
DEVICE_DTS := armada-388-clearfog-base armada-388-clearfog-pro
UBOOT := clearfog-u-boot-spl.kwb
BOOT_SCRIPT := clearfog
SUPPORTED_DEVICES += armada-388-clearfog-base
DEVICE_COMPAT_VERSION := 1.1
DEVICE_COMPAT_MESSAGE := Ethernet interface rename has been dropped
endef
TARGET_DEVICES += solidrun_clearfog-base-a1
define Device/solidrun_clearfog-pro-a1
$(Device/dsa-migration)
DEVICE_VENDOR := SolidRun
DEVICE_MODEL := ClearFog Pro
KERNEL_INSTALL := 1
KERNEL := kernel-bin
DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
DEVICE_DTS := armada-388-clearfog-pro armada-388-clearfog-base
UBOOT := clearfog-u-boot-spl.kwb
BOOT_SCRIPT := clearfog
SUPPORTED_DEVICES += armada-388-clearfog armada-388-clearfog-pro
endef
TARGET_DEVICES += solidrun_clearfog-pro-a1

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# Bootscript for Globalscale ESPRESSOBin Board
# Set distro variables if necessary for compability with downstream firmware
if test -z "${kernel_addr_r}"; then
setenv kernel_addr_r 0x7000000
fi
if test -z "${fdt_add_r}"; then
setenv fdt_addr_r 0x6f00000
fi
if test -z "${devtype}"; then
setenv devtype mmc
fi
if test -z "${devnum}"; then
if mmc dev 0; then
setenv devnum 0
elif mmc dev 1; then
setenv devnum 1
fi
fi
# figure out partition uuid to pass to the kernel as root=
part uuid ${devtype} ${devnum}:2 uuid
setenv console "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000"
setenv bootargs "root=PARTUUID=${uuid} rw rootwait ${console}"
echo "Booting Linux from ${devtype} ${devnum} with args: ${bootargs}"
load ${devtype} ${devnum}:1 ${fdt_addr_r} @DTB@.dtb
load ${devtype} ${devnum}:1 ${kernel_addr_r} Image
booti ${kernel_addr_r} - ${fdt_addr_r}

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#!/bin/sh
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Copyright (C) 2016 Josua Mayer
usage() {
echo "$0 <outfile> [<bootloader> <type_partitionN> <size_partitionN> <img_partitionN>]?"
}
# always require first 2 or 3 arguments
# then in pairs up to 8 more for a total of up to 4 partitions
if [ $# -lt 1 ] || [ $# -gt 14 ] || [ $((($# - 1) % 3)) -ne 0 ]; then
if [ $# -lt 2 ] || [ $# -gt 15 ] || [ $((($# - 2) % 3)) -ne 0 ]; then
usage
exit 1
else
BOOTLOADER="$2"
fi
fi
set -e
# parameters
OUTFILE="$1"; shift
if [ -n "$BOOTLOADER" ]; then
shift
fi
# generate image file
printf "Creating %s from /dev/zero: " "$OUTFILE"
dd if=/dev/zero of="$OUTFILE" bs=512 count=1 >/dev/null
printf "Done\n"
while [ "$#" -ge 3 ]; do
ptgen_args="$ptgen_args -t $1 -p $(($2 * 1024 + 256))"
parts="$parts$3 "
shift; shift; shift
done
head=16
sect=63
# create real partition table using fdisk
printf "Creating partition table: "
set $(ptgen -o "$OUTFILE" -h $head -s $sect -l 1024 -S 0x$SIGNATURE $ptgen_args)
printf "Done\n"
# install bootloader
if [ -n "$BOOTLOADER" ]; then
printf "Writing bootloader: "
dd of="$OUTFILE" if="$BOOTLOADER" bs=512 seek=1 conv=notrunc 2>/dev/null
printf "Done\n"
fi
i=1
while [ "$#" -ge 2 ]; do
img="${parts%% *}"
parts="${parts#* }"
printf "Writing %s to partition %i: " "$img" $i
(
cat "$img"
# add padding to avoid leaving behind old overlay fs data
dd if=/dev/zero bs=128k count=1 2>/dev/null
) | dd of="$OUTFILE" bs=512 seek=$(($1 / 512)) conv=notrunc 2>/dev/null
printf "Done\n"
i=$((i+1))
shift; shift
done

View File

@@ -0,0 +1,24 @@
setenv bootargs "root=PARTUUID=@ROOT@-02 rw rootwait"
if test -n "${console}"; then
setenv bootargs "${bootargs} ${console}"
fi
if mmc dev 0; then
setenv mmcdev 0
elif mmc dev 1; then
setenv mmcdev 1
fi
if test -n "${fdt_addr_r}"; then
setenv fdt_addr ${fdt_addr_r}
fi
if test -n "${kernel_addr_r}"; then
setenv kernel_addr ${kernel_addr_r}
fi
load mmc ${mmcdev}:1 ${fdt_addr} @DTB@.dtb
load mmc ${mmcdev}:1 ${kernel_addr} Image
booti ${kernel_addr} - ${fdt_addr}

View File

@@ -0,0 +1,32 @@
# Determine root device
setexpr rootpart ${distro_bootpart} + 1
if test ${devtype} = mmc -a ${devnum} = 0; then
setenv rootdev /dev/mmcblk0p${rootpart}
elif test ${devtype} = scsi -a ${devnum} = 0; then
setenv rootdev /dev/sda${rootpart}
else
# New U-Boot only
part uuid ${devtype} ${devnum}:${rootpart} uuid
setenv rootdev PARTUUID=${uuid}
fi
setenv bootargs earlyprintk console=ttyS0,115200 root=${rootdev} rootfstype=auto rootwait
# Load device tree and prepare for modification
load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} @DTB@.dtb
fdt addr ${fdt_addr_r}
fdt resize
# Enable SFP cage, if module is present
i2c dev 0
i2c mw 0x70 0.0 0xf
i2c read 0x71 0 1 0x00fffff1
setexpr.b mod_def0 *0x00fffff1 \& 0x10
if test ${mod_def0} -eq 0; then
fdt set /sfp status okay
fdt rm /soc/internal-regs/ethernet@34000 phy-handle
fdt set /soc/internal-regs/ethernet@34000 managed in-band-status
fi
# Load kernel and boot
load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} zImage
bootz ${kernel_addr_r} - ${fdt_addr_r}

View File

@@ -0,0 +1,38 @@
# Bootscript for Methode uDPU device
# Device and variables may vary between different revisions
# of device, so we need to make sure everything is set correctly.
# Set the LED's correctly
gpio clear 12; gpio clear 40; gpio clear 45;
# Find eMMC device,
if mmc dev 0; then
setenv mmcdev 0
setenv rootdev 'root=/dev/mmcblk0p3'
elif mmc dev 1; then
setenv mmcdev 1
setenv rootdev 'root=/dev/mmcblk1p3'
fi
# Set the variables if necessary
if test ${kernel_addr_r}; then
setenv kernel_addr_r 0x5000000
fi
if test ${fdt_add_r}; then
setenv fdt_addr_r 0x4f00000
fi
setenv console 'console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000'
setenv bootargs ${console} $rootdev rw rootwait
load mmc ${mmcdev}:1 ${fdt_addr_r} @DTB@.dtb
load mmc ${mmcdev}:1 ${kernel_addr_r} Image
booti ${kernel_addr_r} - ${fdt_addr_r}
# If the boot command fails, fallback to recovery image
echo '-- Boot failed, falling back to the recovery image --'
setenv bootargs $console
load mmc ${mmcdev}:2 ${kernel_addr_r} recovery.itb
bootm ${kernel_addr_r}

View File

@@ -0,0 +1,21 @@
define KernelPackage/linkstation-poweroff
SUBMENU:=$(OTHER_MENU)
DEPENDS:=@TARGET_mvebu
TITLE:=Buffalo LinkStation power off driver
KCONFIG:= \
CONFIG_POWER_RESET=y \
CONFIG_POWER_RESET_LINKSTATION \
CONFIG_POWER_RESET_QNAP=n
FILES:=$(LINUX_DIR)/drivers/power/reset/linkstation-poweroff.ko
AUTOLOAD:=$(call AutoLoad,31,linkstation-poweroff,1)
endef
define KernelPackage/linkstation-poweroff/description
This driver supports turning off some Buffalo LinkStations by
setting an output pin at the ethernet PHY to the correct state.
It also makes the device compatible with the WoL function.
Say Y here if you have a Buffalo LinkStation LS421D/E.
endef
$(eval $(call KernelPackage,linkstation-poweroff))

View File

@@ -0,0 +1,65 @@
From da57203dc7fd556fbb3f0ec7d7d7c0b0e893b386 Mon Sep 17 00:00:00 2001
From: Tomasz Maciej Nowak <tmn505@gmail.com>
Date: Tue, 10 Nov 2020 16:38:31 +0100
Subject: [PATCH] arm64: dts: mcbin-singleshot: add heartbeat LED
With board revision 1.3, SolidRun moved the power LED to the middle of
the board. In old place of power LED a GPIO controllable heartbeat LED
was added. This commit only touches Single Shot variant, since only this
variant is all revision 1.3.
Note:
This is slightly modified patch. Some boards could be placed in an
enclosure, so the LED18 is enabled by default, since that'll be the only
visible indicator that the board is operating.
Reported-by: Alexandra Alth <alexandra@alth.de>
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../marvell/armada-8040-mcbin-singleshot.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
@@ -5,6 +5,8 @@
* Device Tree file for MACCHIATOBin Armada 8040 community board platform
*/
+#include <dt-bindings/leds/common.h>
+
#include "armada-8040-mcbin.dtsi"
/ {
@@ -12,6 +14,20 @@
compatible = "marvell,armada8040-mcbin-singleshot",
"marvell,armada8040-mcbin", "marvell,armada8040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&cp0_led18_pins>;
+ pinctrl-names = "default";
+
+ led18 {
+ gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
};
&cp0_eth0 {
@@ -27,3 +43,10 @@
managed = "in-band-status";
sfp = <&sfp_eth1>;
};
+
+&cp0_pinctrl {
+ cp0_led18_pins: led18-pins {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+};

View File

@@ -0,0 +1,74 @@
From 018b88eee1a2efda26ed2f09aab33ccdc40ef18f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Sun, 15 Nov 2020 14:59:17 +0100
Subject: ARM: dts: turris-omnia: enable HW buffer management
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The buffer manager is available on Turris Omnia but needs to be
described in device-tree to be used.
Signed-off-by: Marek Behún <kabel@kernel.org>
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
(limited to 'arch/arm/boot/dts/armada-385-turris-omnia.dts')
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -84,12 +84,23 @@
};
};
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
/* Connected to 88E6176 switch, port 6 */
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <3>;
fixed-link {
speed = <1000>;
@@ -103,6 +114,9 @@
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <1>;
+ bm,pool-short = <3>;
fixed-link {
speed = <1000>;
@@ -115,6 +129,9 @@
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <3>;
};
&i2c0 {

View File

@@ -0,0 +1,37 @@
From 9ec25ef84832209a8326f9a71fe3ba14f4bcf301 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Sun, 15 Nov 2020 14:59:18 +0100
Subject: ARM: dts: turris-omnia: add comphy handle to eth2
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The eth2 controller on Turris Omnia is connected to SerDes. For SFP to
be able to switch between 1G and 2.5G modes the comphy link has to be
defined.
Signed-off-by: Marek Behún <kabel@kernel.org>
Fixes: f3a6a9f3704a ("ARM: dts: add description for Armada 38x ...")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -129,6 +129,7 @@
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
+ phys = <&comphy5 2>;
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;

View File

@@ -0,0 +1,61 @@
From d29b67c220caf5f4905e1f1576e71bcb6de4af9e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Sun, 15 Nov 2020 14:59:19 +0100
Subject: ARM: dts: turris-omnia: describe switch interrupt
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Describe switch interrupt for Turris Omnia so that the CPU does not have
to poll the switch. We also need to to set mpp45 pin to gpio function
for this.
Signed-off-by: Marek Behún <kabel@kernel.org>
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -261,13 +261,18 @@
/* Switch MV88E6176 at address 0x10 */
switch@10 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&swint_pins>;
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
- dsa,member = <0 0>;
+ dsa,member = <0 0>;
reg = <0x10>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -320,6 +325,11 @@
marvell,function = "gpio";
};
+ swint_pins: swint-pins {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
spi0cs0_pins: spi0cs0-pins {
marvell,pins = "mpp25";
marvell,function = "spi0";

View File

@@ -0,0 +1,90 @@
From add2d65962977caf23ca2fa21a2457d31b636574 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 16 Nov 2020 13:24:22 +0100
Subject: ARM: dts: turris-omnia: add SFP node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Turris Omnia has an SFP cage that, together with WAN PHY, is connected
to eth2 SerDes via a SerDes multiplexor. When a SFP module is present,
the multiplexor switches the SerDes signal from PHY to SFP.
Describe the SFP cage, but leave it disabled. Until phylink has support
for such configuration, we are leaving it to U-Boot to enable SFP and
disable WAN PHY at boot time depending on whether a SFP module is
present.
Signed-off-by: Marek Behún <kabel@kernel.org>
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King - ARM Linux admin <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 30 ++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -82,6 +82,24 @@
};
};
};
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c>;
+ tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <3000>;
+
+ /*
+ * For now this has to be enabled at boot time by U-Boot when
+ * a SFP module is present. Read more in the comment in the
+ * eth2 node below.
+ */
+ status = "disabled";
+ };
};
&bm {
@@ -126,10 +144,20 @@
/* WAN port */
&eth2 {
+ /*
+ * eth2 is connected via a multiplexor to both the SFP cage and to
+ * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
+ * a SFP module is present, as determined by the mode-def0 GPIO.
+ *
+ * Until kernel supports this configuration properly, in case SFP module
+ * is present, U-Boot has to enable the sfp node above, remove phy
+ * handle and add managed = "in-band-status" property.
+ */
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
phys = <&comphy5 2>;
+ sfp = <&sfp>;
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
@@ -195,7 +223,7 @@
/* routed to PCIe2 connector (CN62A) */
};
- i2c@4 {
+ sfp_i2c: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;

View File

@@ -0,0 +1,160 @@
From 91dd42d0e30fdbb250c61d1192af569f07e6ada4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Sun, 15 Nov 2020 14:59:21 +0100
Subject: ARM: dts: turris-omnia: add LED controller node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Linux now has incomplete support for the LED controller on Turris Omnia:
it can set brightness and colors for each LED.
The controller can also put these LEDs into HW controlled mode, in which
the LEDs are controlled by HW: for example the WAN LED is connected via
MCU to the WAN PHY LED pin.
The driver does not support these HW controlled modes yet, and on probe
puts the LEDs into SW controlled mode.
Add node describing the LED controller, but disable it for now.
Signed-off-by: Marek Behún <kabel@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 111 +++++++++++++++++++++++++-
1 file changed, 110 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
@@ -181,7 +182,115 @@
reg = <0>;
/* STM32F0 command interface at address 0x2a */
- /* leds device (in STM32F0) at address 0x2b */
+
+ led-controller@2b {
+ compatible = "cznic,turris-omnia-leds";
+ reg = <0x2b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * LEDs are controlled by MCU (STM32F0) at
+ * address 0x2b.
+ *
+ * The driver does not support HW control mode
+ * for the LEDs yet. Disable the LEDs for now.
+ *
+ * Also LED functions are not stable yet:
+ * - there are 3 LEDs connected via MCU to PCIe
+ * ports. One of these ports supports mSATA.
+ * There is no mSATA nor PCIe function.
+ * For now we use LED_FUNCTION_WLAN, since
+ * in most cases users have wifi cards in
+ * these slots
+ * - there are 2 LEDs dedicated for user: A and
+ * B. Again there is no such function defined.
+ * For now we use LED_FUNCTION_INDICATOR
+ */
+ status = "disabled";
+
+ multi-led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <2>;
+ };
+
+ multi-led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <1>;
+ };
+
+ multi-led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <3>;
+ };
+
+ multi-led@3 {
+ reg = <0x3>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <2>;
+ };
+
+ multi-led@4 {
+ reg = <0x4>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <1>;
+ };
+
+ multi-led@5 {
+ reg = <0x5>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_WAN;
+ };
+
+ multi-led@6 {
+ reg = <0x6>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <4>;
+ };
+
+ multi-led@7 {
+ reg = <0x7>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ };
+
+ multi-led@8 {
+ reg = <0x8>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ };
+
+ multi-led@9 {
+ reg = <0x9>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ };
+
+ multi-led@a {
+ reg = <0xa>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ };
+
+ multi-led@b {
+ reg = <0xb>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_POWER;
+ };
+ };
eeprom@54 {
compatible = "atmel,24c64";

View File

@@ -0,0 +1,52 @@
From 8ee4a5f4f40da60bb85e13d9dd218a3c9197e3e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Sun, 15 Nov 2020 14:59:22 +0100
Subject: ARM: dts: turris-omnia: update ethernet-phy node and handle name
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Use property name `phy-handle` instead of the deprecated `phy` to
connect eth2 to the PHY.
Rename the node from "phy@1" to "ethernet-phy@1", since "phy@1" is
incorrect according to device-tree bindings documentation.
Also remove the "ethernet-phy-id0141.0DD1" compatible string, it is not
needed. Kernel can read the PHY identifier itself.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -156,7 +156,7 @@
*/
status = "okay";
phy-mode = "sgmii";
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phys = <&comphy5 2>;
sfp = <&sfp>;
buffer-manager = <&bm>;
@@ -387,9 +387,9 @@
pinctrl-0 = <&mdio_pins>;
status = "okay";
- phy1: phy@1 {
+ phy1: ethernet-phy@1 {
status = "okay";
- compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
+ compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
marvell,reg-init = <3 18 0 0x4985>;

View File

@@ -0,0 +1,33 @@
From 5b2c7e0ae762fff2b172caf16b2766cc3e1ad859 Mon Sep 17 00:00:00 2001
From: Rui Salvaterra <rsalvaterra@gmail.com>
Date: Wed, 17 Feb 2021 15:30:38 +0000
Subject: ARM: dts: turris-omnia: fix hardware buffer management
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Hardware buffer management has never worked on the Turris Omnia, as the
required MBus window hadn't been reserved. Fix thusly.
Fixes: 018b88eee1a2 ("ARM: dts: turris-omnia: enable HW buffer management")
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Tested-by: Klaus Kudielka <klaus.kudielka@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -32,7 +32,8 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {

View File

@@ -0,0 +1,208 @@
From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
From: Adrian Panella <ianchi74@outlook.com>
Date: Thu, 9 Mar 2017 09:37:17 +0100
Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
The command-line arguments provided by the boot loader will be
appended to a new device tree property: bootloader-args.
If there is a property "append-rootblock" in DT under /chosen
and a root= option in bootloaders command line it will be parsed
and added to DT bootargs with the form: <append-rootblock>XX.
Only command line ATAG will be processed, the rest of the ATAGs
sent by bootloader will be ignored.
This is usefull in dual boot systems, to get the current root partition
without afecting the rest of the system.
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
This patch has been modified to be mvebu specific. The original patch
did not pass the bootloader cmdline on if no append-rootblock stanza
was found, resulting in blank cmdline and failure to boot.
Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
---
arch/arm/Kconfig | 11 ++++
arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
init/main.c | 16 +++++
3 files changed, 111 insertions(+), 1 deletion(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1780,6 +1780,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ bool "Append rootblock parsing bootloader's kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to a new device tree property: bootloader-args.
+ If there is a property "append-rootblock" in DT under /chosen
+ and a root= option in bootloaders command line it will be parsed
+ and added to DT bootargs with the form: <append-rootblock>XX.
+ Only command line ATAG will be processed, the rest of the ATAGs
+ sent by bootloader will be ignored.
+
endchoice
config CMDLINE
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -5,6 +5,8 @@
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
#define do_extend_cmdline 1
+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#define do_extend_cmdline 1
#else
#define do_extend_cmdline 0
#endif
@@ -69,6 +71,72 @@ static uint32_t get_cell_size(const void
return cell_size;
}
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+
+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
+{
+ char *ptr, *end;
+ char *root="root=";
+ int i, l;
+ const char *rootblock;
+
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
+ ptr = str - 1;
+
+ do {
+ //first find an 'r' at the begining or after a space
+ do {
+ ptr++;
+ ptr = strchr(ptr, 'r');
+ if (!ptr)
+ goto no_append;
+
+ } while (ptr != str && *(ptr-1) != ' ');
+
+ //then check for the rest
+ for(i = 1; i <= 4; i++)
+ if(*(ptr+i) != *(root+i)) break;
+
+ } while (i != 5);
+
+ end = strchr(ptr, ' ');
+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
+
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
+ ptr = end + 1;
+
+ /* if append-rootblock property is set use it to append to command line */
+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
+ if (rootblock == NULL)
+ goto no_append;
+
+ if (*dest != ' ') {
+ *dest = ' ';
+ dest++;
+ len++;
+ }
+
+ if (len + l + i <= COMMAND_LINE_SIZE) {
+ memcpy(dest, rootblock, l);
+ dest += l - 1;
+ memcpy(dest, ptr, i);
+ dest += i;
+ }
+
+ return dest;
+
+no_append:
+ len = strlen(str);
+ if (len + 1 < COMMAND_LINE_SIZE) {
+ memcpy(dest, str, len);
+ dest += len;
+ }
+
+ return dest;
+}
+#endif
+
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
{
char cmdline[COMMAND_LINE_SIZE];
@@ -88,12 +156,21 @@ static void merge_fdt_bootargs(void *fdt
/* and append the ATAG_CMDLINE */
if (fdt_cmdline) {
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //save original bootloader args
+ //and append ubi.mtd with root partition number to current cmdline
+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
+
+#else
len = strlen(fdt_cmdline);
if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
*ptr++ = ' ';
memcpy(ptr, fdt_cmdline, len);
ptr += len;
}
+#endif
}
*ptr = '\0';
@@ -168,7 +245,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
+ }
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ else if (atag->hdr.tag == ATAG_MEM) {
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
@@ -212,6 +291,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
+#else
+
+ }
+#endif
return fdt_pack(fdt);
}
--- a/init/main.c
+++ b/init/main.c
@@ -110,6 +110,10 @@
#include <kunit/test.h>
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#include <linux/of.h>
+#endif
+
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -903,6 +907,18 @@ asmlinkage __visible void __init __no_sa
page_alloc_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //Show bootloader's original command line for reference
+ if(of_chosen) {
+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
+ if(prop)
+ pr_notice("Bootloader command line (ignored): %s\n", prop);
+ else
+ pr_notice("Bootloader command line not present\n");
+ }
+#endif
+
/* parameters may set static keys */
jump_label_init();
parse_early_param();

View File

@@ -0,0 +1,10 @@
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -67,6 +67,7 @@ config MACH_ARMADA_38X
select HAVE_ARM_TWD if SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
+ select ARCH_WANT_LIBATA_LEDS
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 380/385 SoC with device tree.

View File

@@ -0,0 +1,770 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -212,11 +212,19 @@
&pcie1 {
/* Marvell 88W8864, 5GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ };
};
&pcie2 {
/* Marvell 88W8864, 2GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ };
};
&pinctrl {
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
+ CA =
+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ CN =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
+ ETSI =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
+ FCC =
+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
+ CN =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -157,6 +157,18 @@
};
};
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -225,12 +225,100 @@
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
+
+ ETSI =
+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
+
+ ETSI =
+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
+ };
+ };
};
};

View File

@@ -0,0 +1,17 @@
Newer Linksys boards might come with a Winbond W29N02GV which can be
configured in different ways. Make sure we configure it the same way
as the older chips so everything keeps working.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -148,6 +148,8 @@
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
marvell,nand-keep-config;
nand-on-flash-bbt;
};

View File

@@ -0,0 +1,15 @@
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -237,12 +237,10 @@
};
&i2c0 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};

View File

@@ -0,0 +1,19 @@
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -103,6 +103,16 @@
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0 0x400000>;
+ };
+
+ partition@1 {
+ label = "firmware";
+ reg = <0x400000 0xc00000>;
+ };
};
};

View File

@@ -0,0 +1,35 @@
From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Tue, 13 Jan 2015 11:14:09 +0100
Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -218,19 +218,19 @@
#size-cells = <1>;
partition@0 {
- label = "U-Boot";
+ label = "u-boot";
reg = <0x00000000 0x00800000>;
read-only;
};
partition@800000 {
- label = "uImage";
+ label = "kernel";
reg = <0x00800000 0x00400000>;
read-only;
};
partition@c00000 {
- label = "Root";
+ label = "ubi";
reg = <0x00c00000 0x3f400000>;
};
};

View File

@@ -0,0 +1,10 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -485,3 +485,7 @@
};
};
};
+
+&coherencyfab {
+ broken-idle;
+};

View File

@@ -0,0 +1,11 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -387,7 +387,7 @@
port@4 {
reg = <4>;
- label = "internet";
+ label = "wan";
};
port@5 {

View File

@@ -0,0 +1,50 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -14,6 +14,13 @@
compatible = "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -71,7 +78,7 @@
pinctrl-0 = <&gpio_leds_pins>;
pinctrl-names = "default";
- power {
+ led_power: power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -26,6 +26,13 @@
compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
"marvell,armadaxp", "marvell,armada-370-xp";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
@@ -197,7 +204,7 @@
pinctrl-0 = <&power_led_pin>;
pinctrl-names = "default";
- power {
+ led_power: power {
label = "mamba:white:power";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "on";

View File

@@ -0,0 +1,25 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -116,7 +116,7 @@
};
&eth2 {
- status = "okay";
+ status = "disabled";
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
@@ -200,10 +200,10 @@
label = "wan";
};
- port@5 {
- reg = <5>;
+ port@6 {
+ reg = <6>;
label = "cpu";
- ethernet = <&eth2>;
+ ethernet = <&eth0>;
fixed-link {
speed = <1000>;

View File

@@ -0,0 +1,68 @@
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -12,8 +12,8 @@
/ {
model = "Linksys WRT3200ACM";
- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -22,9 +22,10 @@
#include "armada-xp-mv78230.dtsi"
/ {
- model = "Linksys WRT1900AC";
- compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- "marvell,armadaxp", "marvell,armada-370-xp";
+ model = "Linksys WRT1900AC v1";
+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
+ "marvell,armadaxp-mv78230", "marvell,armadaxp",
+ "marvell,armada-370-xp";
aliases {
led-boot = &led_power;
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -9,8 +9,9 @@
#include "armada-385-linksys.dtsi"
/ {
- model = "Linksys WRT1900ACv2";
- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
+ model = "Linksys WRT1900AC v2";
+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -10,8 +10,8 @@
/ {
model = "Linksys WRT1200AC";
- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -10,7 +10,8 @@
/ {
model = "Linksys WRT1900ACS";
- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
+ compatible = "linksys,wrt1900acs", "linksys,shelby",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};

View File

@@ -0,0 +1,87 @@
From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 29 Nov 2016 10:15:45 +0000
Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "armada-388-clearfog.dtsi"
+#include "armada-38x-solidrun-microsom-emmc.dtsi"
/ {
model = "SolidRun Clearfog Base A1";
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/ {
+ soc {
+ internal-regs {
+ sdhci@d8000 {
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&microsom_sdhci_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ wp-inverted;
+ };
+ };
+ };
+};

View File

@@ -0,0 +1,28 @@
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -15,6 +15,13 @@
model = "Helios4";
compatible = "kobol,helios4", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
+
+ aliases {
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ };
memory {
device_type = "memory";
@@ -73,10 +80,9 @@
pinctrl-names = "default";
pinctrl-0 = <&helios_system_led_pins>;
- status-led {
+ led_status: status-led {
label = "helios4:green:status";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
default-state = "on";
};

View File

@@ -0,0 +1,34 @@
Certain SFP modules (most notably Nokia GPON ones) first check
connectivity on 1000base-x, and switch to 2500base-x afterwards. This
is considered a quirk so the phylink switches the interface to
2500base-x as well.
However, after power-cycling the uDPU device, network interface/SFP module
will not work correctly until the module is re-seated. This patch
resolves this issue by forcing the interface to be brought up in
2500base-x mode by default.
Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
@@ -162,7 +162,7 @@
};
&eth0 {
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
status = "okay";
managed = "in-band-status";
phys = <&comphy1 0>;
@@ -170,7 +170,7 @@
};
&eth1 {
- phy-mode = "sgmii";
+ phy-mode = "2500base-x";
status = "okay";
managed = "in-band-status";
phys = <&comphy0 1>;

View File

@@ -0,0 +1,37 @@
From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
From: Tad <tad@spotco.us>
Date: Fri, 5 Feb 2021 22:32:11 -0500
Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
partition to 4MB
Signed-off-by: Tad Davanzo <tad@spotco.us>
---
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -456,9 +456,9 @@
reg = <0xa00000 0x2800000>; /* 40MB */
};
- partition@d00000 {
+ partition@e00000 {
label = "rootfs1";
- reg = <0xd00000 0x2500000>; /* 37MB */
+ reg = <0xe00000 0x2400000>; /* 36MB */
};
/* kernel2 overlaps with rootfs2 by design */
@@ -467,9 +467,9 @@
reg = <0x3200000 0x2800000>; /* 40MB */
};
- partition@3500000 {
+ partition@3600000 {
label = "rootfs2";
- reg = <0x3500000 0x2500000>; /* 37MB */
+ reg = <0x3600000 0x2400000>; /* 36MB */
};
/*

View File

@@ -0,0 +1,29 @@
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -234,7 +234,7 @@
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
- marvell,crypto-sram-size = <0x7e0>;
+ marvell,crypto-sram-size = <0x800>;
};
};
@@ -255,12 +255,17 @@
* cpuidle workaround.
*/
idle-sram@0 {
+ status = "disabled";
reg = <0x0 0x20>;
};
};
};
};
+&coherencyfab {
+ broken-idle;
+};
+
/*
* Default UART pinctrl setting without RTS/CTS, can be overwritten on
* board level if a different configuration is used.

View File

@@ -0,0 +1,60 @@
The WRT1900AC among other Linksys routers uses a dual-firmware layout.
Dynamically rename the active partition to "ubi".
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
--- a/drivers/mtd/parsers/ofpart_core.c
+++ b/drivers/mtd/parsers/ofpart_core.c
@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
return of_get_property(pp, "compatible", NULL);
}
+static int mangled_rootblock;
+
static int parse_fixed_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
struct device_node *mtd_node;
struct device_node *ofpart_node;
const char *partname;
+ const char *owrtpart = "ubi";
struct device_node *pp;
int nr_parts, i, ret = 0;
bool dedicated = true;
@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct
parts[i].size = of_read_number(reg + a_cells, s_cells);
parts[i].of_node = pp;
- partname = of_get_property(pp, "label", &len);
- if (!partname)
- partname = of_get_property(pp, "name", &len);
+ if (mangled_rootblock && (i == mangled_rootblock)) {
+ partname = owrtpart;
+ } else {
+ partname = of_get_property(pp, "label", &len);
+ if (!partname)
+ partname = of_get_property(pp, "name", &len);
+ }
parts[i].name = partname;
if (of_get_property(pp, "read-only", &len))
@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi
return 0;
}
+static int __init active_root(char *str)
+{
+ get_option(&str, &mangled_rootblock);
+
+ if (!mangled_rootblock)
+ return 1;
+
+ return 1;
+}
+
+__setup("mangled_rootblock=", active_root);
+
static void __exit ofpart_parser_exit(void)
{
deregister_mtd_parser(&ofpart_parser);

View File

@@ -0,0 +1,38 @@
The hardware queue scheduling is apparently configured with fixed
priorities, which creates a nasty fairness issue where traffic from one
CPU can starve traffic from all other CPUs.
Work around this issue by forcing all tx packets to go through one CPU,
until this issue is fixed properly.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -4903,6 +4903,16 @@ static int mvneta_ethtool_set_eee(struct
return phylink_ethtool_set_eee(pp->phylink, eee);
}
+#ifndef CONFIG_ARM64
+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
+ struct net_device *sb_dev)
+{
+ /* XXX: hardware queue scheduling is broken,
+ * use only one queue until it is fixed */
+ return 0;
+}
+#endif
+
static const struct net_device_ops mvneta_netdev_ops = {
.ndo_open = mvneta_open,
.ndo_stop = mvneta_stop,
@@ -4913,6 +4923,9 @@ static const struct net_device_ops mvnet
.ndo_fix_features = mvneta_fix_features,
.ndo_get_stats64 = mvneta_get_stats64,
.ndo_do_ioctl = mvneta_ioctl,
+#ifndef CONFIG_ARM64
+ .ndo_select_queue = mvneta_select_queue,
+#endif
.ndo_bpf = mvneta_xdp,
.ndo_xdp_xmit = mvneta_xdp_xmit,
};

View File

@@ -0,0 +1,40 @@
From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat, 3 Oct 2015 09:13:05 +0100
Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
The cpuidle ->enter method expects the return value to be the sleep
state we entered. Returning negative numbers or other codes is not
permissible since coupled CPU idle was merged.
At least some of the mvebu_v7_cpu_suspend() implementations return the
value from cpu_suspend(), which returns zero if the CPU vectors back
into the kernel via cpu_resume() (the success case), or the non-zero
return value of the suspend actor, or one (failure cases).
We do not want to be returning the failure case value back to CPU idle
as that indicates that we successfully entered one of the deeper idle
states. Always return zero instead, indicating that we slept for the
shortest amount of time.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
ret = mvebu_v7_cpu_suspend(deepidle);
cpu_pm_exit();
+ /*
+ * If we failed to enter the desired state, indicate that we
+ * slept lightly.
+ */
if (ret)
- return ret;
+ return 0;
return index;
}

View File

@@ -0,0 +1,60 @@
From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Sat, 9 Jul 2016 10:58:16 +0100
Subject: pci: mvebu: time out reset on link up
If the port reports that the link is up while we are resetting, there's
little point in waiting for the full duration.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -933,6 +933,7 @@ static int mvebu_pcie_powerup(struct mve
if (port->reset_gpio) {
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
+ unsigned int i;
of_property_read_u32(port->dn, "reset-delay-us",
&reset_udelay);
@@ -940,7 +941,13 @@ static int mvebu_pcie_powerup(struct mve
udelay(100);
gpiod_set_value_cansleep(port->reset_gpio, 0);
- msleep(reset_udelay / 1000);
+ for (i = 0; i < reset_udelay; i += 1000) {
+ if (mvebu_pcie_link_up(port))
+ break;
+ msleep(1);
+ }
+
+ printk("%s: reset completed in %dus\n", port->name, i);
}
return 0;
@@ -1100,15 +1107,16 @@ static int mvebu_pcie_probe(struct platf
if (!child)
continue;
- ret = mvebu_pcie_powerup(port);
- if (ret < 0)
- continue;
-
port->base = mvebu_pcie_map_registers(pdev, child, port);
if (IS_ERR(port->base)) {
dev_err(dev, "%s: cannot map registers\n", port->name);
port->base = NULL;
- mvebu_pcie_powerdown(port);
+ continue;
+ }
+
+ ret = mvebu_pcie_powerup(port);
+ if (ret < 0) {
+ port->base = NULL;
continue;
}