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domenico
2025-06-24 13:14:22 +02:00
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448
target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device Tree file for Buffalo LinkStation LS421DE
*
* Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
*/
/dts-v1/;
#include "armada-370.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Buffalo LinkStation LS421DE";
compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp";
aliases {
led-boot = &led_boot;
led-failsafe = &led_failsafe;
led-running = &led_power;
led-upgrade = &led_upgrade;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
append-rootblock = "nullparameter="; /* override the bootloader args */
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
};
system_fan: gpio_fan {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
&gpio0 14 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
};
thermal-zones {
hdd-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
trips {
hdd_alert1: trip1 {
temperature = <36000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert2: trip2 {
temperature = <44000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert3: trip3 {
temperature = <52000>;
hysteresis = <2000>;
type = "passive";
};
hdd_crit: trip4 {
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&hdd_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&hdd_alert2>;
cooling-device = <&system_fan 2 2>;
};
map3 {
trip = <&hdd_alert3>;
cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
};
};
};
ethphy-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&ethphy0>;
trips {
ethphy_alert1: trip1 {
temperature = <65000>;
hysteresis = <4000>;
type = "passive";
};
ethphy_crit: trip2 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&ethphy_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
power {
label = "Power Switch";
linux,code = <KEY_POWER>;
linux,input-type = <EV_SW>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
function {
label = "Function Button";
linux,code = <KEY_CONFIG>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
system_red {
label = "ls421de:red:system";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
led_power: power_white {
label = "ls421de:white:power";
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_failsafe: power_red {
label = "ls421de:red:power";
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
led_upgrade: power_orange {
label = "ls421de:orange:power";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
led_boot: system_white {
label = "ls421de:white:system";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
hdd1_red {
label = "ls421de:red:hdd1";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata1";
};
hdd2_red {
label = "ls421de:red:hdd2";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata2";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;
pinctrl-names = "default";
usb_power: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "USB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
};
sata1_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "HDD1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
};
sata2_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "HDD2";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
};
&coherencyfab {
broken-idle;
};
&eth1 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
rs5c372a: rs5c372a@32 {
compatible = "ricoh,rs5c372a";
reg = <0x32>;
wakeup-source;
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
reg = <0>;
marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
<0x3 0x10 0x0000 0x1991>, /* LED function */
<0x3 0x11 0x0000 0x4401>, /* LED polarity */
<0x3 0x12 0x0000 0x4905>; /* LED timer */
#thermal-sensor-cells = <0>;
};
};
&pciec {
status = "okay";
pinctrl-0 = <&pmx_pcie>;
pinctrl-names = "default";
/* Connected to uPD720202 USB 3.0 Host */
pcie@1,0 {
status = "okay";
};
};
&pmsu {
pinctrl-0 = <&pmx_power_cpu>;
pinctrl-names = "default";
};
&rtc {
status = "disabled";
};
&sata {
nr-ports = <2>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hdd0_temp: sata-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
hdd1_temp: sata-port@1 {
reg = <1>;
#thermal-sensor-cells = <0>;
};
};
&sdio {
pinctrl-0 = <&sdio_pins2>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
broken-cd;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x02000000>; /* 32 MiB */
};
partition@2000000 {
label = "ubi";
reg = <0x02000000 0x1e000000>; /* 480 MiB */
};
};
};
};
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0xf0000>; /* 960 KiB*/
label = "u-boot";
read-only;
};
partition@f0000 {
reg = <0xf0000 0x10000>; /* 64 KiB */
label = "u-boot-env";
};
};
};
};
&pinctrl {
pmx_power_cpu: pmx-power-cpu {
marvell,pins = "mpp4";
marvell,function = "vdd";
};
pmx_power_usb: pmx-power-usb {
marvell,pins = "mpp5";
marvell,function = "gpo";
};
pmx_power_hdd1: pmx-power-hdd1 {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
pmx_power_hdd2: pmx-power-hdd2 {
marvell,pins = "mpp9";
marvell,function = "gpo";
};
pmx_fan_lock: pmx-fan-lock {
marvell,pins = "mpp10";
marvell,function = "gpio";
};
pmx_hdd_present: pmx-hdd-present {
marvell,pins = "mpp11", "mpp12";
marvell,function = "gpio";
};
pmx_fan_high: pmx-fan-high {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
pmx_fan_low: pmx-fan-low {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
pmx_buttons: pmx-buttons {
marvell,pins = "mpp15", "mpp16";
marvell,function = "gpio";
};
pmx_leds1: pmx-leds {
marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
marvell,function = "gpo";
};
pmx_leds2: pmx-leds {
marvell,pins = "mpp55", "mpp57", "mpp62";
marvell,function = "gpio";
};
pmx_pcie: pmx-pcie {
marvell,pins = "mpp56", "mpp60";
marvell,function = "pcie";
};
};

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target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-venom.dts Normal file
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/*
* Device Tree file for the Linksys WRT32X (Venom)
*
* Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT32X";
compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385",
"marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
append-rootblock = "root=/dev/mtdblock";
};
};
&expander0 {
wan_amber@0 {
label = "venom:amber:wan";
reg = <0x0>;
};
wan_blue@1 {
label = "venom:blue:wan";
reg = <0x1>;
};
usb2@5 {
label = "venom:blue:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "venom:blue:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "venom:blue:usb3_2";
reg = <0x7>;
};
wps_blue@8 {
label = "venom:blue:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "venom:amber:wps";
reg = <0x9>;
};
};
&gpio_leds {
power {
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
label = "venom:blue:power";
};
sata {
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
label = "venom:blue:sata";
};
wlan_2g {
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_2g";
};
wlan_5g {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_5g";
};
};
&gpio_leds_pins {
marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
};
&nand {
/* Spansion S34ML02G2 256MiB, OEM Layout */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x200000>; /* 2MB */
read-only;
};
partition@200000 {
label = "u_env";
reg = <0x200000 0x20000>; /* 128KB */
};
partition@220000 {
label = "s_env";
reg = <0x220000 0x40000>; /* 256KB */
};
partition@180000 {
label = "unused_area";
reg = <0x260000 0x5c0000>; /* 5.75MB */
};
partition@7e0000 {
label = "devinfo";
reg = <0x7e0000 0x40000>; /* 256KB */
read-only;
};
/* kernel1 overlaps with rootfs1 by design */
partition@900000 {
label = "kernel1";
reg = <0x900000 0x7b00000>; /* 123MB */
};
partition@f00000 {
label = "rootfs1";
reg = <0xf00000 0x7500000>; /* 117MB */
};
/* kernel2 overlaps with rootfs2 by design */
partition@8400000 {
label = "kernel2";
reg = <0x8400000 0x7b00000>; /* 123MB */
};
partition@8a00000 {
label = "rootfs2";
reg = <0x8a00000 0x7500000>; /* 117MB */
};
/* last MB is for the BBT, not writable */
partition@ff00000 {
label = "BBT";
reg = <0xff00000 0x100000>;
};
};
};
&pcie1 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&pcie2 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
no-1-8-v;
non-removable;
wp-inverted;
bus-width = <8>;
status = "okay";
};
&usb3_1_vbus {
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
&usb3_1_vbus_pins {
marvell,pins = "mpp44";
};

241
target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for ESPRESSObin-Ultra
* Copyright (C) 2019 Globalscale technologies, Inc.
*
* Jason Hung <jhung@globalscaletechnologies.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Ultra Board";
compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
"marvell,armada3710";
aliases {
/* for dsa slave device */
ethernet1 = &switch0port1;
ethernet2 = &switch0port2;
ethernet3 = &switch0port3;
ethernet4 = &switch0port4;
ethernet5 = &switch0port5;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_usb3_vbus>;
};
leds {
pinctrl-names = "default";
compatible = "gpio-leds";
/* No assigned functions to the LEDs by default */
led1 {
label = "ebin-ultra:blue:led1";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
led2 {
label = "ebin-ultra:green:led2";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led3 {
label = "ebin-ultra:red:led3";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
led4 {
label = "ebin-ultra:yellow:led4";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
};
};
&pcie0 {
status = "okay";
};
&sata {
status = "okay";
};
&sdhci0 {
status = "okay";
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x3e0000>;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <100000>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
};
&usb2 {
status = "okay";
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&mdio {
status = "okay";
extphy: ethernet-phy@0 {
reg = <1>;
};
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
switch0port1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
switch0port2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
switch0port3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy3>;
};
switch0port4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy4>;
};
switch0port5: port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
phy-mode = "sgmii";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@11 {
reg = <0x11>;
};
switch0phy2: switch0phy2@12 {
reg = <0x12>;
};
switch0phy3: switch0phy3@13 {
reg = <0x13>;
};
switch0phy4: switch0phy4@14 {
reg = <0x14>;
};
};
};
};

227
target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-372x.dtsi"
/ {
model = "GL.iNet GL-MV1000";
compatible = "glinet,gl-mv1000", "marvell,armada3720";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
switch {
label = "switch";
linux,code = <BTN_0>;
gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
vpn {
label = "green:vpn";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
wan {
label = "green:wan";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led_power: power {
label = "green:power";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0xf0000>;
};
partition@f0000 {
label = "u-boot-env";
reg = <0Xf0000 0x8000>;
};
factory: partition@f8000 {
label = "factory";
reg = <0xf8000 0x8000>;
};
};
};
};
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
no-1-8-v;
vqmmc-supply = <&vcc_sd_reg1>;
status = "okay";
};
&sdhci0 {
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
marvell,pad-type = "fixed-1-8v";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_factory_0>;
nvmem-cell-names = "mac-address";
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_factory_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

448
target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree file for Globalscale MOCHAbin
* Copyright (C) 2019 Globalscale technologies, Inc.
* Copyright (C) 2021 Sartura Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"
/ {
model = "Globalscale MOCHAbin";
compatible = "globalscale,mochabin", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &swport1;
ethernet4 = &swport2;
ethernet5 = &swport3;
ethernet6 = &swport4;
};
/* SFP+ 10G */
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
};
/* SFP 1G */
sfp_eth2: sfp-eth2 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c0>;
los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
};
};
/* microUSB UART console */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* eMMC */
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
non-removable;
/delete-property/ marvell,xenon-phy-slow-mode;
no-1-8-v;
};
&cp0_pinctrl {
cp0_uart0_pins: cp0-uart0-pins {
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
cp0_spi0_pins: cp0-spi0-pins {
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
marvell,function = "spi0";
};
cp0_spi1_pins: cp0-spi1-pins {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp0_i2c0_pins: cp0-i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c1";
};
pca9554_int_pins: pca9554-int-pins {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
cp0_rgmii1_pins: cp0-rgmii1-pins {
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
is31_sdb_pins: is31-sdb-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = "mpp9";
marvell,function = "gpio";
};
cp0_switch_pins: cp0-switch-pins {
marvell,pins = "mpp0", "mpp1";
marvell,function = "gpio";
};
cp0_phy_pins: cp0-phy-pins {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
};
/* mikroBUS UART */
&cp0_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_uart0_pins>;
};
/* mikroBUS SPI */
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
};
/* SPI-NOR */
&cp0_spi1{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x3e0000>;
read-only;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
/* mikroBUS, 1G SFP and GPIO expander */
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
sfp_gpio: pca9554@39 {
compatible = "nxp,pca9554";
pinctrl-names = "default";
pinctrl-0 = <&pca9554_int_pins>;
reg = <0x39>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/*
* IO0_0: SFP+_TX_FAULT
* IO0_1: SFP+_TX_DISABLE
* IO0_2: SFP+_PRSNT
* IO0_3: SFP+_LOSS
* IO0_4: SFP_TX_FAULT
* IO0_5: SFP_TX_DISABLE
* IO0_6: SFP_PRSNT
* IO0_7: SFP_LOSS
*/
};
};
/* IS31FL3199, mini-PCIe and 10G SFP+ */
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
clock-frequency = <100000>;
leds@64 {
compatible = "issi,is31fl3199";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&is31_sdb_pins>;
shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
reg = <0x64>;
led1_red: led@1 {
label = "red:led1";
reg = <1>;
led-max-microamp = <20000>;
};
led1_green: led@2 {
label = "green:led1";
reg = <2>;
};
led1_blue: led@3 {
label = "blue:led1";
reg = <3>;
};
led2_red: led@4 {
label = "red:led2";
reg = <4>;
};
led2_green: led@5 {
label = "green:led2";
reg = <5>;
};
led2_blue: led@6 {
label = "blue:led2";
reg = <6>;
};
led3_red: led@7 {
label = "red:led3";
reg = <7>;
};
led3_green: led@8 {
label = "green:led3";
reg = <8>;
};
led3_blue: led@9 {
label = "blue:led3";
reg = <9>;
};
};
};
&cp0_mdio {
status = "okay";
/* 88E1512 PHY */
eth2phy: ethernet-phy@1 {
reg = <1>;
sfp = <&sfp_eth2>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_phy_pins>;
reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
};
/* 88E6141 Topaz switch */
switch: switch@3 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_switch_pins>;
reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
swport1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
swport2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
swport3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
swport4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy1: swphy1@17 {
reg = <17>;
};
swphy2: swphy2@18 {
reg = <18>;
};
swphy3: swphy3@19 {
reg = <19>;
};
swphy4: swphy4@20 {
reg = <20>;
};
};
};
};
&cp0_ethernet {
status = "okay";
};
/* 10G SFP+ */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-r";
phys = <&cp0_comphy4 0>;
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
/* Topaz switch uplink */
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy0 1>;
fixed-link {
speed = <2500>;
full-duplex;
};
};
/* 1G SFP or 1G RJ45 */
&cp0_eth2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_rgmii1_pins>;
phy = <&eth2phy>;
phy-mode = "rgmii-id";
};
/* SMSC USB5434B hub */
&cp0_usb3_0 {
status = "okay";
phys = <&cp0_comphy1 0>;
phy-names = "cp0-usb3h0-comphy";
};
/* miniPCI-E USB */
&cp0_usb3_1 {
status = "okay";
};
&cp0_sata0 {
status = "okay";
/* 7 + 12 SATA connector (J24) */
sata-port@0 {
phys = <&cp0_comphy2 0>;
phy-names = "cp0-sata0-0-phy";
};
/* M.2-2250 B-key (J39) */
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
};
};
/* miniPCI-E (J5) */
&cp0_pcie2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_pcie_reset_pins>;
phys = <&cp0_comphy5 2>;
phy-names = "cp0-pcie2-x1-phy";
reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
};

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target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "iEi Puzzle-M901";
compatible = "iei,puzzle-m901",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy2 0>;
managed = "in-band-status";
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
managed = "in-band-status";
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy5 2>;
managed = "in-band-status";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
status = "okay";
num-lanes = <2>;
num-viewport = <8>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy2 0>;
managed = "in-band-status";
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
managed = "in-band-status";
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy5 2>;
managed = "in-band-status";
};
&cp1_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp1_comphy0 1>;
};
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
cp1_sfp_pins: sfp-pins {
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
marvell,function = "gpio";
};
};
};
&cp1_usb3_1 {
status = "okay";
phys = <&cp1_comphy3 1>;
phy-names = "usb";
};

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target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "iEi Puzzle-M902";
compatible = "iei,puzzle-m902",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
gpio5 = &cp2_gpio1;
gpio6 = &cp2_gpio2;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
ethernet6 = &cp2_eth0;
ethernet7 = &cp2_eth1;
ethernet8 = &cp2_eth2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
serial1 = &cp0_uart0;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy0: cp2_usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus0>;
};
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy1: cp2_usb3_phy1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus1>;
};
cp2_sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp2_sfpp0_i2c>;
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp0_comphy2 0>;
managed = "in-band-status";
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
managed = "in-band-status";
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy1 2>;
managed = "in-band-status";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
&cp0_i2c1 {
clock-frequency = <100000>;
};
/* SLM-1521-V2, CON6 */
&cp0_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp0_comphy0 1>;
};
};
&cp0_pcie2 {
status = "okay";
num-lanes = <1>;
num-viewport = <8>;
phys = <&cp0_comphy5 2>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
&cp0_usb3_1 {
status = "okay";
phys = <&cp0_comphy3 1>;
phy-names = "usb";
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp1_comphy2 0>;
managed = "in-band-status";
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
managed = "in-band-status";
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy1 2>;
managed = "in-band-status";
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
};
};
/*
* Instantiate the second connected CP115
*/
#define CP11X_NAME cp2
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp2_crypto {
status = "okay";
};
&cp2_ethernet {
status = "okay";
};
&cp2_xmdio {
status = "okay";
cp2_nbaset_phy0: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp2_nbaset_phy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp2_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
/* SLM-1521-V2, CON9 */
&cp2_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp2_comphy2 0>;
managed = "in-band-status";
};
&cp2_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy4 1>;
managed = "in-band-status";
};
&cp2_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy1 2>;
managed = "in-band-status";
};
&cp2_gpio1 {
status = "okay";
};
&cp2_gpio2 {
status = "okay";
};
&cp2_i2c0 {
clock-frequency = <100000>;
/* SLM-1521-V2 - U3 */
i2c-mux@72 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
cp2_sfpp0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* U12 */
cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
};
};
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
};
};